JBT6L77-AS TOSHIBA CMOS Digital Integrated Circuits Silicon Monolithic JBT6L77-AS Source Driver for TFT LCD Panels The JBT6L77-AS is a 64 gray-level and 240-channel-output source driver for TFT LCD panels. Grayscale data accepts 6-bit digital data inputs, which combined with the internal DA converter and 11 external power supplies, allows display of up to 260,000 colors. Based on high-speed CMOS, the JBT6L77-AS offers both low power consumption and high-speed operation. Features · Grayscale data : 18-bit digital (3 outputs × 6 bits) parallel transfer method, selectable write direction · Panel drive outputs : 240 outputs, 64 gray levels, DAC system, reference analog voltage inputs · High-speed operation : 30 MHz (max) · Power supply voltage : Digital power supply voltage ¼ 2.5 to 3.6 V Analog power supply voltage ¼ 5.0 ± 0.5 V · Operating temperature · Gate driver for TFT LCD panel : JBT6L78-AS : −20 to 75°C · Cascading multiple devices 1 2001-12-18 JBT6L77-AS Block Diagram U/D DI/O DO/I Shift register CPH DA0 to DA5 DB0 to DB5 Sampling register DC0 to DC5 LOAD Load register Control circuit block V0 to V10 DA converter Output circuit AVDD DVDD VSS TESTB SA1 SB1 SC1 SA80 SB80 SC80 2 2001-12-18 JBT6L77-AS PAD Layout Y (+) Chip size: 1.56 ´ 13.28 (mm) X (+) DUMMY SC1 SB80 SC80 SA80 DUMMY SA1 SB1 Output pad 240, 50 mm pitch, two-step zigzag allocation DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY Chip center (0,0) 11 11 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY VSS DC5 DC3 DC1 CPH DO/I TESTB V10 V8 V6 V4 V2 V0 DB4 DB2 DB0 DA4 DA2 DA0 TEG VSS TEG DC4 DC2 DC0 U/D LOAD DVDD V9 V7 V5 V3 V1 DB5 DB3 DB1 DA5 DA3 DA1 DI/O TEG AVDD Alignment mark 6 6 3 3 3 3 3 3 3 3 3 3 2 2 3 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 6 AVDD Alignment mark 6 : Cross point ◆ Alignment mark ◆ Output side dummy ◆ Output pins (SA1 to SC80) 40 60 40 60 40 60 ◆ Short-side dummy pins Pattern prohibited 50 30 30 30 40 30 30 30 45 90 90 45 50 50 50 50 50 50 20 20 50 90 100 90 40 ◆ Input pins (AVDD, VSS) 75 75 ◆ Input pins (V0 to V10, LOAD, TESTB) 40 75 45 40 45 40 70 20 70 70 20 20 3 50 90 45 35 35 20 50 90 45 20 50 45 90 45 20 37.5 37.5 ◆ Input pins (others) 45 50 90 45 40 ◆ Input pins (DVDD) 20 20 25 20 25 20 【Unit: mm】 2001-12-18 JBT6L77-AS PAD Coordinates Chip size: 13.28 ´ 1.56 (mm) Number of PAD: 396 [Unit: mm] No. Name X Point Y Point No. Name X Point Y Point No. Name X Point Y Point 1 AVDD -6307.5 -606 39 U/D -2495.0 -606 77 DB4 1135.0 -606 2 AVDD -6212.5 -606 40 DO/I -2335.0 -606 78 DB3 1295.0 -606 3 AVDD -6117.5 -606 41 DO/I -2265.0 -606 79 DB3 1365.0 -606 4 AVDD -6022.5 -606 42 DO/I -2195.0 -606 80 DB3 1435.0 -606 5 AVDD -5927.5 -606 43 LOAD -2050.0 -606 81 DB2 1595.0 -606 6 AVDD -5832.5 -606 44 LOAD -1990.0 -606 82 DB2 1665.0 -606 7 VSS -5657.5 -606 45 TESTB -1900.0 -606 83 DB2 1735.0 -606 8 VSS -5562.5 -606 46 TESTB -1840.0 -606 84 DB1 1895.0 -606 9 VSS -5467.5 -606 47 DVDD -1715.0 -606 85 DB1 1965.0 -606 10 VSS -5372.5 -606 48 DVDD -1625.0 -606 86 DB1 2035.0 -606 11 VSS -5277.5 -606 49 DVDD -1535.0 -606 87 DB0 2195.0 -606 12 VSS -5182.5 -606 50 V10 -1260.0 -606 88 DB0 2265.0 -606 13 TEG1 -5035.0 -606 51 V10 -1200.0 -606 89 DB0 2335.0 -606 14 TEG2 -4965.0 -606 52 V9 -1060.0 -606 90 DA5 2495.0 -606 15 TEG3 -4895.0 -606 53 V9 -1000.0 -606 91 DA5 2565.0 -606 16 DC5 -4735.0 -606 54 V8 -910.0 -606 92 DA5 2635.0 -606 17 DC5 -4665.0 -606 55 V8 -850.0 -606 93 DA4 2795.0 -606 18 DC5 -4595.0 -606 56 V7 -710.0 -606 94 DA4 2865.0 -606 19 DC4 -4435.0 -606 57 V7 -650.0 -606 95 DA4 2935.0 -606 20 DC4 -4365.0 -606 58 V6 -560.0 -606 96 DA3 3095.0 -606 21 DC4 -4295.0 -606 59 V6 -500.0 -606 97 DA3 3165.0 -606 22 DC3 -4135.0 -606 60 V5 -360.0 -606 98 DA3 3235.0 -606 23 DC3 -4065.0 -606 61 V5 -300.0 -606 99 DA2 3395.0 -606 24 DC3 -3995.0 -606 62 V4 -210.0 -606 100 DA2 3465.0 -606 25 DC2 -3835.0 -606 63 V4 -150.0 -606 101 DA2 3535.0 -606 26 DC2 -3765.0 -606 64 V3 -10.0 -606 102 DA1 3695.0 -606 27 DC2 -3695.0 -606 65 V3 50.0 -606 103 DA1 3765.0 -606 28 DC1 -3535.0 -606 66 V2 140.0 -606 104 DA1 3835.0 -606 29 DC1 -3465.0 -606 67 V2 200.0 -606 105 DA0 3995.0 -606 30 DC1 -3395.0 -606 68 V1 340.0 -606 106 DA0 4065.0 -606 31 DC0 -3235.0 -606 69 V1 400.0 -606 107 DA0 4135.0 -606 32 DC0 -3165.0 -606 70 V0 490.0 -606 108 DI/O 4295.0 -606 33 DC0 -3095.0 -606 71 V0 550.0 -606 109 DI/O 4365.0 -606 34 CPH -2935.0 -606 72 DB5 695.0 -606 110 DI/O 4435.0 -606 35 CPH -2865.0 -606 73 DB5 765.0 -606 111 TEG4 4595.0 -606 36 CPH -2795.0 -606 74 DB5 835.0 -606 112 TEG5 4665.0 -606 37 U/D -2635.0 -606 75 DB4 995.0 -606 113 TEG6 4735.0 -606 38 U/D -2565.0 -606 76 DB4 1065.0 -606 114 TEG7 4895.0 -606 4 2001-12-18 JBT6L77-AS [Unit: mm] No. Name X Point Y Point No. Name X Point Y Point No. Name X Point Y Point 115 TEG8 4965.0 -606 156 SB5 5326.0 481 197 SA19 3276.0 621 116 TEG9 5035.0 -606 157 SC5 5276.0 621 198 SB19 3226.0 481 117 VSS 5182.5 -606 158 SA6 5226.0 481 199 SC19 3176.0 621 118 VSS 5277.5 -606 159 SB6 5176.0 621 200 SA20 3126.0 481 119 VSS 5372.5 -606 160 SC6 5126.0 481 201 SB20 3076.0 621 120 VSS 5467.5 -606 161 SA7 5076.0 621 202 SC20 3026.0 481 121 VSS 5562.5 -606 162 SB7 5026.0 481 203 SA21 2976.0 621 122 VSS 5657.5 -606 163 SC7 4976.0 621 204 SB21 2926.0 481 123 AVDD 5832.5 -606 164 SA8 4926.0 481 205 SC21 2876.0 621 124 AVDD 5927.5 -606 165 SB8 4876.0 621 206 SA22 2826.0 481 125 AVDD 6022.5 -606 166 SC8 4826.0 481 207 SB22 2776.0 621 126 AVDD 6117.5 -606 167 SA9 4776.0 621 208 SC22 2726.0 481 127 AVDD 6212.5 -606 168 SB9 4726.0 481 209 SA23 2676.0 621 128 AVDD 6307.5 -606 169 SC9 4676.0 621 210 SB23 2626.0 481 129 DUMMY 6488.5 -439 170 SA10 4626.0 481 211 SC23 2576.0 621 130 DUMMY 6488.5 -339 171 SB10 4576.0 621 212 SA24 2526.0 481 131 DUMMY 6488.5 -239 172 SC10 4526.0 481 213 SB24 2476.0 621 132 DUMMY 6488.5 -139 173 SA11 4476.0 621 214 SC24 2426.0 481 133 DUMMY 6488.5 -39 174 SB11 4426.0 481 215 SA25 2376.0 621 134 DUMMY 6488.5 61 175 SC11 4376.0 621 216 SB25 2326.0 481 135 DUMMY 6488.5 161 176 SA12 4326.0 481 217 SC25 2276.0 621 136 DUMMY 6488.5 261 177 SB12 4276.0 621 218 SA26 2226.0 481 137 DUMMY 6488.5 361 178 SC12 4226.0 481 219 SB26 2176.0 621 138 DUMMY 6488.5 461 179 SA13 4176.0 621 220 SC26 2126.0 481 139 DUMMY 6488.5 561 180 SB13 4126.0 481 221 SA27 2076.0 621 140 DUMMY 6276.0 621 181 SC13 4076.0 621 222 SB27 2026.0 481 141 DUMMY 6176.0 621 182 SA14 4026.0 481 223 SC27 1976.0 621 142 DUMMY 6076.0 621 183 SB14 3976.0 621 224 SA28 1926.0 481 143 SA1 5976.0 621 184 SC14 3926.0 481 225 SB28 1876.0 621 144 SB1 5926.0 481 185 SA15 3876.0 621 226 SC28 1826.0 481 145 SC1 5876.0 621 186 SB15 3826.0 481 227 SA29 1776.0 621 146 SA2 5826.0 481 187 SC15 3776.0 621 228 SB29 1726.0 481 147 SB2 5776.0 621 188 SA16 3726.0 481 229 SC29 1676.0 621 148 SC2 5726.0 481 189 SB16 3676.0 621 230 SA30 1626.0 481 149 SA3 5676.0 621 190 SC16 3626.0 481 231 SB30 1576.0 621 150 SB3 5626.0 481 191 SA17 3576.0 621 232 SC30 1526.0 481 151 SC3 5576.0 621 192 SB17 3526.0 481 233 SA31 1476.0 621 152 SA4 5526.0 481 193 SC17 3476.0 621 234 SB31 1426.0 481 153 SB4 5476.0 621 194 SA18 3426.0 481 235 SC31 1376.0 621 154 SC4 5426.0 481 195 SB18 3376.0 621 236 SA32 1326.0 481 155 SA5 5376.0 621 196 SC18 3326.0 481 237 SB32 1276.0 621 5 2001-12-18 JBT6L77-AS [Unit: mm] No. Name X Point Y Point No. Name X Point Y Point No. Name X Point Y Point 238 SC32 1226.0 481 279 SB46 -824.0 621 320 SA60 -2874.0 481 239 SA33 1176.0 621 280 SC46 -874.0 481 321 SB60 -2924.0 621 240 SB33 1126.0 481 281 SA47 -924.0 621 322 SC60 -2974.0 481 241 SC33 1076.0 621 282 SB47 -974.0 481 323 SA61 -3024.0 621 242 SA34 1026.0 481 283 SC47 -1024.0 621 324 SB61 -3074.0 481 243 SB34 976.0 621 284 SA48 -1074.0 481 325 SC61 -3124.0 621 244 SC34 926.0 481 285 SB48 -1124.0 621 326 SA62 -3174.0 481 245 SA35 876.0 621 286 SC48 -1174.0 481 327 SB62 -3224.0 621 246 SB35 826.0 481 287 SA49 -1224.0 621 328 SC62 -3274.0 481 247 SC35 776.0 621 288 SB49 -1274.0 481 329 SA63 -3324.0 621 248 SA36 726.0 481 289 SC49 -1324.0 621 330 SB63 -3374.0 481 249 SB36 676.0 621 290 SA50 -1374.0 481 331 SC63 -3424.0 621 250 SC36 626.0 481 291 SB50 -1424.0 621 332 SA64 -3474.0 481 251 SA37 576.0 621 292 SC50 -1474.0 481 333 SB64 -3524.0 621 252 SB37 526.0 481 293 SA51 -1524.0 621 334 SC64 -3574.0 481 253 SC37 476.0 621 294 SB51 -1574.0 481 335 SA65 -3624.0 621 254 SA38 426.0 481 295 SC51 -1624.0 621 336 SB65 -3674.0 481 255 SB38 376.0 621 296 SA52 -1674.0 481 337 SC65 -3724.0 621 256 SC38 326.0 481 297 SB52 -1724.0 621 338 SA66 -3774.0 481 257 SA39 276.0 621 298 SC52 -1774.0 481 339 SB66 -3824.0 621 258 SB39 226.0 481 299 SA53 -1824.0 621 340 SC66 -3874.0 481 259 SC39 176.0 621 300 SB53 -1874.0 481 341 SA67 -3924.0 621 260 SA40 126.0 481 301 SC53 -1924.0 621 342 SB67 -3974.0 481 261 SB40 76.0 621 302 SA54 -1974.0 481 343 SC67 -4024.0 621 262 SC40 26.0 481 303 SB54 -2024.0 621 344 SA68 -4074.0 481 263 SA41 -24.0 621 304 SC54 -2074.0 481 345 SB68 -4124.0 621 264 SB41 -74.0 481 305 SA55 -2124.0 621 346 SC68 -4174.0 481 265 SC41 -124.0 621 306 SB55 -2174.0 481 347 SA69 -4224.0 621 266 SA42 -174.0 481 307 SC55 -2224.0 621 348 SB69 -4274.0 481 267 SB42 -224.0 621 308 SA56 -2274.0 481 349 SC69 -4324.0 621 268 SC42 -274.0 481 309 SB56 -2324.0 621 350 SA70 -4374.0 481 269 SA43 -324.0 621 310 SC56 -2374.0 481 351 SB70 -4424.0 621 270 SB43 -374.0 481 311 SA57 -2424.0 621 352 SC70 -4474.0 481 271 SC43 -424.0 621 312 SB57 -2474.0 481 353 SA71 -4524.0 621 272 SA44 -474.0 481 313 SC57 -2524.0 621 354 SB71 -4574.0 481 273 SB44 -524.0 621 314 SA58 -2574.0 481 355 SC71 -4624.0 621 274 SC44 -574.0 481 315 SB58 -2624.0 621 356 SA72 -4674.0 481 275 SA45 -624.0 621 316 SC58 -2674.0 481 357 SB72 -4724.0 621 276 SB45 -674.0 481 317 SA59 -2724.0 621 358 SC72 -4774.0 481 277 SC45 -724.0 621 318 SB59 -2774.0 481 359 SA73 -4824.0 621 278 SA46 -774.0 481 319 SC59 -2824.0 621 360 SB73 -4874.0 481 6 2001-12-18 JBT6L77-AS [Unit: mm] No. Name X Point Y Point 361 SC73 -4924.0 621 362 SA74 -4974.0 481 363 SB74 -5024.0 621 364 SC74 -5074.0 481 365 SA75 -5124.0 621 366 SB75 -5174.0 481 367 SC75 -5224.0 621 368 SA76 -5274.0 481 369 SB76 -5324.0 621 370 SC76 -5374.0 481 371 SA77 -5424.0 621 372 SB77 -5474.0 481 373 SC77 -5524.0 621 374 SA78 -5574.0 481 375 SB78 -5624.0 621 376 SC78 -5674.0 481 377 SA79 -5724.0 621 378 SB79 -5774.0 481 379 SC79 -5824.0 621 380 SA80 -5874.0 481 381 SB80 -5924.0 621 382 SC80 -5974.0 481 383 DUMMY -6024.0 621 384 DUMMY -6124.0 481 385 DUMMY -6224.0 621 386 DUMMY -6488.5 561 387 DUMMY -6488.5 461 388 DUMMY -6488.5 361 389 DUMMY -6488.5 261 390 DUMMY -6488.5 161 391 DUMMY -6488.5 61 392 DUMMY -6488.5 -39 393 DUMMY -6488.5 -139 394 DUMMY -6488.5 -239 395 DUMMY -6488.5 -339 396 DUMMY -6488.5 -439 ¾ Aligment mark 6464.0 -605 ¾ Aligment mark -6464.0 -605 7 2001-12-18 JBT6L77-AS Pin Function Pin Name I/O Function Data transfer enable pin These pins are used to input/output grayscale data. Input and output are switched as shown below according to the setting of the U/D pin. DI/O DO/I I/O U/D DI/O DO/I H Input Output L Output Input When set for input A high on DI/O or DO/I is latched into the internal logic synchronously with the rising edge of CPH. When the internal circuit is in standby state, the device is ready to transfer data. The grayscale data is latched in sequentially, starting at the next rise of CPH. When set for output The pin is used to transfer the enable signal to the JBT6L77-AS at the next stage of the LCD driver. The pin enters standby state after outputting a high. U/D I Transfer direction select pin This pin controls the direction in which the data is transferred into the sampling register. Data is transferred synchronously with each rising edge of CPH in one of the following sequences: When U/D is high, data is transferred in the order SA1 to SC1, SA2 to SC2, SA3 to SC3, … When U/D is low, the direction is reversed to give SA80 to SC80, SA79 to SC79, SA78 to SC78, … The voltage applied to this pin must be a DC-level voltage that is either high or low. CPH I Sampling clock input This clock input is used to transfer grayscale data. In sync with the rising edge of CPH, writes grayscale data bus data to the sampling register. I Grayscale data bus The data inputs consist of 6-bit word for each three channel that are transferred in parallel at the rising edge of CPH. The relationship between the grayscale data and the weight of each bit is as follows: Grayscale data = 32 ´ Dw5 + 16 ´ Dw4 + 8 ´ Dw3 + 4 ´ Dw2 + 2 ´ Dw1 + Dw0 (*) w = A, B, C LOAD I Data load input pin When a high voltage supplys to the load input, the data is transferred from the Sampling register to the Load register synchronously at the rising edge of CPH. (Note) After High level is input to this pin (LOAD), input CPH for at least three cycles in the same cycle as that for sampling. · When LOAD = Low level, output is at high impedance. · When LOAD = High level, output corresponds to grayscale data. V0 to V10 I Reference analog input pins These pins are used to input the voltage used for the DAC. VSS < V0 < = V1 < =…< = V9 < = V10 < AVDD or AVDD > V0 > = V1 > =…> = V9 > = V10 > VSS TESTB I Test pin Leave this pin open or VDD level. SA1 to SA80 SB1 to SB80 SC1 to SC80 O LCD panel drive pins DA0 to DA5 DB0 to DB5 DC0 to DC5 AVDD Analog power supply pin DVDD Digital power supply pin. VSS GND pin 8 2001-12-18 JBT6L77-AS Device Operation (1) Starting data transfer A high input to the data transfer enable pin (DI/O or DO/I) is latched into the internal logic synchronously with the rising edge of CPH, setting the device ready to transfer data. Data transfer starts at the next rise of CPH (see Timing diagram 1 and 2). (2) Data transfer method The data is latched in from the grayscale bus to the sampling register synchronously with each rising edge of CPH. Grayscale data for three outputs are latched into the device simultaneously in one transfer. Grayscale data are written as three outputs in parallel during one transfer. Data transfer completes after 80 transfers. Then the device enters Standby mode. Data written to the sampling register are the operation result of the grayscale data bus. (3) Terminating data transfer The data transfer enable pin (DO/I or DI/O) output goes high synchronously with the rising edge of CPH one clock period before the last data is latched in. It is held high until the next rise of CPH (see Timing diagram 1 and 2). The output from this pin can be connected directly as input to the data transfer enable pin (DI/O or DO/I) of the next stage LCD driver. In this way, multiple devices can be easily cascaded to drive a large screen. (4) Panel drive output When a high voltage supplies to the load input, the data in the sampling register is transferred to the load register and the device starts updating output to the LCD panel drive pins. 9 2001-12-18 JBT6L77-AS (5) Reference power supply circuit The connection between the device and the external reference power supply for Reference analog supply is configured with 1, 7 or 8 resistors in series (total of 63 resistor ladders). JBT6L77-AS R0 V0 V6 V7 V8 V9 V10 R7 to R14 R15 to R22 R23 to R30 R31 to R38 V5 R39 to R46 External power supply for reference voltage R47 to R54 V4 R55 to R61 V3 R62 V2 R1 to R6 V1 10 2001-12-18 JBT6L77-AS Resistor Name Resistance Value (W) Resistor Name Resistance Value (W) R0 6247 R32 62 R1 2186 R33 125 R2 1312 R34 125 R3 875 R35 125 R4 687 R36 187 R5 625 R37 62 R6 500 R38 125 R7 375 R39 125 R8 375 R40 125 R9 312 R41 125 R10 250 R42 125 R11 312 R43 125 R12 312 R44 187 R13 187 R45 125 R14 187 R46 125 R15 250 R47 125 R16 187 R48 187 R17 187 R49 125 R18 187 R50 187 R19 187 R51 125 R20 187 R52 187 R21 125 R53 187 R22 187 R54 187 R23 125 R55 250 R24 125 R56 187 R25 125 R57 312 R26 187 R58 312 R27 125 R59 375 R28 125 R60 437 R29 125 R61 687 R30 125 R62 6746 R31 187 11 2001-12-18 JBT6L77-AS (6) Grayscale data and output voltages The LCD drive output voltages are determined by the grayscale values and the 11 reverence analog inputs line voltages (V0 to V11). · Schematic representation of reference analog voltage inputs AVDD V0 V2 V3 V4 V5 V6 V7 V8 V9 V10 AVSS 00H 07H 0FH 17H 1FH 12 27H 2FH 37H 3EH 3FH 2001-12-18 JBT6L77-AS · Grayscale data and output voltages (Input voltage: V0 = 4.90 V, V10 = 0.10 V) (*) w = A, B, C Output Voltage Grayscale Data Dw5 Dw4 Dw3 Dw2 Dw1 Dw0 00H 0 0 0 0 0 0 V00H 01H 0 0 0 0 0 1 V01H 3.90 02H 0 0 0 0 1 0 V02H 3.55 03H 0 0 0 0 1 1 V03H 3.34 04H 0 0 0 1 0 0 V04H 3.20 05H 0 0 0 1 0 1 V05H 3.09 06H 0 0 0 1 1 0 V06H 2.99 07H 0 0 0 1 1 1 V07H 08H 0 0 1 0 0 0 V08H 2.85 09H 0 0 1 0 0 1 V09H 2.79 0AH 0 0 1 0 1 0 V0AH 2.74 0BH 0 0 1 0 1 1 V0BH 2.70 0CH 0 0 1 1 0 0 V0CH 2.65 0DH 0 0 1 1 0 1 V0DH 2.60 0EH 0 0 1 1 1 0 V0EH 2.57 0FH 0 0 1 1 1 1 V0FH 10H 0 1 0 0 0 0 V10H 2.50 11H 0 1 0 0 0 1 V11H 2.47 12H 0 1 0 0 1 0 V12H 2.44 13H 0 1 0 0 1 1 V13H 2.41 14H 0 1 0 1 0 0 V14H 2.38 15H 0 1 0 1 0 1 V15H 2.35 16H 0 1 0 1 1 0 V16H 2.33 17H 0 1 0 1 1 1 V17H 18H 0 1 1 0 0 0 V18H 2.28 19H 0 1 1 0 0 1 V19H 2.26 1AH 0 1 1 0 1 0 V1AH 2.24 1BH 0 1 1 0 1 1 V1BH 2.21 1CH 0 1 1 1 0 0 V1CH 2.19 1DH 0 1 1 1 0 1 V1DH 2.17 1EH 0 1 1 1 1 0 V1EH 2.15 1FH 0 1 1 1 1 1 V1FH 13 V0 V2 V3 V4 V5 4.90 2.91 2.54 2.30 2.13 2001-12-18 JBT6L77-AS (*) w = A, B, C Grayscale Data Dw5 Dw4 Dw3 Dw2 Dw1 Dw0 20H 1 0 0 0 0 0 V20H 2.10 21H 1 0 0 0 0 1 V21H 2.09 22H 1 0 0 0 1 0 V22H 2.07 23H 1 0 0 0 1 1 V23H 2.05 24H 1 0 0 1 0 0 V24H 2.03 25H 1 0 0 1 0 1 V25H 2.00 26H 1 0 0 1 1 0 V26H 1.99 27H 1 0 0 1 1 1 V27H 28H 1 0 1 0 0 0 V28H 1.95 29H 1 0 1 0 0 1 V29H 1.93 2AH 1 0 1 0 1 0 V2AH 1.91 2BH 1 0 1 0 1 1 V2BH 1.89 2CH 1 0 1 1 0 0 V2CH 1.87 2DH 1 0 1 1 0 1 V2DH 1.84 2EH 1 0 1 1 1 0 V2EH 1.82 2FH 1 0 1 1 1 1 V2FH 30H 1 1 0 0 0 0 V30H 1.78 31H 1 1 0 0 0 1 V31H 1.75 32H 1 1 0 0 1 0 V32H 1.73 33H 1 1 0 0 1 1 V33H 1.70 34H 1 1 0 1 0 0 V34H 1.68 35H 1 1 0 1 0 1 V35H 1.65 36H 1 1 0 1 1 0 V36H 1.62 37H 1 1 0 1 1 1 V37H 38H 1 1 1 0 0 0 V38H 1.55 39H 1 1 1 0 0 1 V39H 1.52 3AH 1 1 1 0 1 0 V3AH 1.47 3BH 1 1 1 0 1 1 V3BH 1.42 3CH 1 1 1 1 0 0 V3CH 1.36 3DH 1 1 1 1 0 1 V3DH 1.29 3EH 1 1 1 1 1 0 V3EH V9 1.18 3FH 1 1 1 1 1 1 V3FH V10 0.10 14 Output Voltage V6 V7 V8 1.97 1.80 1.59 2001-12-18 JBT6L77-AS Timing Diagrams 1 DI/O, DO/I (Input) 0 1 2 3 78 79 80 CPH (*) DA0 to DA5 SA1/ SA80 SA2/ SA79 SA3/ SA78 SA79/ SA2 SA80/ SA1 DB0 to DB5 SB1/ SB80 SB2/ SB79 SB3/ SB78 SB79/ SB2 SB80/ SB1 DC0 to DC5 SC1/ SC80 SC2/ SC79 SC3/ SC78 SC79/ SC2 SC80/ SC1 DO/I, DI/O (Output) (*) Upper stage: SA1 ® U/D = High Lower stage: SA80 ® U/D = Low Timing Diagrams 2 0 1 2 3 4 79 80 81 0 1 2 3 4 CPH DI/O, DO/I (Input) DI/O, DO/I (Output) DA0 to DA5 DB0 to DB5 DC0 to DC5 First data Last data First data at next stage LOAD SA1 to SA80 SB1 to SB80 SC1 to SC80 Hi-z Hi-z 15 2001-12-18 JBT6L77-AS Absolute Maximum Ratings (VSS = 0 V) Characteristics Symbol Rating Unit Analog supply voltage DVDD -0.3 to 6.5 V Digital supply voltage AVDD -0.3 to 6.5 V VIN -0.3 to DVDD + 0.3 V V (0:10) -0.3 to AVDD + 0.3 V Tstg -55 to 125 °C Input voltage Reference analog voltage Storage temperature Relevant Pin V0 to V10 Recommended Operating Conditions (VSS = 0 V) Symbol Test Condition Rating Unit Digital supply voltage DVDD ¾ 2.5 to 3.6 V Analog supply voltage AVDD ¾ 4.5 to 5.5 V V0 to V10 ¾ 0.1 to AVDD - 0.1 V Operating temperature Topr ¾ -20 to 75 °C Operating frequency fCPH ¾ DC to 30 MHz CPH ¾ pF/ CL 100 (max) SA1 to SA80 SB1 to SB80 SC1 to SC80 Characteristics Reference analog voltage-1 Output load capacitance (Note 1) PIN Relevant Pin Note 1: The following shows the relative magnitude of each reference analog voltage: < V3 = < V4 < < V6 = < V7 = < V8 < VSS = V0 < V1 < = V2 = = V5 = = V9 < V10 < AVDD or < V7 < < V5 = < V4 = < V3 = < V2 < VSS = V10 < V9 < = V8 = = V6 = = V1 < V0 < AVDD 16 2001-12-18 JBT6L77-AS Electrical Characteristics DC Characteristics (VSS = 0 V, DVDD = 2.5 to 3.6 V, AVDD = 4.5 V to 5.5 V, Ta = -20 to 75°C) Characteristics Low level Input current Symbol Test Circuit IILL1 IILL2 ¾ Test Condition Min Typ. Max ¾ ¾ ¾ 10 ¾ ¾ ¾ 400 High level IIH ¾ ¾ ¾ 10 Low level VIL ¾ 0 ¾ 0.2 ´ DVDD High level VIH ¾ 0.8 ´ DVDD ¾ DVDD Low level VOL 0 ¾ 0.5 High level VOH DVDD - 0.5 ¾ DVDD ¾ ¾ 10 ¾ 0.1 ¾ AVDD - 0.1 0.1 < = Reference analog voltage < = 1.2 -40 ¾ 40 1.2 < Reference analog voltage < = 4.9 -30 ¾ 30 During operations (Note 5) ¾ ¾ 4 When no, operations (Note 6) ¾ ¾ 3 During operations (Note 5) ¾ ¾ 8 When no, operations (Note 6) ¾ ¾ 8 LOAD = Low ¾ ¾ 100 ¾ Input voltage ¾ Output voltage Output off current Output voltage range IOH = -0.1 mA IOFF VOUT (Note 7) ¾ VDO1 ¾ Output voltage deviation VDO2 Current consumption (1) Current consumption (2) IOL = 0.1 mA DIDD AIDD ¾ ¾ Unit Relevant Pin (Note 2) mA TESTB (Note 3) V (Note 4) V DI/O, DO/I mA SA1 to SA80 SB1 to SB80 SC1 to SC80 mV mA DVDD mA (Note 7) AVDD mA Note 2: DA0 to DA5, DB0 to DB5, DC0 to DC5, DI/O, DO/I, CPH, LOAD, U/D Note 3: DA0 to DA5, DB0 to DB5, DC0 to DC5, DI/O, DO/I, CPH, LOAD, U/D, TESTB Note 4: DA0 to DA5, DB0 to DB5, DC0 to DC5, DI/O, DO/I, CPH, LOAD Note 5: DVDD = 3.6 V, AVDD = 5.5 V, fCPH = 30 MHz, 1H = 100 ms, no load, checkerboard pattern, LOAD = 1 ms at low level, typical value Note 6: AVDD = 5.5 V, fCPH = 30 MHz, 1H = 100 ms, DI/O: Fixed low Note 7: AVDD = 5.5 V, Standby at LOAD = Low, fCPH = 30 MHz, DI/O: Fixed low 17 2001-12-18 JBT6L77-AS AC Characteristics (VSS = 0 V, DVDD = 2.5 to 3.6 V, AVDD = 4.5 V to 5.5 V, Ta = -20 to 75°C) Symbol Test Circuit Test Condition Min Typ. Max Unit CPH pulse width H tCWH ¾ ¾ 4 ¾ ¾ ns CPH pulse width L tCWL ¾ ¾ 4 ¾ ¾ ns Enable setup time tsDI ¾ ¾ 4 ¾ ¾ ns Enable hold time thDI ¾ ¾ 0 ¾ ¾ ns Data setup time tsDD ¾ ¾ 4 ¾ ¾ ns Data hold time thDD ¾ ¾ 0 ¾ ¾ ns LOAD setup time tsLD ¾ ¾ 1 ¾ ¾ CPH LOAD hold time thLD ¾ ¾ 2 ¾ ¾ CPH LOAD pulse width H tLWH ¾ ¾ 10 ¾ ¾ ms LOAD pulse width L tLWL ¾ ¾ 1 ¾ ¾ ms Output delay time 1 tpdDO ¾ CL = 15 pF ¾ ¾ 15 ns Output delay time 2 tpdDX ¾ CL = 100 pF ¾ ¾ 10 ms Characteristics 18 2001-12-18 JBT6L77-AS DVDD ´ 0.8 DVDD ´ 0.8 CPH Last Last-1 tpdDO DO/I, DI/O (Output) tpdDO DVDD ´ 0.8 DVDD ´ 0.8 tsLD tLWH DVDD ´ 0.8 LOAD tCWH CPH Last-1 DVDD ´ 0.8 Last DVDD ´ 0.2 tsDD DW0 to DW5 W = A, B, C tCWL DVDD ´ 0.2 thDD DVDD ´ 0.2/ DVDD ´ 0.2 Valid DVDD ´ 0.8 Valid Last valid DVDD ´ 0.8 DVDD ´ 0.8 CPH thLD tLWL DVDD ´ 0.2 LOAD tsDI DI/O, DO/I (Input) thDI DVDD ´ 0.8 tpdDX tpdDX SA1 to SA80 SB1 to SB80 SC1 to SC80 19 2001-12-18 JBT6L77-AS RESTRICTIONS ON PRODUCT USE 000707EBM · TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. · The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. · Light striking a semiconductor device generates electromotive force due to photoelectric effects. In some cases this can cause the device to malfunction. This is especially true for devices in which the surface (back), or side of the chip is exposed. When designing circuits, make sure that devices are protected against incident light from external sources. Exposure to light both during regular operation and during inspection must be taken into account. · The products described in this document are subject to the foreign exchange and foreign trade laws. · The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. · The information contained herein is subject to change without notice. 20 2001-12-18