T6C24 TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC T6C24 ROW DRIVER LSI FOR A DOT MATRIX LCD The T6C24 is a row (common) driver LSI for a dot matrix LCD. The T6C24 generates the timing signals for the display using a built-in oscillator and also controls the T6C23 column (segment) LCD driver. The T6C24 features a low-impedance 240-output row driver. The T6C24 also includes internal resistors to divide the bias voltage, a power supply op-amp and a contrast control circuit. The T6C24 can be used in conjunction with the T6C23 to construct a low-power LCD system. Features l Dot matrix graphic LCD row driver l Built-in oscillator (additional external resistor) l Duty : 1/240 l Display OFF function VSS : /DSPOF = L, all LCD outputs = l Low power consumption l Logic power supply : 2.7 to 5.5 V l LCD power supply : 8.0 V to 30.0 V l CMOS process l Package : TCP (Tape Carrier Package) 1 2002-01-07 T6C24 Block Diagram Pin Assignment Note: The above diagram shows the pin configuration of the LSI chip; it does not show the configuration of the tape carrier package. 2 2002-01-07 T6C24 Pin Functions Pin Name Pin No. I/O 27 to 266 Output Row driver outputs CL 17 Output Shift clock pulse FP 19 Output Display synchronous signal FR 18 Output Frame signal COM1 to COM240 Functions Data flow direction select. Usually connected to VDD DIR 11 Input DIR DATA FLOW H COM1 → COM240 L COM240 → COM1 WFS 10 Input Frame signal inversion select. Usually connected to VDD. WFS = H: FR phase change per 13 lines. WFS = L: FR phase change per 17 lines. / DSPOF 16 Input Display off. Usually connected to VDD / DSPOF = H: Display−on mode, (COM1 to COM240) are operational. / DSPOF = L: Display−off mode, (COM1 to COM240) are at the VSS level. / RST 9 Input / RST = L: Reset state. Usually connected to VDD CPX 12 Input Crystal oscillation / CR oscillation Select CPX = L : CR oscillation CPX = H : Crystal oscillation or external clock input from CIN RIN 13 Input Connected to resistor for built-in oscillator CIN 15 Input Connected to crystal CKOUT 14 Output / TEST 8 Input VDD, VSS 7, 20 ― Power supply VCCL, VCCR VLC0L, VLC0R VLC1L, VLC1R VLC4L, VLC4R VLC5L, VLC5R HVSSL, HVSSR 1, 26 2, 25 3, 24 4, 23 5, 22 6, 21 ― Power supply for LCD drive Connected to resistor or crystal for built-in oscillator Test pin. Usually connected to VDD 3 2002-01-07 T6C24 Function of Each Block ● Oscillator The T6C24 has an on-chip oscillator (an external resistor is required). (1) CPX = L Rf fosc 390 kΩ 54 kHz 620 kΩ 34 kHz 780 kΩ 27 kHz Note: The resistor values are typical values. The oscillation frequency depends on how the device has been mounted. Hence Rf must be adjusted to achieve the target oscillation frequency. (2) CPX = H ● Timing generation circuit This circuit divides the oscillator frequency and generates the display timing signals (CL, FP and FR). ● Shift register 240-bit shift register 4 2002-01-07 T6C24 ● Row driver circuit and LCD voltage generation circuit The T6C24 has 240 row drivers and four different LCD drive output voltage levels. The display data from the latch circuit and the M signal determine which of the four LCD drive voltage is selected. The voltage generation circuit and row driver circuit are shown in the following diagram. Absolute Maximum Ratings (Ta = 25°C) Item Symbol Rating Unit Supply Voltage (1) VDD (Note 2) −0.3 to 7.0 V Supply Voltage (2) (Note 1, 2) −0.3 to 32.0 V Vin (Note 2, 3) −0.3 to VDD + 0.3 V Operating Temperature Topr −20 to 75 °C Storage Temperature Tstg −55 to 125 °C Input Voltage Note 1: Note 2: Note 3: Note 4: VCCL, VCCR, VLC0L, VLC0R, VLC1L, VLC1R, VLC4L, VLC4R, VLC5L and VLC5R Referenced to VSS, HVSSL and HVSSR Applies to all data bus and I / O pins. Ensure that the following condition is always maintained. VCCL / R ≥ VLC0L / R ≥ VLC1L / R ≥ VLC4L / R ≥ VLC5L / R ≥ HVSSL / R 5 2002-01-07 T6C24 Electrical Characteristics DC Characteristics Test Conditions (1) Unless Otherwise Noted, VSS = 0 V, VDD = 3.0 V ± 10%, VCCL / R = 23.0 V ± 10%, Ta = −20 to 75°C Item Symbol Test Circuit Test Condition Min Typ. Max Unit Operating Supply (1) VDD ― ― 2.7 ― 3.3 V VDD Operating Supply (2) VCC ― ― 8.0 ― 30.0 V VCCL, VCCR H Level VIH ― ― 0.7 VDD ― VDD V L Level VIL ― ― 0 ― 0.3 VDD V WFS, CPX, DIR, / DSPOF, / RST, / TEST H Level VOH ― IOH = −400 µA VDD − 0.4 ― ― V L Level VOL ― IOL = 400 µA VSS ― VSS +0.4 V Rrow ― (Note 5) Load voltage = output level of 0.5 V ― ― 1.5 kΩ COM1 to COM240 Input Leakage IIL ― VIN = VDD to GND −1 ― 1 µA WFS, CPX, DIR, / DSPOF, / RST, / TEST Current Consumption (1) ISS ― (Note 1) ― −35 −50 µA VDD Current Consumption (2) ICC ― (Note 2) ― 10 20 µA VCCL, VCCR VLC0L, VLC0R Current Consumption (3) IDOF ― (Note 3) ― 25 40 µA VSS, VSSL, VSSR VLC5L, VLC5R Current Consumption (4) ISTB ― (Note 4) −1 ― 1 µA VSS, VSSL, VSSR VLC5L, VLC5R Operating Freq. fosc ― ― 20 ― 100 kHz RIN, CIN External Clock Frequency fex ― ― 20 ― 100 kHz CIN External Clock Duty fduty ― ― 40 50 60 % CIN External Clock Rise / Fall Time tr / tf ― ― ― ― 50 ns CIN Input Voltage Output Voltage Row Driver Output Resistance Pin Name CL, FP, FR Note 1: Logic current : VDD = 3.0 V ± 10%, Ta = 25°C, Rf = 620 kΩ (33.6 kHz), no load Note 2: LCD driver current : VDD = 3.0 V ± 10%, VCCL / R = 23.0 V, Ta = 25°C, 1 / 13 bias, Rf = 620 kΩ, no load Note 3: Display-off current : VDD = 3.0 V ± 10%, VCCL / R = 23.0 V, Ta = 25°C, 1 / 13 bias, Rf = 620 kΩ, / DSPOF = L, no load Note 4: Standby current : VDD = 3.0 V ± 10%, VCCL / R = 23.0 V, Ta = 25°C, 1 / 13 bias, Rf = 620 kΩ, / RST = L, no load Note 5: VCCL / R = VLC0L / R = 23.0 V, VLC1L / R = VCC × 12 / 13, VLC4L / R = VCC × 1 / 13, HVSSL / R = VLC5L / R = 0 V 6 2002-01-07 T6C24 Test Conditions (2) Unless Otherwise Noted, VSS = 0 V, VDD = 5.0 V ± 10 , VCCL / R = 23.0 V ± 10 , Ta = −20 to 75°C Item Symbol Test Circuit Test Condition Min Typ. Max Unit Operating Supply (1) VDD ― ― 4.5 ― 5.5 V VDD Operating Supply (2) VCC ― ― 8.0 ― 30.0 V VCCL, VCCR H Level VIH ― ― 0.7 VDD ― VDD V L Level VIH ― ― 0 ― 0.3 VDD V WFS, CPX, DIR, / DSPOF, / RST, / TEST H Level VOH ― IOH = −400 µA VDD − 0.4 ― ― V L Level VOL ― IOL = 400 µA VSS ― VSS + 0.4 V Rrow ― (Note 5) Load voltage = output level of 0.5 V ― ― 1.5 kΩ COM1 to COM240 Input Leakage IIL ― VIN = VDD to GND −1 ― 1 µA WFS, CPX, DIR, / DSPOF, / RST, / TEST Current Consumption (1) ISS ― (Note 1) ― −60 −90 µA VDD Current Consumption (2) ICC ― (Note 2) ― 10 20 µA VCCL, VCCR VLC0L, VLC0R Current Consumption (3) IDOF ― (Note 3) ― 50 80 µA VSS, VSSL, VSSR VLC5L, VLC5R Current Consumption (4) ISTB ― (Note 4) −1 ― 1 µA VSS, VSSL, VSSR VLC5L, VLC5R Operating Freq. fosc ― ― 20 ― 100 kHz RIN, CIN External Clock Frequency fex ― ― 20 ― 100 kHz CIN External Clock Duty fduty ― ― 40 50 60 % CIN External Clock Rise / Fall Time tr / tf ― ― ― ― 50 ns CIN Input Voltage Output Voltage Row Driver Output Resistance Pin Name CL, FP, FR Note 1: Logic current : VDD = 5.0 V ± 10%, Ta = 25°C, Rf = 620 kΩ (33.6 kHz), no load Note 2: LCD driver current : VDD = 5.0 V ± 10%, VCCL / R = 23.0 V, Ta = 25°C, 1 / 13 bias, Rf = 620 kΩ, no load Note 3: Display-off current : VDD = 5.0 V ± 10%, VCCL / R = 23.0 V, Ta = 25°C, 1 / 13 bias, Rf = 620 kΩ, / DSPOF = L, no load Note 4: Standby current : VDD = 5.0 V ± 10%, VCCL / R = 23.0 V, Ta = 25°C, 1 / 13 bias, Rf = 620 kΩ, / RST = L, no load Note 5: VCCL / R = VLC0L / R = 23.0 V, VLC1L / R = VCC × 12 / 13, VLC4L / R = VCC × 1 / 13, HVSSL / R = VLC5L / R = 0 V 7 2002-01-07 T6C24 RESTRICTIONS ON PRODUCT USE 000707EBE · TOSHIBA is continually working to improve the quality and reliability of its products. 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