HD66503
(240-Channel Common Driver with Internal LCD
Timing Circuit)
Description
The HD66503 is a common driver for liquid crystal dot-matrix graphic display systems. This device
incorporates a 240 liquid crystal driver and an oscillator, and generates timing signals (alternating signals
and frame synchronizing signals) required for the liquid crystal display. It also achieves low current
consumption of 100 µA through the CMOS process. Combined with the HD66520, a 160-channel column
driver with an internal RAM, the HD66503 is optimal for use in displays for portable information tools.
Features
•
•
•
•
•
•
•
•
•
•
•
•
LCD timing generator: 1/120, 1/240 duty cycle internal generator
Alternating signal waveform generator: Pin programmable 2 to 63 line inversion
Recommended display duty cycle: 1/120, 1/240 (master mode): 1/120 to 1/240 (slave mode)
Number of LCD driver: 240
Power supply voltage: 2.7 to 5.5V
High voltage: 8 to 28-V LCD drive voltage
Low power consumption: 100 µA (during display)
Internal display off function
Oscillator circuit with standby function: 130 kHz (max)
Display timing operation clock: 65 kHz (max) (operating at 1/2 system clock)
Package: 272-pin TCP
CMOS process
Ordering Information
Type No.
TCP
Outer Lead Pitch (µm)
HD66503TA0
HD66503TB0
Straight TCP
Folding TCP
200
200
927
HD66503
Pin Arrangement
1
272
V2R
X239
2
271
V5R
X238
3
270
V6R
X237
4
269
V1R
X236
5
268
VEER
X235
6
267
VCC2
X234
7
266
M/S
X233
8
265
DOC
X232
9
264
FLM
X231
10
263
CL1
262
M
261
RESET
260
DISPOFF
259
DUTY
258
MEOR
257
MWS0
256
MWS1
255
MWS2
254
MWS3
253
MWS4
252
MWS5
251
SHL
Top View
X240
X10
231
250
GND
X9
232
249
C
X8
233
248
R
X7
234
247
CR
X6
235
246
VCC1
X5
236
245
VEEL
X4
237
244
V1L
X3
238
243
V6L
X2
239
242
V5L
X1
240
241
V2L
Note : This figure does not specify the tape carrier package dimensions.
928
HD66503
Pin Description
Classification
Symbol
Pin No.
Pin Name
I/O
Power
supply
VCC1,
VCC2
246
267
VCC
Power
supply
2
GND
250
GND
Power
supply
1
VEEL,
VEER
245
268
VEE
Power
supply
2
VCC–VEE: LCD drive circuits power supply
V1L, R
244
269
241
272
242
271
243
270
V1
Input
2
LCD drive level power supply
See Figure 1.
V2
Input
2
V5
Input
2
V6
Input
2
M/6
266
Master/slave Input
1
Controls the initiation and termination of
the LCD timing generator. In addition,
the input/output is determined of 4 signal
pins: display data transfer clock (CL1);
first line marker (FLM); alternating signal
(M); and display off control ('2&). See
Table 1 for details.
DUTY
259
Duty
Input
1
Selects the display duty cycle.
Low level: 1/120 display duty ratio
High level:
1/240 display duty ratio
MWS0 to
MWS5
257
256
255
254
253
252
MWS0
MWS1
MWS2
MWS3
MWS4
MWS5
Input
6
The number of line in the line alternating
waveform is set during master mode.
The number of lines can be set between
10 and 63.
When using the external alternating
signal or during slave mode, set the
number of lines to 0. See Table 2.
MEOR
258
M Exclusive- Input
OR
1
During master mode, the signals
alternating waveform output from pin M
is selected.
During low level, the line alternating
waveform is output from pin M.
During high level, pin M outputs an
EOR (exclusive OR) waveform between
a line alternating waveform and frame
alternating waveform. Set the pin to low
during slave mode. See Table 3.
V2L, R
V5L, R
V6L, R
Control
signals
Number
of Pins Functions
VCC–GND: logic power supply
929
HD66503
Classification
Control
signals
LCD
timing
930
Symbol
Pin No.
Pin Name
CR, R, C
247
248
249
CR
R
C
5(6(7
261
Reset
CL1
263
FLM
M
I/O
Number
of Pins Functions
3
These pins are used as shown in Figure
4 in master mode, and as shown in
Figure 5 in slave mode.
Input
1
Clock 1
I/O
1
The following initiation will be proceeded
by setting to initiation.
1) Stops the internal oscillator or the
external oscillator clock input.
2) Initializes the counters of the liquid
crystal display timing generator and
alternating signal (M) generator.
3) Set display off control output ('2&)
to low and turns off display.
After reset, display off control output
('2&) will stay low for four more frame
cycles (four clocks of FLM signals) to
prevent error display at initiation. The
electrical characteristics are shown in
Table 4. See Figure 2.
However, when reset is performed
during operation, RAM data in the
HD66520 which is used together with
the HD66503 may be destroyed.
Therefore, write data to the RAM again.
The bidirectional shift register shifts
data at the falling edge of CL1. During
master mode, this pin-outputs a data
transfer clock with a two times larger
cycle than the internal oscillator (or the
cycle of the external clock) with a duty
of 50%. During slave mode, this pin
inputs the external data transfer clock.
264
First line
marker
I/O
1
During master mode, pin FLM outputs
the first line marker. During slave mode,
this pin inputs the external data first line
marker. The shift direction of the first
line marker is determined by DUTY and
SHL signal as follows. Set signal DUTY
to high during slave mode. See Table 5.
262
M
I/O
1
Pin M inputs and outputs the alternating
signal of the LCD output.
HD66503
Classification
LCD
timing
LCD
drive
output
Symbol
Pin No.
Pin Name
I/O
Number
of Pins Functions
SHL
251
Shift left
Input
1
Pin SHL switches the shift direction of
the shift register. Refer to FLM for
details.
',632))
260
Display off
Input
1
'2&
Turns off the LCD.
During master mode, liquid crystal drive
output X1 to X240 can be set to level
V1 by setting the pin to low. By setting
the HD66520 to level V1 in the same
way, the data on the display can be
erased. During slave mode, set
',632)) high.
265
Display off
control
I/O
1
Controls the display-off function. During
master mode, pin '2& becomes an
output pin and controls display off after
reset and display off according to signal
',632)). In this case, connect this
signal to the HD66520’s pin ',632)).
During slave mode, pin '2& becomes
an input pin for display off control
signal. In this case, connect this signal
to the master HD66503’s pin '2&.
X1 to
X240
240
to 1
X1 to
X240
Output 240
Selects one from among four levels
(V1, V2, V5, and V6) depending on the
combination of M signal and display
data. See Figure 3.
Note: 30 input/outputs (excluding driver block)
931
HD66503
V1
V6
V5
V2
Figure 1 LCD Drive Levels
VCC
2.7V
treset
tr
0.8 VCC
RESET
0.2 VCC
Figure 2 Reset Pin Operation
M signal
1
0
Display data
1
0
1
0
Output level
V2
V6
V1
V5
Figure 3 LCD Drive Output
932
HD66503
Table 1
M/6 Signal Status
M/6
Mode
LCD Timing Generator
CL1, FLM, M, '2& Input/Output State
H
Master
1/120 or 1/240 duty cycle control
Output
L
Slave
Stop
Input
Table 2
MSW0 to MSW5 Signals Status
Number
of Lines MWS5
MWS4
MWS3
MWS2
MWS1
MWS0
Line Alternating
Waveform
Pin M State
0
0
0
0
0
0
0
—
Input
1
0
0
0
0
0
1
Disable
Output
2
0
0
0
0
1
0
2-line alternation
3 to 63
0 to 1
0 to 1
0 to 1
0 to 1
1 to 1
1 to 1
3-line alternation to
63-line alternation
Table 3
MEOR Signal Status
Mode
MEOR
Types of Alternating Waveforms Output by Pin M
Master
H
Line alternating waveform ⊕ frame alternating waveform
L
Line alternating waveform
L
—
Slave
Table 4
Power Supply Conditions
Item
Symbol
Min
Typ
Max
Unit
Reset time
treset
1.0
—
—
µs
Rise time
tr
—
—
200
ns
Table 5
FLM Status Control
Mode
DUTY
SHL
Shift Direction of First Line Marker
Master
H
H
X240 → X1
L
X1 → X240
H
X120 → X1, X240 → X121
L
X1 → X120, X121 → X240
H
X240 → X1
L
X1 → X240
L
Slave
H
933
HD66503
Internal Block Diagram
X1 to X240
V1L
V6L
V5L
V2L
V1R
V6R
V5R
V2R
LCD driver
MLS
D1 to D240
VEEL
VCC1
VEER
Level
shifter
Level shifter
VCC2
GND
L1 to L240
MP
Bidirectional shift register
CL1P
DUTYS
DOCP
SHLS
FLMP
RESET
FLMM
LCD timing
generator
CL1M
FLM1
CL1M
FLMM
AC switching signal
generator
MM
MW0
DOCM
CRP
MWS5S
to
MWS0S
Display off
controller
MEORS
DISPS
MSS
CR oscillator
CR
934
R
C
6
M/S switcher
CL1
FLM
M
DOC
M/S DUTY
MEOR
SHL
MWS5
DISPOFF
to MWS0
HD66503
1. CR Oscillator: The CR oscillator generates the HD66503 operation clock. During master mode, since
the operation clock is needed, connect oscillation resistor Rf with oscillation capacitor Cf as follows.
When the external clock is used, input external clock to pin CR and open pins C and R (Figure 4).
When using the HD66503 during slave mode, the operation clock will not be needed; therefore,
connect pin CR to VCC and open pins C and R (Figure 5).
2. Liquid Crystal Timing Generator: The liquid crystal timing generator creates various signals for the
LCD. During master mode (M/6 = VCC), the generator operates the HD66503’s internal circuitry as a
common internal driver using the generated LCD signals. In addition, signals CL1, M, and '2&
created by this generator can synchronously display data on a liquid crystal display by inputting them
into the RAM-provided segment driver HD66520 used together with HD66503. During slave mode
(M/6 = GND), this generator stops; the slave HD66503 operates based on signals CL1, M, '2&, and
FLM generated by the master HD66503.
3. M/6 Switcher: Controls the input and output of LCD signals CL1, FLM, M, and '2&.
This circuit outputs data when M/6 = VCC (master mode) and inputs data when M/6 = GND (slave
mode).
4. Alternating Signal Generator: Generates the alternating signal for the liquid crystal display. Since
the alternating signal decreases cross talk, it can alternate among 2 to 63 lines. The number of lines
are specified with pins MWS0 to MWS5 is set to either VCC or GND.
Moreover, the alternating signal can be externally input by grounding pins MWS0 to MWS5. In this
case, the alternating signal is input from pin M.
C
R
CR
C
CR
R
Rf
OPEN OPEN
External clock
Cf
Figure 4 Oscillator Connection in Master Mode
C
R
OPEN OPEN
CR
VCC
Figure 5 Oscillator Connection in Slave Mode
935
HD66503
5. Display Off Control Circuit: Controls display-off function by using external display off signal
',636 and automatic display off signal FLMM generated by the liquid crystal timing generator.
Automatic display off signal FLMM is an internal signal that is used to turn off the display in four
frames after signal reset is released. As a result, it is possible to turn off display using the display off
signal that is sent randomly from an external LSI and automatically prevent incorrect display after
reset release.
6. Bidirectional Shift Register: This is a 240-bit bidirectional shift register. This register can change the
shift direction using signal SHL. During master mode, the scan signal of the common driver can be
generated by sequentially shifting first line marker signal FLM generated internally. During slave
mode, a scan signal is generated by sequentially shifting first line marker signal FLM input from pin
FLM.
7. Level Shifter: Boosts the logic signal to a high voltage signal for the LCD.
8. LCD Drive Circuit: One of the LCD levels V1, V2, V5, and V6 are selected and output via pin X
according to the combination of the data in the bidirectional shift register and signal M.
Table 6
Output Level of LCD Circuit
Data in the Shift Register
M
Output Level
1
1
V2
0
1
V6
1
0
V1
0
0
V5
936
HD66503
Internal Function Description
1. Generation of Signals CL1 and FLM: Signal CL1 shifts the scanning signal of the common driver. It
is a 50% duty-ratio clock that changes level synchronously with the rising edge of oscillator clock
CR.
FLM is a clock signal that is output once every 240 CL1 clock cycles for a duty of 1/240 (DUTY =
VCC), and every 120 CL1 clock cycles for a duty of 1/120 (DUTY = GND).
2. Generation of Signal M: Signal M alternates current in the LCD. It alternates the current to decrease
cross talk after a certain number of lines ranging from 2 to 63 lines. The number of lines can be
specified with pins MWS0 to MWS5 by setting each pin to either VCC or GND (H or L). In addition,
when pin MEOR is connected to GND, signal M is a simple line alternating waveform, and when pin
MEOR is connected to VCC, signal M is an EOR (exclusive OR) of line alternating waveform and
frame alternating waveform.
CR
240
(120)
CL1
1
2
FLM
Figure 6 Generation of Signals CL1 and FLM
(When MWS0 to MWS5 = 6)
CL1
1
2
3
4
5
6
1
2
M
(MEOR = GND)
M
(MEOR = VCC)
FLM
Figure 7 Generation of Signal M
937
HD66503
3. Auto Display-Off Control: This functions prevents incorrect display after reset release. The display is
turned off four frames following after reset release. In addition, the display off control signal shown in
Figure 8 is output by pin '2&. This pin is connected to pin ',632)) of the HD66520.
RESET
FLM
1
2
3
4
5
DOC
Figure 8 Automatic Display-Off Control Function
938
6
HD66503
Application Example
Outline of HD66503 System Configuration
The HD66503 system configuration is outlined in Figures 9 and 10. Refer to the connection list (Table 7)
for connection details.
• When a single HD66503 is used to configure a small display (Figure 9)
• When two HD66503s are used to configure a large display (Figure 10)
HD66520
No. 1
LCD
No. 1
When using the internal oscillator
Refer to
connection list A
When using an external clock
Refer to
connection list D
COM1
to
COM240
Note: One HD66503 drives common signals and supplies timing signal to the HD66520.
Figure 9 When Using a Single HD66503
HD66520
LCD
COM1
No. 1
to
Upper
display
COM240
COM241
to
No. 2
Lower
display
No. 1
No. 2
When using the
internal oscillator
Refer to
connection list B
Refer to
connection list C
When using an
external clock
Refer to
connection list E
Refer to
connection list C
COM480
HD66520
Note: Upper and lower displays are driven by separate HD66503s to ensure display quality. No. 1 operates in master
mode, and No. 2 operates in slave mode.
Figure 10 When Using Two HD66503s
939
940
H
H
H
L
H
H
A
B
C
D
E
Sets the number
of lines for
alternating the
current
Sets the number
of lines for
alternating the
current
Sets the number
of lines for
alternating the
current
Sets the number
of lines for
alternating the
current
Sets the number
of lines for
alternating the
current
MWS0, MWS1,
MWS2, MWS3,
MWS4, MWS5
Notes: H = VCC (Fixed)
L = GND (Fixed)
“—” means “open”
Rf: Oscillation resistor
Cf: Oscillation capacitor
H
H
H
H
DUTY
H
H
L
H
H
MEOR
From
CPU or
external
reset
circuit
From
CPU or
external
reset
circuit
From
CPU or
external
reset
circuit
From
CPU or
external
reset
circuit
From
CPU or
external
reset
circuit
RESET
From
controller
From
controller
H
From
controller
From
controller
DISPOFF
—
Rf
Rf
R
From
—
external
oscillator
From
—
external
oscillator
H
Cf
Rf
Cf
Rf
CR
—
—
—
Cf
Cf
C
FLM
To FLM of
HD66520
HD66503
To FLM of
HD66520
M
To M of
HD66520
HD66503
To M of
HD66520
To CL1 of
HD66520
HD66503
To CL1 of
HD66520
To FLM of
HD66520
HD66503
To FLM of
HD66520
To M of
HD66520
HD66503
To M of
HD66520
From CL1
From FLM
From M of
of HD66503 of HD66503 HD66503
To CL1 of
HD66520
HD66503
To CL1 of
HD66520
CL1
DOC
H
To DISPOFF
of HD66520
COM240 to COM1
COM1 to COM240
COM240 to COM1
H
L
COM1 to COM240
COM480 to COM241
H
L
COM241 to COM480
COM240 to COM1
COM1 to COM240
COM240 to COM1
COM1 to COM240
L
H
L
H
L
SHL X1 to X240
To DOC of
HD66503
To DISPOFF
of HD66520
From DOC
of HD66503
T0 DISPOFF
of HD66520
To DOC of
HD66503
To DISPOFF
of HD66520
Table 7
Connection
Example
M/S
HD66503
HD66503 Connection List
HD66503 Connection List
HD66503
Example of System Configuration (1)
Figure 11 shows a system configuration for a 240 × 160-dot LCD panel using segment driver HD66520
with internal bit-map RAM. All required functions can be prepared for liquid crystal display with just two
chips except for liquid crystal display power supply circuit functions. Refer to Timing Chart (1) for
details.
SHL
LS1
LS0
240
seg1
seg2
160
HD66520
(ID No. 0)
LCD
com239
com240
Line scan direction
com1
com2
seg159
seg160
X1 , X2, X3,……… X240
LCD driver
3 FLM, CL1, M
/
1
/
DOC
DOC
HD66503
LCD display timing control circuit
DISPOFF
CR
R
C
DUTY SHL M/S
/ MWS0 to 5
6
/ MEOR
1
/ RESET
1
VCC
V1, V2, V5, V6
V1, V2, V3, V4
1
3
/
8
/
16
/
/
DISPOFF
A0 to A15
DB0 to DB7
CS, WE, OE
Power supply circuit
Figure 11 System Configuration (1)
941
HD66503
Example of System Configuration (2)
Figure 12 shows a system configuration for a 240 × 320-dot LCD panel using segment driver HD66520
with internal bit-map RAM. Refer to Timing Chart (1) for details.
SHL
LS1
LS0
240
seg1
seg2
HD66520
(ID No. 0)
LCD
320
seg159
seg160
HD66520
(ID No. 2)
seg161
seg162
com239
com240
Line scan direction
com1
com2
SHL
LS1
LS0
seg319
seg320
VCC
X1, X2, X3, ……… X240
3 FLM, CL1, M
/
1 DOC
/
LCD driver
HD66503
DOC
LCD display timing control circuit
DISPOFF
CR
R
C
DUTY SHL M/S
V1, V2, V5, V6
V1, V2, V3, V4
1
3
/
8
/
16
/
/
DISPOFF
A0 to A15
DB0 to DB7
CS, WE, OE
Power supply circuit
Figure 12 System Configuration (2)
942
/ MWS0 to 5
6
/ MEOR
1
/ RESET
1
VCC
V6 V5
X122
(COM122)
X240
V5
V6
V2
(COM240)
V6 V5
V6 V5
X121
(COM121)
X120
(COM120)
V6 V5 V1
2
X2
(COM2)
1
V6 V1 V5
240
10
10 lines
X1
(COM1)
FLM
CL1
CR
M
11
12
20
10 lines
21
22
V6 V5
V6 V5 V1
V6 V1 V5
V6 V2 V5
V6 V5
V6 V5
120 121 122
130 131 132
10 lines
140 141 142
10 lines
V6
240
V2
V6
V6
V6
V6
V6
1
V5
V5
V5
V5
V5 V1
V1 V5
2
HD66503
Timing Chart (1)
Figure 13 Timing Chart (1)
943
HD66503
Example of System Configuration (3)
Figure 14 shows a system configuration for a 320 × 480-dot LCD panel using segment driver HD66520
with internal bit-map RAM. Refer to Timing Chart (2) for details.
16/
8/
3/
A0 to A15
DB0 to DB7
CS, WE, OE
VCC
1
/
FLM, CL1, M 3
/
MWS0 to 5 / 6
MEOR
/1
DISPOFF / 1
RESET / 1
LS0
LS1
SHL
HD66520
(ID No.0)
HD66520
(ID No.2)
SHL
seg320
seg319
seg162
seg161
seg160
seg159
seg2
seg1
com1
com2
LCD
480
seg319
seg320
seg161
seg162
seg1
seg2
X1, X2, X3, ……… X240
MEOR
MWS0 to 5
FLM, CL1, M
DUTY SHL M/S
LCD driver
C
HD66503
Slave mode
R
DISPOFF
RESET
DOC
CR
OPEN
com479
com480
seg159
seg160
DUTY SHL M/S
Line scan cirection
C
LCD driver
HD66503
Master mode
R
X1, X2, X3, ……… X240
DOC
CR
OPEN
VCC
320
VCC
LS1
LS0
SHL
HD66520
(ID No.1)
VCC
HD66520
(ID No.3)
Power supply circuit
V1, V2, V3, V4
Figure 14 System Configuration (3)
944
LS0
320
com239
com240
com241
com242
V1, V2, V5, V6
LS1
LS0
LS1
SHL
480
HD66503 No. 1
V6 V5 V1
V6 V5 V1
V6 V1 V5
X480
V6 V2 V5
(COM480)
X242
(COM242)
X241
(COM241)
2
10
10 lines
V6 V1 V5
1
X240
V6 V2 V5
(COM240)
X2
(COM2)
X1
(COM1)
FLM
CL1
CR
M
11
12
20
10 lines
21
22
V6 V2 V5
V6 V5 V1
V6 V1 V5
V6 V2 V5
V6 V5 V1
V6 V1 V5
240 241 242
250 251 252
10 lines
260 261 262
10 lines
V6
V6
1
V5 V1
V5 V1
V1 V5
V6 V2 V5
V6
V6
2
V1 V5
V6 V2 V5
480
HD66503
Timing Chart (2)
HD66503 No. 2
Figure 15 Timing Chart (2)
945
HD66503
Power Supply Circuit
+3V
VCC1, VCC2
V1L, V1R
R1
V6L, V6R
R1
V3L, V3R
R2
V4L, V4R
R1
V5L, V5R
R1
V2L, V2R
VEEL, VEER
Contrast
–25V
GND
0V
Note: The values of R1 and R2 vary with the LCD panel used. When the bias factor is 1/15,
for example, the values of R1 and R2 can be determined as follows:
R1
4R1 + R2
=
1
15
If R1 = 3 kΩ, then R2 = 33 kΩ
Figure 16 Power Supply Circuit
946
HD66503
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
Notes
Logic circuit
VCC
–0.3 to +7.0
V
2
LCD drive circuit
VEE
VCC – 30.0 to VCC + 0.3
V
5
Input voltage (1)
VT1
–0.3 to VCC + 0.3
V
2, 3
Input voltage (2)
VT2
VEE – 0.3 to VCC + 0.3
V
4, 5
Operating temperature
Topr
–20 to +75
°C
Storage temperature
Tstg
–40 to +125
°C
Power voltage
Notes: 1. If the LSI is used beyond its absolute maximum rating, it may be permanently damaged. It
should always be used within the limits of its electrical characteristics in order to prevent
malfunction or unreliability.
2. Measured relative to GND (0V).
3. Applies to all input pins except for V1L, V1R, V2L, V2R, V5L, V5R, V6L, and V6R, and to
input/output pins in high-impedance state.
4. Applies to pins V1L, V1R, V2L, V2R, V5L, V5R, V6L, and V6R.
5. Apply the same voltage to pairs V1L and V1R, V2L and V2R, V5L and V5R, V6L and V6R, and
VEEL and VEER.
It is important to preserve the relationships VCC1 = VCC2 ≥ V1L = V1R ≥ V6L = V6R ≥ V5L = V5R
≥ V2L = V2R ≥ VEEL = VEER
947
HD66503
Electrical Characteristics
DC Characteristics (VCC = 2.7 to 5.5V, VCC–VEE = 8 to 28V, GND = 0V, Ta = –20 to +75°C)
Measurement
Condition
Item
Symbol
Min
Typ
Max
Unit
Input high level
voltage
VIH
0.8 VCC
—
VCC
V
1
Input low level
voltage
VIL
0
—
0.2 VCC
V
1
Output high
level voltage
VOH
VCC–0.4
—
—
V
IOH = –0.4 mA
2
Output low
level voltage
VOL
—
—
0.4
V
IOL = +0.4 mA
2
Driver “on”
resistance
RON
—
—
2.0
kΩ
VCC–VEE = 28V,
load current: ±150 µA
13, 14
Input leakage
current (1)
IIL1
–1.0
—
1.0
µA
VIN = 0 to VCC
1
Input leakage
current (2)
IIL2
–25
—
25
µA
VIN = VEE to VCC
3
Operating
frequency (1)
fopr1
10
—
200
kHz
Master mode
4
(external clock operation)
Operating
frequency (2)
fopr2
5
—
500
kHz
Slave mode
5
Oscillation
frequency (1)
fOSC1
70
100
130
kHz
Cf = 100 pF ±5%,
Rf = 51 kΩ ±2%
6, 12
Oscillation
frequency (2)
fOSC2
21
30
39
kHz
Cf = 100 pF ±5%,
Rf = 180 kΩ ±2%
6, 12
Power
IGND1
consumption (1)
—
—
80
µA
Master mode
1/240 duty cycle,
Cf = 100 pF,
Rf = 180 kΩ
VCC–GND = 3V,
VCC–VEE = 28V
7, 8
Power
IGND2
consumption (2)
—
—
20
µA
Master mode
7, 9
1/240 duty cycle external
clock
fopr1 = 30 kHz
VCC–GND = 3V,
VCC–VEE = 28V
Power
IGND3
consumption (3)
—
—
10
µA
Slave mode
1/240 duty cycle
during operation
fCL = 15 kHz
VCC–GND = 3V,
VCC–VEE = 28V
948
Notes
7, 10
HD66503
Item
Symbol
Min
Typ
Max
Unit
Power
consumption
IEE
—
—
20
µA
Measurement
Condition
Notes
Master mode
1/240 duty cycle,
Cf = 100 pF,
Rf = 180 kΩ
VCC–GND = 3V
VCC–VEE = 28V,
Notes: 1. Applies to input pins MEOR, MWS0 to MWS5, DUTY, SHL, ',632)), M/6,
and when inputting to input/output pins CL1, FLM, '2&, and M.
2. Applies when outputting from input/output pins CL1, FLM, '2&, and M.
3. Applies to V1L/R, V2L/R, V5L/R, and V6L/R. X1 to X240 are open.
4. Figure 17 shows the external clock specifications:
Duty =
TH
TL
External
clock
0.8VCC
0.5VCC
0.2VCC
trcp
OPEN OPEN
CR
R
C
tfcp
7, 11
5(6(7, and CR,
TH
× 100%
TH + TL
Min
Typ
Max
Duty
45
50
55
Unit
%
trcp
tfcp
—
—
—
—
50
50
ns
ns
Figure 17 External Clock
5. Regulates to operation frequency limits of the bidirectional shift register in the slavemode.
6. Connect resistance Rf and capacitance Cf as follows:
Cf
Rf
CR
R
C
Figure 18 Timing Components
7. Input and output currents are excluded. When a CMOS input is floating, excess current flows
from the power supply through to the input circuit. To avoid this, VIH and VIL must be held to
VCC and GND levels, respectively.
8. This value is specified for the current flowing through GND under the following conditions:
Internal oscillation circuit is used. Each terminal of MEOR, MWS0 to MWS5, DUTY, SHL,
',632)), M/6, and 5(6(7 is connected to VCC. Oscillator is set as described in note 6.
9. This value is specified for the current flowing through GND under the following conditions: Each
terminal of MEOR, MWS0 to MWS5, DUTY, SHL, ',632)), M/6, and 5(6(7 is connected to
VCC. Oscillator is set as described in note 4.
949
HD66503
10. This value is specified for the current flowing through GND under the following conditions: Each
terminal of MEOR, MWS0 to MWS5, DUTY, SHL, '2&, ',632)), 5(6(7, and CR is
connected to VCC, M/6 to GND, and frequency of CL1, FLM, M is respectively established as
follows.
fCL1 = 15 kHz, fFLM = 62.5 Hz, fM = 120 Hz
11. This value is specified for the current flowing through V EE under the following condition
described in note 8. Do not connect any lines to pin X.
12. Figure 19 shows a typical relation among ocsillation frequency R f and Cf. Oscillation frequency
may vary with mounting conditions.
fOSC = (kHz)
300
200
Cf = 100 (pF)
100
0
0
100
Rf (kΩ)
200
Figure 19 Ocsillation Frequency Characteristics
13. Indicates the resistance between one pin from X1 to X240 and another pin from the V pins
V1L/R, V2L/R, V5L/R, and V6L/R, when a load current is applied to the X pin; defined under the
following conditions:
VCC–VEE = 28 (V)
V1L/R, V6L/R = VCC–1/10 (VCC–VEE)
V5L/R, V2L/R = VEE + 1/10 (VCC–VEE)
RON
V1L, V1R
V6L, V6R
Pin X (X1 to X240)
V5L, V5R
V2L, V2R
Connect any of these MOS switch
Figure 20 On Resistance Conditions
950
HD66503
14. V1L/R and V6L/R should be near the VCC level, and V5L/R and V2L/R should be near the VEE
level. All these voltage pairs should be separated by less than ∆V, which is the range within
which RON, the LCD drive circuits’ output impedance is stable. Note that ∆V depend on power
supply voltages VCC–VEE. See Figure 21.
VCC
V1L/R
V6L/R
6.4
V (V)
V
2.5
V5L/R
V
V2L/R
VEE
8
28
VCC–VEE (V)
Figure 21 Relationship between Driver Output Waveform
951
HD66503
AC Characteristics (VCC = 2.7 to 5.5V, VCC–VEE = 8 to 28V, GND = 0V, Ta = –20 to +75°C)
Slave Mode (M/6 = GND)
Item
Symbol
Min
Typ
Max
Unit
Notes
CL1 high-level width
tCWH
500
—
—
ns
1
CL1 low-level width
tCWL
500
—
—
ns
1
FLM setup time
tFS
100
—
—
ns
1
FLM hold time
tFH
100
—
—
ns
1
CL1 rise time
tr
—
—
50
ns
1
CL1 fall time
tf
—
—
50
ns
1
Note:
1. Based on the load circuit shown in Figure 22.
Test point
30 pF (including jig capacitance)
Figure 22 Load Circuit
tr
CL1
0.8 VCC
0.2 VCC
tf
tCWH
tFS
FLM
tCWL
tFH
0.8 VCC
0.2 VCC
Figure 23 Slave Mode Timing
952
HD66503
Master Mode (M/6 = VCC)
Item
Symbol
Min
Typ
Max
Unit
CL1 delay time
tDCL1
—
—
1
µs
FLM delay time
tDFLM
—
—
1
µs
M delay time
tDM
—
—
500
ns
FLM setup time
tFS
tosc/2 – 500
—
—
ns
Notes
tOSC
CR
0.8 VCC
0.2 VCC
tDCL1
CL1
tDCL1
0.8 VCC
0.2 VCC
tFS
tDFLM
FLM
tDFLM
0.8 VCC
0.2 VCC
tDM
0.8 VCC
0.2 VCC
M
Figure 24 Master Mode Timing
953