PANASONIC AN6472NFBP

ICs for Telephone
AN6472NFBP
Cordless Telephone Speech Network IC Incorporating
Cross-Point Switch
■ Overview
Unit : mm
64
1
48
16
33
17
32
2.8±0.2
0.55
14.0±0.3
17.2±0.4
1.3±0.25
0.1±0.1
+0.1
0.15 –0.05
1.3±0.25
■ Features
• The speech block can operate on line voltage, with no
external power supply, and is operational even during a
commercial power failure.
• Incorporates a receiver noise reducing function to
improve the handset's howling margin.
• Incorporates auto. PAD, dial mute, DC voltage regulation, and other basic speech functions.
• The cross-point switch can be operated independently.
• Each output of the cross-point switch can correspond to
multiple inputs, allowing three- or four-person communication.
• The REC/PLAY amplifiers incorporate ALC and VOX
circuits.
• Receiver volume can be increased by 6 dB or 9 dB.
49
0.8
0.35±0.1
14.0±0.3
17.2±0.4
The AN6472NFBP is a speech network IC which
includes a receiver noise reducing function and is most
suitable for quality cordless telephones. It incorporates a
cross-point switch controlled by serial input. It allows
speech path switching and mixing, and provides for
three- or four-person communication and other sophisticated functions. It also incorporates REC/PLAY amplifiers
with VOX circuits.
QFP package with 64 pins (QFH064-P-1414)
1
ICs for Telephone
AN6472NFBP
■ Block Diagram
48
47
46
45
44
–
49
+
GND
42
41
40
38
37
36
35
34
33
32
VOX
Det.
+
0dB
0dB
L(07)
VREF
39
ALC
Det.
–
L(OF)
50
43
31
COMP
ALC
10dB
51
30
INJ
52
+
53
0dB
–
18
dB
20
dB
0/12
dB
18
dB
29
54
28
+
55
–
27
D
57
0dB
58
0dB
a1
Decoder
6dB
Latch
56
26
a2
a3
25
a4
DC
Control
a5
a6
24
DM
Control
23
+
L(3F)
0dB
Line Supply
Monitor
VCC
20
VCC
DMC
DMC
Noise
Protection DMC
L(17)
L(1F)
AP
Control
0dB
30dB
L(27)
–
64
Det.
1
GND
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
19
18
0/6/9dB
+
VREF
0dB
AP
62
2
0dB
0dB
63
–
21
0dB
DMC
22
+
AP
P.O.R
–
61
Power Supply
Control
60
0dB
DCC
59
17
GND
ICs for Telephone
AN6472NFBP
■ Pin Descriptions
Pin No.
Description
Pin No.
Description
1
Ground
33
RF2 link output
2
Line power (+) input
34
RF1 link output
3
Side-tone adjustment
35
Intercom link output
4
Line voltage control (1)
36
VOX detection control
5
Int. ref. voltage output (2)
37
VOX amp. input
6
Int. ref. voltage output (1)
38
Time stamp link output
7
Trans. preamp. output
39
Recording link output
8
Noise reduction detection output
40
ALC input
9
Noise reduction detection input
41
ALC detection control
10
Noise reduction amp. output
42
Loudspeaker link input
11
Auto. PAD control
43
Recording input
12
Rec. preamp. input
44
Recording inverse input
13
Rec. preamp. output
45
Recording preamp. output
14
Rec. amp. input
46
Recording bias current control
15
Rec. amp. output (1)
47
To recording head
16
Rec. amp. output (2)
48
EQ amp. inverse input
17
BT signal input
49
EQ amp. output
18
DTMF preamp. output
50
REC/PLAY int. ref. voltage output
19
DTMF signal input
51
Ground
20
MIC preamp. output
52
MIX preamp. output
21
MIC preamp. input (1)
53
MIX link input
22
MIC preamp. input (2)
54
AUX preamp. output
23
Dial mute control
55
AUX link input
24
Line voltage control
56
Intercom link input
25
Line interruption detector output
57
RF1 link input
26
Strobe signal input
58
RF2 link input
27
Clock signal input
59
Power-ON reset control
28
Data input
60
External supply voltage input
29
Ground
61
Internal supply voltage output
30
Logic power supply input
62
Circuit voltage control (2)
31
VOX detector output
63
Line current bypass (2)
32
SP link output
64
Line current bypass (1)
■ Absolute Maximum Ratings (Ta=25˚C)
Symbol
Rating
Supply voltage (1)
Parameter
VCC
7.0
Unit
V
Supply current (1)
ICC
50
mA
Supply voltage (2)
VL
12.0
V
Supply current (2)
IL
135
mA
mW
Power dissipation*1
PD
640
Operating ambient temperature
Topr
–20 to+75
˚C
Storage temperature
Tstg
–55 to+150
˚C
*1 In a free-air condition with Ta=75˚C
3
ICs for Telephone
AN6472NFBP
■ Recommended Operating Range
Parameter
Symbol
Operating supply voltage range (1)
VCC
4.5V to 5.5V
Range
Operating supply voltage range (2)
VL
3.0V to 11.0V
■ Recommended Operating Conditions (Ta =20 to +75˚C)
Parameter
Symbol
Supply voltage
VCC
Clock frequency
fCLK
Input pulse width
CLK
STB
DATA
Setup time
STB
DATA
Hold time
STB
Condition
min
4.5
typ
max
5
Input Duty 40% to 50%
tW
tsu
th
Unit
5.5
V
250
kHz
1.6
µs
1.2
µs
1.6
µs
0.8
µs
1.6
µs
1.2
µs
Input pulse width (high)
twh
0.8
µs
Input pulse width (low)
twl
0.8
µs
Clock pulse rise time
tr
20
µs
Clock pulse fall time
tr
20
µs
Input voltage
Vi
VCC
V
0
■ Electrical Characteristics (Ta=25±2˚C)
Parameter
Symbol
Condition
min
typ
max
Unit
Power Supply Characteristics During Power Failure
Line DC voltage (I-1)
VL – I1
Line DC voltage (I-2)
VL – I2
Line DC voltage (I-3)
VL – I3
Line DC voltage H (I-1)
VLH – I1
Line DC voltage H (I-2)
VLH – I2
Line DC voltage H (I-3)
VLH – I3
Internal supply voltage (I)
Vreg – I
Internal ref. supply voltage (I)
Vref – I
V–DCC=HIGH,
IL=20mA, VCC=0V
V–DCC=HIGH,
IL=60mA, VCC= 0V
V–DCC=HIGH,
IL=120mA, VCC= 0V
V–DCC= LOW,
IL=30mA, VCC= 0V
V–DCC= LOW,
IL= 60mA, VCC= 0V
V–DCC= LOW,
IL=120mA, VCC= 0V
V– DCC=HIGH,
IL=20mA, VCC= 0V
V–DCC=HIGH,
IL=20mA, VCC= 0V
3.2
3.5
3.8
V
4.5
4.8
5.2
V
6.6
7.0
7.5
V
4.5
5.0
5.5
V
5.7
6.2
6.7
V
7.9
8.5
9.2
V
1.8
2.0
2.2
V
0.9
1.0
1.1
V
3.1
3.4
3.8
V
4.3
4.7
5.1
V
6.3
6.8
7.3
V
4.3
4.85
5.4
V
Normal power supply characteristics
4
Line DC voltage (E-1)
VL – E1
Line DC voltage (E-2)
VL – E2
Line DC voltage (E-3)
VL – E3
Line DC voltage H (E-1)
VLH – E1
V– DCC=HIGH,
IL=20mA, VCC=5V
V–DCC=HIGH,
IL=20mA, VCC=5V
V–DCC=HIGH,
IL=20mA, VCC=5V
V–DCC=HIGH,
IL=20mA, VCC=5V
ICs for Telephone
AN6472NFBP
■ Electrical Characteristics (cont.) (Ta=25±2˚C)
Parameter
Symbol
Line DC voltage H (E-2)
VLH – E2
Line DC voltage H (E-3)
VLH – E3
Internal supply voltage (E)
Vreg – E
Internal ref. supply voltage (E)
Vref – E
Total circuit current
Power interruption detection (1)
Power interruption detection (2)
Itotal
V – HIT1
V – HIT2
Condition
V–DCC=LOW,
IL=60mA, VCC=5V
V–DCC=LOW,
IL=120mA, VCC=5V
V–DCC=HIGH,
IL=20mA, VCC=5V
V–DCC=HIGH,
IL=20mA, VCC=5V
V–DCC=HIGH,
IL=20mA, VCC=5V
min
typ
max
Unit
5.3
5.95
6.6
V
7.55
8.2
8.9
V
4.6
4.85
5.0
V
2.25
2.5
2.7
V
17
27
35
mA
VL=2.7V, VCC=5V
0
0.1
0.6
V
VL=1.5V, VCC=5V
4.4
4.95
5
V
30.5
32.5
34.5
dB
27
29
31
dB
2.5
3.5
5
dB
0
4
4
6
8
dB
19
21
23
dB
30.5
32.5
34.5
dB
26.8
28.8
30.8
dB
2.5
3.7
5
dB
4
12
6
8
10
dB
5
6
7
dB
7.5
9
10.5
dB
19.5
21.5
23.5
dB
–1.2
– 0.1
1.2
dB
28.2
30.2
32.2
dB
24.4
26.4
28.4
dB
2.5
3.8
5
dB
Receiver During Power Failure
Rec. gain (I-1)
GV – IR1
Rec. gain (I-2)
GV – IR2
Rec. auto. PAD width (I)*1
AP – IR
Rec. max. output (I)
VO – IR
Rec. noise reduction (I)
NL – IR
BT amp. gain (I)
GV – IBT
IL=30mA, VCC= 0V
Vin= – 42dBm
IL= 80mA, VCC= 0V
Vin= –42dBm
IL=30mA– 80mA, VCC= 0V,
Vin= – 42dBm
With IL=30mA, VCC= 0V, and
THD=5%
IL=30mA, VCC= 0V,
Vin= –42dBm
Vin–M= –65/–50dBm
IL=30mA, VCC= 0V,
V–DMC=LOW,
Vin= –30dBm
dBm
Receiver On External Power Supply
Rec. gain (E-1)
GV – ER1
Rec. gain (E-2)
GV – ER2
Rec. auto. PAD width (E)*1
AP – ER
Rec. max. output (E)
VO – ER
Rec. noise reduction (E)
NL – ER
Rec. digital volume (1)*2
GV – DV1
Rec. digital volume (2)*2
GV – DV2
BT amp. gain (E)
GV – EBT
Rec. gain difference
DG–R
IL=30mA, VCC=5V
Vin= –42dBm
IL=30mA, VCC=5V
Vin= –42dBm
IL=30mA–80mA, VCC=5V
Vin= –42dBm
With IL=30mA, VCC=5V, and
THD=5%
IL=30mA, VCC=5V,
Vin= –42dBm
Vin–M= –65/–65dBm
IL=30mA, VCC=5V,
Vin= –42dBm, DV–1 ON
IL=30mA, VCC=5V,
Vin= –42dBm, DV–2 ON
IL=30mA, VCC=5V,
V–DMC=LOW,
Vin= –30dBm
For VCC=0V and 5V(between
Gv–IR1 and Gv–ER1)
dBm
Transmitter Amp. During Power Failure
Trans. gain (I-1)
GV – IM1
Trans. gain (I-2)
GV – IM2
Trans. auto. PAD width (I)*1
AP – IM
R=27Ω(Pin3), IL=30mA,
VCC=0V, Vin= –38dBm
IL=80mA, VCC=0V,
Vin= –38dBm
IL=30mA–80mA, VCC=0V,
Vin= –38dBm
Note) Unless otherwise specified, input signal Fin =1kHz, control voltage V-DOC = high, and control voltage V-DMC = high.
*1 Gain decrease when line current IL is changed from 30 to 80 mA. If pin 11 (auto. PAD control)is connected to pin 61 (int.
supply voltage output), the gain will not change.
*2 Gain increase from receiver gain (E-1).
5
ICs for Telephone
AN6472NFBP
■ Electrical Characteristics (cont.) (Ta=25±2˚C)
Parameter
Symbol
Trans. max. output (I-1)
VO – IM1
Trans. max. output (I-2)
VO – IM2
DTMF gain (I-1)
GV – ID1
DTMF gain (I-2)
GV – ID2
DTMF auto. PAD width (I)*1
AP – IDT
DTMF max. output (I-1)
VO – ID1
DTMF max. output (I-2)
VO – ID2
Condition
With IL=30mA, VCC= 0V and
HD=5%
With IL=30mA, VCC= 0V,
THD=5% and V–DCC=LOW
IL=30mA, VCC= 0V,
V–DMC= LOW,
Vin= –30dBm
IL=80mA, VCC= 0V,
V–DMC=LOW,
Vin= –30dBm
IL=30mA–80mA, VCC= 0V,
V–DMC= LOW,
Vin= –30dBm
IL=30mA, VCC=0V,
V–DMC=LOW, THD=5%
IL=30mA, VCC= 0V,
THD=5%, V–DMC=LOW,
V–DCC=LOW
min
typ
max
Unit
0
3.5
dBm
0
3.5
dBm
17.5
19.5
21.5
dB
13.7
15.7
17.7
dB
2.5
3.8
5
dB
0
3.8
dBm
0
3.5
dBm
28.6
30.6
32.6
dB
25.0
27.0
29.0
dB
2.5
4
5
dB
2
6
dBm
2
6
dBm
18.1
20.1
22.1
dB
14.5
16.5
18.5
dB
2.5
4.1
5.5
dB
2
6
dBm
2
6
dBm
–1.8
–0.8
0.7
dB
–2.3
–1.3
0.2
dB
Transmitter Amp. On External Power Supply
Trans. gain (E-1)
GV – EM1
Trans. gain (E-2)
GV – EM2
Trans. auto. PAD width (E)*1
AP – EM
Trans. max. output (E-1)
VO – EM1
Trans. max. output (E-2)
VO – EM2
DTMF gain (E-1)
GV – ED1
DTMF gain (E-2)
GV – ED2
DTMF auto. PAD width (E)*1
AP – EDT
DTMF max. output (E-1)
VO – ED1
DTMF max. output (E-2)
VO – ED2
Trans. gain difference
DG – M
DTMF gain difference
DG – MF
IL=30mA, VCC= 0V,
Vin= –38dBm
IL=80mA, VCC=5V,
Vin= –38dBm
IL=30mA–80mA, VCC=5V,
Vin= –38dBm
With IL=30mA, VCC=5V and
THD=5%
IL=30mA, VCC=5V,
THD=5%, V–DCC=LOW
IL=30mA, VCC=5V,
DM=ON, Vin= –30dBm
IL=80mA, VCC=5V,
V–DMC=LOW,
Vin= –30dBm
IL=30mA–80mA, VCC=5V,
V–DMC=LOW,
Vin= –30dBm
IL=30mA, VCC=5V,
V–DMC=LOW, THD=5%
IL=30mA, VCC=5V,
DM=ON, V–DMC=LOW,
THD=5%
For VCC= 0V and VCC=5V
(between Gv–IM1 and Gv–EM1)
For VCC= 0V and 5V
(between Gv–ID1 and Gv–ED1)
Note) Unless otherwise specified, input signal Fin=1 kHz, control voltage V-DOC=high, and control voltage V-DMC=high.
*1 Gain decrease when line current IL is changed from 30 to 80 mA. If pin 11 (auto. PAD control) is connected to pin 61(int.
supply voltage output) , the gain will not change.
6
ICs for Telephone
AN6472NFBP
■ Electrical Characteristics (cont.) (Ta=25±2˚C)
Parameter
Symbol
Condition
min
typ
max
Unit
Recording Preamplifiers
Rec. preamp. gain
GV – Rp
Vin= – 60dBm, Rin=0Ω
Rec. preamp. output
VO – RP
Vin= – 45dBm, Rin=10Ω
Rec. preamp. output noise voltage*1
Vno – RP
DIN/AUDIO, Rg=10kΩ
43
45
47
dB
–13.4
–11.4
–9.4
dBm
0.8
2.5
mVrms
Recording Amplifier
L–SW (h07)= ON
145
180
215
µA
GV – REC
L–SW (h07)= ON,
Vin= –15dBm, RL=1kΩ
40.0
50.0
63.0
mVrms
EQ amp. gain
GV – EQ
27.8
29.8
31.8
dB
EQ amp. output noise voltage
Vno – EQ
L–SW (h07)= ON,
Vin= – 40dBm
L–SW (h07)= ON,
DIN/AUDIO, RL=1kΩ
0.45
1.2
mVrms
Head bias current
Head output
I – REC
Playing EQ Amplifier
VOX Detector
VOX sensitivity (1)
VS1
I–VOX=12.5µA
VOX sensitivity (2)
VS2
I–VOX=24.5µA
3.5
4.8
V
0.025
0.5
V
Link SW Input Amplifier
MIX amp. gain
GV – MIX
Vin= – 36dBm
5
6
7
dB
AUX amp. gain
GV – AUX
Vin= – 36dBm
5
6
7
dB
SP output gain (1)*1
GV – SPO1
11
12
13
dB
SP output gain (2)*1
GV – SPO2
–1.5
– 0.5
0.5
dB
Intercom output gain*1
GV – DHO
18.5
20
21.5
dB
RF1 output gain*1
GV – RF10
16.5
18
19.5
dB
RF2 output gain*1
GV – RF20
16.5
18
19.5
dB
Recording output gain*1
GV – RECO
–1.0
0
1.0
dB
Recording output gain*1
GV – RO
19.9
21.4
22.9
dB
Line output gain*1
GV – TO
17.7
19.2
20.7
dB
Rec. output gain difference*2
GD – RO
–1.0
0
1.0
dB
Time stamp output gain*1
GV – TSO
Input AUX IN, Vin= – 36dBm,
L–SW (h3A) = ON
Input AUX IN, Vin= – 36dBm,
L–SW (h3A&h2F) = ON
Input AUX IN, Vin= – 36dBm,
L–SW (h3B) = ON
Input AUX IN, Vin= – 36dBm,
L–SW (h3C) = ON
Input AUX IN, Vin= – 36dBm,
L–SW (h3D) = ONΩ
Input AUX IN, Vin= – 36dBm,
L–SW (h3E) = ON
Input AUX IN, Vin= – 36dBm,
L–SW (h38) = ON
Input AUX IN, Vin= – 36dBm,
L–SW (h39) = ON
Input AUX IN, Vin= – 36dBm,
L–SW (h30) = ON
Input AUX IN, Vin= – 36dBm,
L–SW (h37) = ON
–1.0
0
1.0
dB
Link SW Output Amplifier
Note) Unless otherwise specified, external supply voltage VCC=5V, line current IL= 0mA, input signal frequency=1 kHz, control
voltage V-DOC=high, and control voltage V-DMC = high.
*1 Each amp. gain is measured from AUX OUT or MIX OUT to its output (the AUX or MIX preamp. gain is not included in the
calculation).
*2 The difference from the receiver output gain (Gv-RO).
7
ICs for Telephone
AN6472NFBP
■ Electrical Characteristics (cont.) (Ta=25±2˚C)
Parameter
Symbol
Condition
min
typ
max
Unit
Link SW Input
MIC input gain*1
Gv – MI
Rec. input gain*1
Gv – RI
Intercom input gain
Gv – DHI
RF1 input gain
Gv – RF1I
RF2 input gain
Gv – RF2I
SP link input gain
Gv – SPI
Vin= –38dBm, rec. output
L –SW(h0E)= ON
Vin= –42dBm, rec. output
L–SW (h16)= ON
Vin= –30dBm, rec. output
L–SW (h1E)= ON
Vin= –30dBm, rec. output
L–SW (h26)= ON
Vin= –30dBm, rec. output
L–SW (h2E)= ON
Vin= –30dBm, SP rec. output
L–SW (h02)= ON
–1
0
1
dB
–1
0
1
dB
5
6
7
dB
–1
0
1
dB
–1
0
1
dB
11
12
13
dB
0
4
dBm
0
4
dBm
0
4
dBm
0
4
dBm
0
4
dBm
Link Maximum Output
SP OUT max. output
Vo – SP
DH OUT max. output
Vo – DH
RF1 OUT max. output
Vo – RF1
RF2 OUT max. output
Vo – RF2
L-REC OUT max. output
Vo – LR
Input L–SP IN, THD=5%
L–SW (h02)= ON
Input RF1 IN, THD=5%
L–SW (h23)= ON
Input RF2 IN, THD=5%
L–SW (h25) = ON
Input RF1 IN, THD=5%
L–SW (h2C)= ON
Input AUX IN, THD=5%
L–SW (h3E)= ON
Note) Unless otherwise specified, external supply voltage VCC=5V, line current IL= 0mA, input signal frequency=1 kHz, control
voltage V-DOC= high, and control voltage V-DMC= high.
*1 Each amp. gain is measured from MIC OUT or R PRE OUT to its output.
■ Electrical Characteristics (cont.) (Ta=25±2˚C)
Parameter
Symbol
Condition
min
typ
max
Unit
Controls
Dial mute high level voltage
VDMC – H
Dial mute high level control current
IDMC – H
Dial mute low level voltage
VDMC – L
Dial mute low level control current
IDMC – L
DC voltage control high level voltage
VDCC – H
DC voltage control high level
control current
IDCC – H
DC voltage control low level voltage
VDCC – L
DC voltage control low level
control current
IDCC – L
2
V– DMC = 5V
38
– 0.2
V– DMC= 0V
– 40
–20
2
V – DCC= 5V
10
25
– 0.2
V– DCC= 0V
Note) Unless otherwise specified, VCC=5V, and IL = 20 mA.
8
15
–2
– 0.1
VCC
+ 0.2
V
80
µA
0.3
V
–10
µA
VCC
+ 0.2
V
50
µA
0.4
V
µA
ICs for Telephone
AN6472NFBP
■ Electrical Characteristics (cont.) (Ta=25±2˚C)
Parameter
Symbol
Data input high level voltage
VDIN – H
Data input high level control current
IDIN – H
Data input low level voltage
VDIN – L
Data input low level control current
IDIN – L
Condition
min
typ
max
2
V– DIN=5V
70
160
– 0.2
V– DIN = 0V
Unit
VCC
+ 0.2
V
250
µA
0.3
V
µA
–1
– 0.1
450
570
750
Ω
450
580
750
Ω
Power Supply Block
AC impedance (I)
ZAC – I
AC impedance (E)
ZAC – E
IL=80mA, VCC= 0V,
Vin=200mVrms, Fin=1kHz
IL=80mA, VCC=5V,
Vin=200mVrms, Fin=1kHz
Input impedance
BT amp. input impedance
Zin – BT
Pin 17 Input
8.7
9.5
10.7
kΩ
ALC amp. input impedance
Zin – ALC
Pin 40 Input
8.5
9.5
10.5
kΩ
Intercom preamp. input impedance
Zin – DH
Pin 56 Input
8.5
9.5
10.5
kΩ
RF1 preamp. input impedance
Zin – RF1
Pin 57 Input
8.5
9.5
10.5
kΩ
RF2 preamp. input impedance
Zin – RF2
Pin 58 Input
8.5
9.5
10.5
kΩ
SP input impedance
Zin – SP
Pin 42 Input
37.5
50.0
62.5
kΩ
■ Electrical Characteristics (Design Values for Reference) (Ta=25±2˚C)
The following are design values for reference, not guaranteed values.
Parameter
Symbol
Condition
min
typ
max
Unit
Speech Block
Rec. output noise voltage (I)
Vn – IR
Rec. output noise voltage (E)
Vn – ER
Trans. output noise voltage (I)
Vn – IT
Trans. output noise voltage (E)
Vn – ET
Dial mute trans. amp. mute attenuation
M – TDM
Trans. preamp. mute attenuation
M – TM
Rec. output mute attenuation
M – RO
IL=30mA, VCC=0V,
DIN/AUDIO
IL=30mA, VCC=5V,
DIN/AUDIO
IL=30mA, VCC=0V,
DIN/AUDIO
IL=30mA, VCC=5V,
DIN/AUDIO
IL=30mA, VCC=5V,
Vin= –30dBm,
V– DBM–H/L
IL=30mA, Vin= –30dBm,
VCC=5V,
Lsw (h3F)=OFF/ON
IL=30mA, Vin= –30dBm,
VCC=5V,
Lsw (h27)= OFF/ON
0.3
mVrms
0.3
mVrms
0.3
mVrms
0.3
mVrms
75
dB
70
dB
50
dB
Rec. preamp. input impedance
Zin – R
Pin 12 Input
500
kΩ
MIC preamp. input impedance
Zin – M
Pin 21 and 22 Input
500
kΩ
40
dB
1
dB
80
dB
REC/PLAY Block
ALC amp. ALC width
W – ALC
ALC amp. ALC effect
DALC
Rec. amp. mute attenuation
M – REC
IL= 0mA, VCC=5V,
and ALC output distortion≤2%
IL=0mA, VCC=5V, and
Vin= –45dBm to –20dBm
VCC=5V, Vin= –10dBm
IL= 0mA, and
LSW (h07)= ON/OFF
9
ICs for Telephone
AN6472NFBP
■ Electrical Characteristics (Cont.) (Design Values for Reference) (Ta=25±2˚C)
The following are design values for reference, not guaranteed values.
Parameter
Symbol
EQ amp. mute attenuation
M–EQ
Condition
min
VCC=5V, Vin= –30dBm
IL= 0mA,
LSW(h0F)=ON/OFF
typ
max
Unit
80
dB
Rec. preamp. input impedance
Zin–REC
Pin 43 input
10
kΩ
EQ amp. input impedance
Zin–EQ
Pins 47 and 48 input
500
kΩ
VOX amp. input impedance
Zin–VOX
Pin 47 input
500
kΩ
75
dB
Link Switch
Link SW mute attenuation
M–LS
VCC=5V, IL=30mA, AC output
measured at link ON/OFF
MIX preamp. input impedance
Zin–MIX
Pin 53 input
500
kΩ
AUX preamp. input impedance
Zin–AUX
Pin 55 input
500
kΩ
CPC output impedance
Zout–CPC
Pin 25 input
100
kΩ
Zin–NL
Pin 9 input
45
Ω
VOX–CT
VCC=5V, IL=30mA, cross talk
to line during VOX
–70
dBm
Noise reduction amp. input impedance
VOX cross talk
■ Pin Descriptions
Pin No. Pin name I/O
1
GND
2
VL
Waveform
0V
I
DC
3 ∼10V
Description
Ground :
•This is the ground pin for the
speech network.
Equivalent circuit
Remarks
GND for REC/PLY,
VREG, SPEECH and
LINK
Line power input:
•Connects to the positive output of the diode bridge.
The line drive gain (G) is :
G = ZLine//ZTel
R1
Also assuming
ZLine≈600Ω
ZTel ≈600Ω
R1= 27Ω
G= 20log 300 = 20.9db
27
2
TO
3
ST
O
4
VL–
CONT
I
5
Vref–
SN
O
DC
0.3V
DC1V
1V
(Const)
Side-tone adjustment:
•Grounded through R1 (27Ω)
•Connects to the side-tone
adjusting circuit to adjust side
tone and receiver level.
3
C2 and the internal resistance
determine the f. characteristics.
Line voltage control (1) :
Int. ref. voltage output (2) :
•Output impedance=50Ω
61 Vreg
24kΩ
Int. ref. voltage output (1) :
6
Vref
O
1V
(Const)
•Outputs half the Vreg reference
6
+
24
kΩ
5
–
voltage.
7
T–
FILTER
O
DC1V
Trans. preamp. output :
•C7 as connected between this
pin and the ground forms a
low-pass filter.
4
6kΩ
7
Note) The symbols are the same as those used in the application circuit.
10
Grounded through
0.01µF capacitor.
a
ICs for Telephone
AN6472NFBP
■ Pin Descriptions (cont.)
8
VN
DET
9
VN
DET–
IN
I
10
VN
OUT
O
11
12
APC
RV IN
Waveform
Pin 8 output
Pin No. Pin name I/O
I
DC (with a capacitor)
Input
Full-wave detection
(with no capacitor)
•Noise reduction detection amp. input
: Noise reduction amp. output is fed
through C7 and R6 to this pin.
VREF
Vreg-R · I
IL
I
VREF – SN
13
14
15
RV
PREOUT
RV
FILTER
17
VREF – SN
RV
OUT
(1)
VREF – SN
VREF – SN
O
·
16
O
O
RV
OUT
(2)
BT–
IN
VREF – SN
I
VREF – SN
Signal input
18
19
MF –
OUT
MF –
IN
O
VREF – SN
I
Description
•Noise reduction detection amp. output : A smoothing capacitor C6 and
R5 connect to this pin to adjust the
attack and recovery times of noise
reduction.
VREF – SN
Signal input
•Noise reduction amp. output :
Connects to the noise reduction
detection amp. input.
Auto. PAD control :
•Connects through a resistance to Pin
61(Vreg). If the resistance increases,
the PAD operates closer to the near
end. If the resistance decreases, the
PAD operates closer to the far end.
Rec. preamp. input :
•Receiver signals are input from
the side-tone circuit to this pin.
•R8 and C9 connected between
Pin 13 and this pin determine
the f. characteristics.
Equivalent circuit
Vref–SN
Vref–SN
+
+
–
–
95kΩ 10
3kΩ
64kΩ
8
9
Remarks
•This pin must be
grounded if noise
reduction is not used.
•The greater C7, the longer the attack time. The
smaller R6, the shorter
the recovery time.
•Noise reduction detection amp. gain (G) is :
0.1µF
G = 64K
R6
11
I
I∝ IL
+
12
Rec. preamp. output :
•R8 and C9 connected between Pin 12
and this pin determine the f. characteristics.
•The output impedance is up to 1 kΩ.
13
–
G= –
10kΩ
+
The receiver preamplifier
gain (G) is :
1
1
1
R9 + jωC9
R8 + jωC10
–
13
Rec. amp. input :
16
Rec. amp. outputs (1 and 2) :
•A ceramic or dynamic receiver
is connected.
•The output circuit is a BTL
configuration.
•The output impedance is up to
50 Ω.
BT signal input :
•BT (beep tone) signals are input
through C15 to this pin.
•Input impedance is 10 kΩ.
–
13
15
30kΩ
Vref–SN
10kΩ
17
+
–
DTMF preamp. output :
•A C/R combination between
Pin 19 and this pin determines
the f. characteristics of the
DTMF preamp.
DTMF signal input :
•DTMF signals are input
through a capacitor to this pin.
•DTMF signals are enabled
when DMC is low at Pin 40.
+
10kΩ
+
–
18
In the application circuit,
MIC. IN (–) is input
through a capacitor. This
capacitor and R12-R14,
and C15 and C16 determine the f. characteristics.
Vref–SN
10kΩ
+
19
–
The 10 kΩ input impedance and C12 or C13
form a HPF.
18
11
ICs for Telephone
AN6472NFBP
■ Pin Descriptions (cont.)
Pin No. Pin name I/O
20
21
22
23
MIC
OUT
O
VREF – SN
MIC
IN
(+)
I
MIC
IN
(–)
I
DMC
Waveform
VREF – SN
VREF – SN
I
24
I
0.2V
Line DC voltage
L–VCC
25
CPC
O
0.2V
Line interruption
5V
26
STR
I
0V
27
CLK
I
0V
5V
28
DATA
I
0V
12
MIC preamp. input (1) :
•A bias resistor and a microphone connect to this pin.
Vref
21
+
22
–
10kΩ
+
–
20
MIC preamp. input (2) :
•R12 and C14 connected
between Pin 20 and this pin
determine the f. characteristics.
Line voltage control :
•Line voltage is normal when
the input voltage at this pin is
high. Line voltage increases
by 1-1.5 V when the input
voltage is low.
Line interruption detector output :
•This is an open collector output to a
microprocessor, requiring a pull-up
resistor connected to the microprocessor's power supply. This pin goes
low when line voltage is 3.0 V or
more, and goes high when 1.5 V or
less.
Strobe signal input :
•The strobe signal for serial
control data is input to this
pin. The rising edge of the
strobe signal determines the
timing at which internal control address or ON/OFF status
is validated.
Clock signal input :
•The clock signal for serial control
data is input to this pin. The rising
edge of the clock signal determines
the timing at which data is read.
5V
Equivalent circuit
MIC preamp. output :
•R12 and C14 connected
between Pin 22 and this pin
determine the f. characteristics.
•The output impedance is up to
1 kΩ.
Dial mute control :
•Normal speech mode when
Pin 23 is high or open (MIC
amp. ON and rec. amp. ON).
•DTMF mode when Pin 23 is
low (DTMF amp. ON and BT
amp. ON).
VCC
DC –
CONT
Description
Data input :
•Serial data is input to this pin.
Data is read into the internal
shift register in synchronization with clock signals.
61
200kΩ
23
100kΩ
150kΩ
24
200kΩ
VL 2
144kΩ
L–VCC
100kΩ
25
56kΩ
26
L–VCC
10kΩ
300kΩ
27
L–VCC
10kΩ
300kΩ
28
10kΩ
300kΩ
L–VCC
Remarks
ICs for Telephone
AN6472NFBP
■ Pin Descriptions (cont.)
Pin No. Pin name I/O
Waveform
Description
29
GND
Ground :
•This is the ground pin for the
logic circuits.
30
L–
VCC
Logic power supply input :
31
VOX–
OUT
L · VCC
O
0V
Voice ON
33
RF2–
OUT
O
VREF – SN
O
VREF – SN
VOX detector output :
•This is an open collector output.
•This pin goes high when voice
signals are input to Pin 37.
Loudspeaker link output :
•This is a link switch output to
an external loudspeaker amplifier.
•The output amplifier gain is
selectable between 12 and 0
dB.
•Output impedance is 50 ±
30Ω.
RF2 link output :
•This is a link switch output.
•Output impedance is 50Ω.
Remarks
31
Vref – SN
From LINK SW
0/12dB
+
–
32
SP–
OUT
Equivalent circuit
50kΩ
32
30kΩ
10kΩ
Vref
Vref– SN
From LINK SW
50kΩ
+
–
36
DH–
OUT
VOX
DET
O
VREF – SN
O
VREF – SN
O
DC (with a capacitor)
Pin 37 input
Half-wave rectification
(with no capacitor)
RF1 link output :
•This is a link switch output.
•Output impedance is 50Ω.
Intercom link output :
•This is a link switch output to
an intercom.
•Output impedance is 50Ω.
10kΩ
From LINK SW
+
10kΩ
VOX detection control :
•A smoothing capacitor (C18)
and a resistor (R18) connect in
parallel to this pin to adjust
the attack and recovery times
of the VOX detector.
I
38
LTS–
OUT
O
Time stamp link output :
•This is a buffered link switch
output.
•Output impedance is 50Ω.
VREF – SN
+
500
36
O
VREF – SN
B) With large C18 (22
µF) and large R18 (100
kΩ)
VOX input
VOX output
From LINK SW
+
–
39
LRC–
OUT
VOX detection can be done
in two ways :
A) With small C18 (560
pF) and small R18 (39kΩ)
VOX input
VOX output
–
VOX
IN
35
90kΩ
500
37
Vref – SN
50kΩ
Vref–PR
37
VOX amp. input :
•VOX (voice detection) signals
are input to this pin.
•Input impedance is 500Ω.
33
34
68kΩ
–
35
RF1–
OUT
Pin 36 output
34
When address 2F of the
cross-point switch is
OFF, the output amplifier gain is set to 12 dB.
38
39
Recording link output :
•This is a buffered link switch
output.
•Output impedance is 50Ω.
13
ICs for Telephone
AN6472NFBP
■ Pin Descriptions (cont.)
Pin No. Pin name I/O
40
ALC.
IN
Waveform
Description
Equivalent circuit
ALC input :
•Pin 45 connects through a
coupling capacitor to this pin.
•Input impedance is 10kΩ.
I
+
–
44
46
RD
PRE –
NF
REC
PRE –
OUT
I
VREF – SN
I
I
VREF – SN
VREF – SN
O
VREF – SN
BIASS
ADJ
VREF – PR
47
HEAD I/O
48
EQ.
NF
I
VREF – PR
O
VREF – PR
51
14
VREF –
PR
GND
O
1
V
2 REF
(CONST)
50kΩ
Vref–PR
10kΩ
43
+
50kΩ
22kΩ
from ALC
+
44
REC/PLAY int. ref. voltage
output :
•The Pin 5 ref. voltage is buffered and output from this pin.
•Output impedance is 50Ω
Ground :
G=–
45
+
VREF-PR
×3
R25
1
Vreg
VREF-PR =
2
IH =
46
47
Vref– PR
from
recording head
+
49
48
Vref
6
R23
R22+jωC23
•Address 07 of the crosspoint SW determines
the ON/OFF status of
the rec. preamp.
•The bias current to the
head is :
VREG
61
To recording head :
•A recording head connects to
this pin.
EQ amp. inverse input :
•A C/R combination between
Pin 49 and this pin determines
the equalizer characteristics.
EQ amp. output :
•Outputs amplified equalizer
signals.
•Output impedance is 50Ω.
The gain (G) of the
recording preamplifier is
:
45
+
–
50
Recording preamp. inverse input :
•A/CR combination between Pin 45 and
this pin determines the gain and f. characteristics of the recording preamplifier.
Recording preamp. output :
•Outputs amplified recording
signals.
•Output impedance is 50Ω.
Recording bias current control :
•A C/R combination connected to this
pin determines the recording bias current and gain of a recording head.
•The smaller the resistance of the C/R
combination, the greater the bias current and gain.
to LINK SW
+
42
–
49
EQ.
OUT
0V
During recording
0V
During playing
Recording input :
•Recording signals are input
through a coupling capacitor
to this pin.
•Input impedance is normally
10kΩ. It decreases during
ALC operation.
Vref – SN
–
Bias voltage
Loudspeaker link input :
•SP signals to this pin are output
through a coupling capacitor to the
link switch.
•Input impedance is 50kΩ.
41
–
45
RD
PRE –
IN
Input
Full-wave rectification
(with no capacitor)
–
43
SP –
IN
O
2kΩ
ALC detection control :
•A smoothing capacitor (C20) and a
resistor (R20) connect in parallel to
this pin to adjust the attack and
recovery times of the ALC.
•Ground Pin 41 if no
ALC circuit is used.
•The larger C20, the longer the attack time. The
smaller R20, the shorter
the recovery time
–
42
ALC.
DET
Pin 41 output
41
VRE G
Vref – PR
40
DC (with a capacitor)
Remarks
50
•The gain of the equalizer amp. is calculted the
same way as the receiver preamp.
•Address OF of the crosspoint SW determines the
ON/OFF status of the EQ
amp.
ICs for Telephone
AN6472NFBP
■ Pin Descriptions (cont.)
Pin No. Pin name I/O
52
MIX
OUT
MIX
IN
54
AUX
OUT
57
RF1
IN
RF2
IN
O
VREF – SN
I
VREF – SN
I
VREF – SN
I
MIX link input :
• MIX signals are input through a
coupling capacitor to this pin.
AUX preamp. output :
• A C/R combination between Pin 55
and this pin determines the gain and f.
characteristics of the AUX preamp.
• Output impedance is 50Ω.
AUX link input :
• AUX signals are input through a
coupling capacitor to this pin.
Intercom link input :
• Intercom signals are input
through a coupling capacitor
C30 to this pin.
• Input impedance is 10kΩ
VREF – SN
to LINK SW
+
53
The gain of the MIX
preamp. is calculated the
same way as the rec.
preamp.
52
Vref–SN
to LINK SW
+
55
The gain of the AUX
preamp. is calculated the
same way as the rec.
preamp.
54
Vref–SN
10kΩ
56
to LINK SW
+
RF1 link input :
• RF1 signals are input through
a coupling capacitor C31 to
this pin.
• Input impedance is 10kΩ.
RF2 link input :
• Same as above.
I
Vref–SN
The input impedance as
illustrated left and C30,
C31, or C32 form a
HPF.
Vref–SN
10kΩ
to LINK SW
+
–
58
DH IN
I
Remarks
–
56
AUT
IN
VREF – SN
Equivalent circuit
–
55
O
Description
MIX preamp. output :
• A C/R combination between Pin 53
and this pin determines the gain and f.
characteristics of the MIX preamp.
• Output impedance is 50Ω.
–
53
Waveform
57/58
VCC
PR
I
5V
60
61
VCC
Vreg
±0.5V
VCC to 0.2V
O
DC
2V during power
failure
50kΩ
Comparator
59
+
–
59
Power-ON reset control :
• C33 between this pin and
GND determines the powerON reset time of the logic circuits.
External supply voltage input :
• –5±0.5V power supply is input
to this pin.
Internal supply voltage output :
• A power supply derived from line
voltage is output from this pin to the
internal speech network.
2
VL
61
2
62
2 to 5 VDC
depending on
VL
VLC
Reset
signal
150kΩ
•The larger C33, the longer
the power-ON reset time.
• The power-ON reset signal
is output when the supply
voltage reaches 4V.
Circuit voltage control (2) :
•This pin is grounded through
C36.
64
C36 (typically 47µF)
determines how the circuit voltage fluctuates.
62
63
PD2
O
0 to 3 V depending
on VL
DC
64
PD1
I
Same as above
VL–33Ω × IL
Line current bypass :
•Line current is bypassed from
this pin through R35 to GND.
R35 must be 1/2 W or more.
Line current bypass (1) :
• Line current is bypassed from
this pin through R36 to Pin 2.
R36 must be 1/2 W or more.
2 VL
33Ω
64
Power supply
63
DC
ZTel is 1.5-2.0kΩ on the
IC side. It must be
adjusted to 600Ω by
inserting a 820Ω resistor
between VL and GND.
64
R36
33Ω
63
15Ω
VL
820Ω
100µF
15
ICs for Telephone
AN6472NFBP
Logic Specifications
■ Basic Block Diagrams
Output (cross-point SW and other controls)
Latch Circuit
Reset
Decoder
Decoder
(6 bit, 48 channels)
Shift Register
A6
A5
A4
A3
A2
A1
D
Clock
Data
Strobe
■ Time Charts (Assuming the address h26 latch is to be set)
Clock
Data
1
0
0
1
1
0
1
(A6)
(A6)
(A4)
(A3)
(A2)
(A1)
(D)
Strobe
1. Data is read into the shift register in synchronization with a rising edge of the clock, with the higher data being shifted
sequentially on a first-come highest-bit basis.
2. When the strobe is low, data is shifted sequentially on the sift register in synchronization with the clock. Data on the
latch circuit will not change.
3. When the strobe goes high, the latched data whose address is represented by the highest six bits of the shift register is
updated. Latched data is set when the least significant bit is 1, and reset when the bit is 0.
4. Referring to 3 above, if the address is h00 (the highest six bits of the shift register are all 0s), the latch circuit is cleared
(all reset) regardless of the data content.
5. At power-on (VCC ON), the latch circuit is cleared (by power-ON reset).
16
ICs for Telephone
AN6472NFBP
■ Logic Circuits Address Specifications
1. Cross-point switch
Output
Input
Handset rec. Line ouput Loudspeaker
Loudspeaker
Intercom
RF1
RF2
Recording
0B
0E
Time stamp
02
09
Microphone
0A
0C
0D
Receiver
10
12
14
15
16
Intercom
18
1A
1C
1D
1E
RF1
20
21
23
RF2
28
29
2B
2C
MIX
30
31
32
33
34
35
AUX
38
39
3A
3B
3C
3D
25
26
2E
37
3E
Note) Empty space means “not applicable.” Address is in hexadecimal.
2. Other control switches
Address
00
07
0F
17
1F
27
2F
3F
09, 21, 29
Description
Cross-point SW all reset
Recording amp. ON
Playing amp. ON
Receiver volume 6 dB up
Receiver volume 9 dB up
Handset receiver amp. mute
SP output amp. gain 12 dB down
MIC preamp. mute
Receiver noise reduction is enabled.
Note) Address is in hexadecimal.
17
ICs for Telephone
AN6472NFBP
■ Timing Charts
1/fCLK
tWL (CLK)
tWh (CLK)
90%
90%
2.5V
2.5V
2.5V
CLK
10%
10%
tr (CLK)
tf (CLK)
DATA
2.5V
2.5V
tsu (DATA)
th (DATA)
tsu (STB)
STR
th (STB)
2.5V
tW (STB)
PD —Ta
Power Dissipation PD (mW)
1,600
1,400
1,200
1,000
900mW
800
640mW
600
400
200
0
0
25
50
75
100
Ambient Temperature Ta (˚C)
18
125
150
2.5V
R30
DH IN
GND
33Ω
15Ω
R36
C36 47µF
R35
C35
100µF
C33 47µF
C34
100µF
C32 0.068µF
C31 0.068µF
C30 0.068µF
C29 0.068µF
RF2 IN
VREG
15Ω
C28 0.068µF
RF1 IN
R34
10kΩ
AUX IN
AUX OUT
R33 10kΩ
MIX IN
C27 100µF
MIX OUT
PV-VREF
R31
R32
EQ OUT
R28
330kΩ
200Ω C26
22µF
C27
0.01µF
+
R29
10kΩ
20kΩ
20kΩ
Vref
L(07)
–
+
–
0dB
0dB
6dB
–
1
L(07)
46
P.O.R
R5 12kΩ
R3
4.7kΩ
3
Power
Interruption
Detector
2
R4
7.7kΩ
R27 1kΩ
DCC
47
C1
0.022µF
+
0dB
C24
4
JP1
+
0/12
dB
10dB
R23
56kΩ
45
44
43
42
7
Noise
Protector
VREF
6
AP
20
dB
ALC
Vref
L(2F)
5
RPRE IN
18
dB
+
Detection
8
40
DMC
DMC
18
dB
JP6
9
AP
Control
0dB
0dB
ALC
Detector
41
JP8
LINK-SP IN
JP5
Vcc
39
10
30dB
0dB
0dB
C39 0.068µF
11
0dB
38
JP4
12
Noise
Control
A P
36
D
a 1
a 2
a 3
a 4
a 5
a 6
R9
47kΩ
C9
0.001µF
13
Rin
14
Rout
RF1. OUT
15
C38
0.1µF
SP
16
0/6/9dB
Rout2
L(27)
DM
Contorol
0dB
Vcc
INJ.
COMP
33
RF2. OUT
DC
Contorol
L(3F)
34
Rout1
0dB
0dB
35
RFILTER
DMC
L(17)
L(1F)
DMC
0dB
VOX
Detector
37
VOXIN
LINK-R OUT
ALC IN
–
R37
820Ω
C37 +
100µF
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
REC IN
R20 220kΩ
REC OUT
TS OUT
PLAY IN
C25 0.47µF R27 1kΩ
R1 27Ω
C26 1µF
Power Supply
Control
JP2
R25 47Ω
R2 470Ω
0560pF
C18
22µF
R24
1kΩ
C2 22µF
DH. OUT
R18
10kΩ
C23
0.01µF
R22
10kΩ
+
C4 100µF
R21 C22 0.15µF
10kΩ
C21 0.1F
C3 0.01µF
JP7
C5 0.01µF
C20 22µF
R5 100kΩ
10kΩ 0.033µF
+
C7 0.1µF
+
R6 10kΩ
+
R7 6.8kΩ
+
R8
12kΩ
+
–
C6 10µF
Latch
C8 0.1µF
C19
R19
Decorder
–
+
+
17
18
19
20
21
22
23
C14 0.0015µF
R12 27kΩ
C12 0.068µF
BT IN
R11
10kΩ
R13 C15
10kΩ 4.7µF
R14 10kΩ
MICOUT
CPC
JP3
DTMF OUT
C13
0.068µF
DTMF IN
MIC
IN–
C16
0.068µF
SW2
SW1
VCC
25
R16 100kΩ
STR
26
24
CLK
27
100kΩ
DATA
R15
2.2kΩ
MIC
IN+
VREG
MIC
VCC
LOGIC
VCC
VOX
OUT
LOGIC GND
C17 100µF
R17 120kΩ
SP
OUT
28
29
30
31
32
R10
Data Input
+
+
19
+
+
–
10kΩ
+
C10 0.068µF
AN6472NFBP
ICs for Telephone
■ AN6472NFBP Applicant Circuit