ATMEL U4091BM

Features
•
•
•
•
Speech Circuit with Anti-clipping
Tone-ringer Interface with DC/DC Converter
Speaker Amplifier with Anti-distortion
Power-supply Management (Regulated and Unregulated) and a Special Supply for
Electret Microphone
• Voice Switch
• Interface for Answering Machine and Cordless Phone
Applications
•
•
•
•
•
Feature Phone
Answering Machine
Fax Machine
Speaker Phone
Cordless Phone
Benefits
• No Piezoelectric Transducer Necessary for Tone Ringing
• Complete System Integration of Analog Signal Processing on One Chip
• Very Few External Components
Programmable
Telephone
Audio
Processor
U4091BM-R
1. Description
The programmable telephone audio processor U4091BM-R is a linear integrated circuit for use in feature phones, answering machines and fax machines. It contains the
speech circuit, tone-ringer interface with DC/DC converter, sidetone equivalent and
ear-protection rectifiers. The circuit is line-powered and contains all components necessary for signal amplification and adaptation to the line. The U4091BM-R can also be
supplied via an external power supply. An integrated voice switch with loudspeaker
amplifier enables hands-free or open-listening operation. With an anti-feedback function, acoustic feedback during open listening can be reduced significantly. The
generated supply voltage is suitable for a wide range of peripheral circuits.
Rev. 4872A–CORD–08/05
Figure 1-1.
Block Diagram
Speech
circuit
Voice
switch
Audio
amplifier
Clock
Data
Reset
Serial
bus
DTMF
2
MCU
Tone
ringer
U4091BM-R
4872A–CORD–08/05
4872A–CORD–08/05
V MIC
18
6
7
41
40
3
4
5
RA
AGC
AGCI
AMPB
SACL
AMREC
AGCO
MICRO
44
Offset
canceler
DTMF
Filter
DTMF/
melody
14
SA
EPO RXLS
13
Switch matrix
LRX
1
AGARX
STBAL
43
34
RECO1
35
AFS
control
LTX
37
MIC
Offset
canceler
TXA
39
33
MICO
36
31
AGATX
42
32
V MP
ADC
MUX
38
24
23
LIDET
25
BIDIR
serial
bus
REG
9
Power
supply
26
3.58 MHz
OSC.
1/8/16/32
DIV.
POR
VMP
8
20
19
21
22
30
11
12
16
15
17
28 29 27
RFDO
Ringing
power
converter
10
µC
optional
V RING
Figure 1-2.
TXACL
2
VL
U4091BM-R
Detailed Block Diagram
3
2. Pin Configuration
Figure 2-1.
4
Pinning SSO44
RECIN
1
44
STRC
TXACL
2
43
STC
MIC3
3
42
STO
MIC2
4
41
AMREC
MIC1
5
40
AMPB
RECO2
6
39
MICO
RECO1
7
38
IMPSW
IND
8
37
TLDT
VL
9
36
INLDT
SENSE
10
35
INLDR
GND
11
34
TLDR
VB
12
33
CT
SAO2
13
32
BNMT
SAO1
14
31
BNMR
VMPS
15
30
ADIN
VMP
16
29
ES
VMIC
17
28 OSCOUT
TSACL
18
27 RESET
VRING
19
26
OSCIN
IMPA
20
25
SDA
COSC
21
24
SCL
SWOUT
22
23
INT
U4091BM
U4091BM-R
4872A–CORD–08/05
U4091BM-R
Table 2-1.
Pin Description
Pin
Symbol
Function
1
RECIN
Receive amplifier input(1)
2
TXACL
Time constant adjustment for transmit anti-clipping
3
MIC3
Microphone input for hands-free operation
4
MIC2
Input of symmetrical microphone amplifier with high common-mode rejection ratio
5
MIC1
Input of symmetrical microphone amplifier with high common-mode rejection ratio
6
RECO2
Output of the receive amplifier
7
RECO1
Output of the receive amplifier, also used for sidetone network
8
IND
The internal equivalent inductance of the circuit is proportional to the value of the capacitor at this pin. A
resistor connected to ground may be used to adjust the DC mask
9
VL
10
SENSE
Positive supply-voltage input to the device in speech mode
11
GND
Ground, reference point for DC and AC signals
12
VB
Unstabilized supply voltage for speech network
Input for sensing the available line current
13
SAO2
Negative output of speaker amplifier (push-pull only)
14
SAO1
Positive output of speaker amplifier (single-ended and push-pull operation)
15
VMPS
Unregulated supply voltage for the microcontroller (via series regulator to VMP)
16
VMP
Regulated output voltage for supplying the microcontroller (typically 3.3V/6 mA in speech mode)
17
VMIC
18
TSACL
Time constant for speaker amplifier anti-clipping
Reference node for microphone amplifier, supply for electret microphones
19
VRING
Input for ringer supply
20
IMPA
Input for adjusting the ringer input impedance
21
COSC
70-kHz oscillator for ringing power converter
22
SWOUT
Output for driving the external switch resistor
23
INT
Interrupt line for serial bus
24
SCL
Clock input for serial bus
25
SDA
26
OSCIN
Input for 3.58-MHz oscillator
Data line for serial bus
27
RESET
Reset output for the microcontroller
28
OSCOUT
Clock output for the microcontroller
29
ES
30
ADIN
Input of A/D converter
Input for external supply indication
31
BNMR
Output of background-noise monitor receive
32
BNMT
Output of background-noise monitor transmit
33
CT
34
TLDR
Time constant of receive-level detector
35
INLDR
Input of receive-level detector
36
INLDT
Input of transmit-level detector
37
TLDT
38
IMPSW
39
MICO
Note:
Time constant for mode switching of voice switch
Time constant of transmit-level detector
Switch for additional line impedance
Microphone preamplifier output
1. The protection device at pin RECIN is disconnected.
5
4872A–CORD–08/05
Table 2-1.
Pin Description
Pin
Symbol
Function
40
AMPB
Input for playback signal of answering machine
41
AMREC
42
STO
Output for connecting the sidetone network
43
STC
Input for sidetone network
44
STRC
Input for sidetone network
Note:
Output for recording signal of answering machine
1. The protection device at pin RECIN is disconnected.
3. DC Line Interface and Supply-voltage Generation
The DC line interface consists of an electronic inductance and a dual-port output stage which
charges the capacitors at VMPS and VB. The value of the equivalent inductance is given by:
2 × R SENSE × C IND × ( R DC × R 30 )
L = -----------------------------------------------------------------------------------------( R DC + R 30 )
The U4091BM-R contains two identical series regulators which provide a supply voltage VMP of
3.3V suitable for a microprocessor. In speech mode, both regulators are active because VMPS
and VB are charged simultaneously by the DC line interface. The output current is 6 mA. The
capacitor at VMPS is used to provide the microcomputer with sufficient power during long line
interruptions. Thus, long flash pulses can be bridged or an LCD display can be turned on for
more than 2 seconds after going on-hook. When the system is in ringing mode, VB is charged by
the on-chip ringing power converter. In this mode, only one regulator is used to supply VMP with
maximum 3 mA.
4. Supply Structure of the Chip
A main benefit of the U4091BM is the easy implementation of various applications due to the
flexible system structure of the chip.
Possible applications:
• Group listening phone
• Hands-free phone
• Phones which feature ringing with the built-in speaker amplifier
• Answering machine with external supply
The special supply topology for the various functional blocks is shown in Figure 4-1 on page 7.
There are four major supply states:
1. Speech condition
In speech condition, the system is supplied by the line current. If the LIDET block
detects a line voltage above approximately 2V, the internal signal VLON is activated.
This is detected via the serial bus, all the blocks which are needed have to be switched
on via the serial bus.
For line voltages below 2V, the switches remain in quiescent state as shown in the
diagram.
6
U4091BM-R
4872A–CORD–08/05
U4091BM-R
2. Power down (pulse dialing)
When the chip is in power-down mode (bit LOMAKE), for example, during pulse dialing,
all internal blocks are disabled via the serial bus. In this condition, the voltage regulators and their internal band gap are the only active blocks.
3. Ringing
During ringing, the supply for the system is fed into VB via the Ringing Power Converter
(RPC). Normally, the speaker amplifier in single-ended mode is used for ringing. The
frequency for the melody is generated by the DTMF/Melody generator.
4. External supply
In an answering machine, the chip is powered by an external supply via pin VB. The
answering machine connections can be directly made to U4091BM-R. The answering
machine is connected to the pin AMREC. For the output AMREC, an AGC function is
selectable via the serial bus. The output of the answering machine will be connected to
the pin AMPB, which is directly connected to the switching matrix. This enables the signal to be switched to every desired output.
Figure 4-1.
Supply Generator
VL
RSENSE
10
5.5V
C
VMPS
470 µF
1 µF
IND
R
+
R
300 kΩ
+
+
-
3.3V
VMP
47 µF
5.5V
VB
V
220 µF
5. Ringing Power Converter (RPC)
The RPC transforms the input power at VRING (high voltage/low current) into an equivalent output power at VB (low voltage/high current) which is capable of driving the low-ohmic
loudspeaker. The input impedance at VRING is adjustable from 3 kΩ to 12 kΩ by R IMPA
(ZRING = RIMPA / 100) and the efficiency of the step-down converter is approximately 65%.
6. Ringing Frequency Detector (RFD)
The U4091BM-R provides an output signal for the microcontroller. This output signal is always
double the value of the input signal (ringing frequency). It is generated by a current comparator
with hysteresis. The levels for the on-threshold are programmable in 16 steps, the off-level is
fixed. Every change of the comparator output generates a high level at the interrupt output INT.
The information can then be read out by means of a serial bus with either normal or fast read
mode. The block RFD is always enabled.
7
4872A–CORD–08/05
Table 6-1.
Threshold Level
RINGTH[0:3]
VRING
0
7V
15
22V
Step
1V
7. Clock Output Divider Adjustment
The pin OSCOUT is a clock output which is derived from the crystal oscillator. It can be used to
drive a microcontroller or another remote component and thereby reduces the number of crystals required. The oscillator frequency can be divided by 1, 8, 16, or 32. During power-on reset,
the divider will be reset to 1 until it is changed by setting the serial bus.
Table 7-1.
Clock Output
CLK[0:1]
Divider
Frequency
0
1
3.58 MHz
1
8
447 kHz
2
16
224 kHz
3
32
112 kHz
8. Serial Bus Interface
The circuit is controlled by an external microcontroller through the serial bus.
The serial bus is a bi-directional system consisting of a single-directional clock line (SCL) which
is always driven by the microcontroller, and a bi-directional data-signal line. It is driven by the
microcontroller as well as by the U4091BM-R (see Figure 20-1 on page 37).
The serial bus requires external pull-up resistors as only pull-down transistors (pin SDA) are
integrated.
8.1
WRITE
The data is a 12-bit word:
A0-A3: address of the destination register (0 to 15)
D0-D7: content of the register
The data line must be stable when the clock is high. Data must be shifted serially. After 12 clock
periods, the write indication is sent. Then, the transfer to the destination register is (internally)
generated by a strobe signal transition of the data line when the clock is high.
8.2
READ
There is a normal and a fast-read cycle.
In the normal read cycle, the microcontroller sends a 4-bit address followed by the read indicator, then an 8-bit word is read out. The U4091BM-R drives the data line.
The fast read cycle is indicated by a strobe signal. With the following two clocks the U4091BM-R
reads out the status bits RFDO and LIDET which indicate that a ringing signal or a line signal is
present (see Figure 10-1 on page 11, Figure 10-2 on page 11 and Figure 10-3 on page 11).
8
U4091BM-R
4872A–CORD–08/05
U4091BM-R
9. DTMF Dialing
The DTMF generator sends a multi-frequency signal through the matrix to the line. The signal is
the result of the sum of two frequencies and is internally filtered. The frequencies are chosen
from a low and a high frequency group. The circuit conforms to the CEPT recommendation concerning DTMF option. Three different levels for the low level group and two different preemphasis (2.5 dB and 3.5 dB) can be chosen by means of the serial bus (rec. T/CF 46-03).
Attention: In high gain mode, distortion can occur if AGATX is high and DC mask is low.
10. Melody and Confidence Tone Generation
Melody and confidence tone frequencies are given in Table 10-1.
The frequencies are provided at the DTMF input of the switch matrix. A sinusoidal wave, a
square wave or a pulsed wave can be selected by the serial bus. A square signal means the output is high for half of the frequency cycle, and low for the other half. A pulsed signal means high
impedance phases of 1/6 of the period occur between the high and low phases.
Table 10-1.
Status of Melody Generating
Decimal
DTMFM[0:2]
0
000
DTMF generator OFF
1
001
Confidence tone melody on (sine)
2
010
Ringer melody (pulse)
3
011
Ringer melody (square signal)
4
100
DTMF (mid level)
5
101
DTMF (low level)
6
110
DTMF (high level)
7
111
–
Table 10-2.
Status
DTMF Frequencies
Decimal
DTMFF[0:1]
in DTMF Mode
Frequency
Error (%)
0
00
697
–0.007
1
01
770
–0.156
2
10
852
0.032
3
11
941
0.316
Decimal
DTMFF[2:3]
in DTMF Mode
Frequency
Error (%)
0
00
1209
–0.110
1
01
1336
0.123
2
10
1477
–0.020
3
11
1633
–0.182
Table 10-3.
DTMF Frequencies
9
4872A–CORD–08/05
Table 10-4.
Table 10-5.
Decimal
0
Pre-emphasis Selection
Level
0
2.5 dB
1
3.5 dB
DTMF and Melody Frequencies
DTMFF
[0:4]
00000
f
(Hz)
440.0
Tone/
Name
A
4
4
Error (%)
DTMF
Freq.
DTMP
Freq.
Key
–0.008
697
1209
1
1
00001
466.2
A#
–0.016
770
1209
4
2
00010
493.9
B4
–0.003
852
1209
7
523.2
4
0.014
941
1209
*
0.018
697
1336
2
3
4
00011
00100
C
4
554.4
C#
4
5
00101
587.3
D
–0.023
770
1336
5
6
00110
622.3
D#4
–0.129
852
1336
8
4
0.106
941
1336
0
4
–0.216
697
1477
3
7
8
00111
01000
659.3
698.5
E
F
4
9
01001
740.0
F#
–0.222
770
1477
6
10
01010
784.0
G4
0.126
852
1477
9
–0.169
941
1477
#
0.288
697
1633
A
11
12
13
01011
01100
01101
4
830.0
G#
880.0
5
A
5
932.3
A#
–0.014
770
1633
B
5
–0.004
852
1633
C
–0.335
941
1633
D
14
01110
987.8
B
15
01111
1046.5
C5
16
17
10000
10001
5
1108.7
C#
–0.355
697
1209
1
1174.7
5
–0.023
770
1209
4
D
5
18
10010
1244.5
D#
–0.129
852
1209
7
19
10011
1318.5
E5
0.106
941
1209
*
1396.9
5
–0.214
697
1336
2
–0.222
770
1336
5
20
21
10100
10101
F
5
1480.0
F#
5
22
10110
1568.0
G
0.126
852
1336
8
23
10111
1661.2
G#5
–0.241
941
1336
0
24
11000
1760.0
A6
–0.302
697
1477
3
25
11001
6
1864.6
A#
–0.014
770
1477
6
6
0.665
852
1477
9
0.367
941
1477
#
26
11010
1975.5
B
27
11011
2093.0
C6
28
10
DTMFF4 in DTMF Mode
11100
6
2217.5
C#
0.387
697
1633
A
6
0.771
770
1633
B
29
11101
2349.3
D
30
11110
2663.3
---
852
1633
C
31
11111
2983.0
---
941
1633
D
U4091BM-R
4872A–CORD–08/05
U4091BM-R
Figure 10-1. Write Cycle
Write cycle
CLOCK
DATA
D7
D6
D5
D4
D3
D2
D1
D0
A3
A2
A1
A0
R/W=0
Data from µP
Strobe
from µP
Figure 10-2. Normal Read Cycle
Normal read cycle
CLOCK
DATA
A3
A2
A1
A0
R/W = 1
D7
D6
Strobe
from µP
Data from µP
D5
D4
D3
D2
D1
D0
Data from U4091BM
Figure 10-3. Fast Read Cycle
Fast read cycle
CLOCK
DATA
D7=IZC
Strobe
from µP
D6=IVE
Data from U4091BM
11
4872A–CORD–08/05
Table 10-6.
Register
R0
R1
R2
R3
12
Names and Functions of the Serial Registers
Group
Enables
Enables
Matrix
Matrix
No.
Name
Description
Status
R0B0
ENRING
Enable ringer
R0B1
ERX
Enable receive part
0
R0B2
ETX
Enable transmit part
0
R0B3
ENVM
Enable VM generator
R0B4
ENMIC
Enable microphone
0
R0B5
ENSTBAL
Enable sidetone
0
R0B6
MUTE
Muting earpiece amplifier
0
R0B7
ENRLT
Enable POR low threshold
R1B0
ENSACL
Enable anti-clipping for speaker amplifier
0
R1B1
ENSA
Enable speaker amplifier and AFS
0
1
1
1
R1B2
ENSAO
Enable output stage speaker amplifier
0
R1B3
ENAM
Enable answering machine connections
0
R1B4
ENAGC
Enable AGC for answering machine
0
R1B5
Reserved
-
0
R1B6
Reserved
-
0
R1B7
FOFFC
Speed up offset canceller
0
R2B0
I1O1
Switch on MIC/LTX
0
R2B1
I1O2
Switch on MIC/SA
0
R2B2
I1O3
Switch on MIC/EPO
0
R2B3
I1O4
Switch on MIC/AMREC
0
R2B4
I1O5
Switch on MIC/AGCI
0
R2B5
I2O1
Switch on DTMF/LTX
0
R2B6
I2O2
Switch on DTMF/SA
0
R2B7
I2O3
Switch on DTMF/EPO
0
R3B0
I2O4
Switch on DTMF/AMREC
0
R3B1
I2O5
Switch on DTMF/AGCI
0
R3B2
I3O1
Switch on LRX/LTX
0
R3B3
I3O2
Switch on LRX/SA
0
R3B4
I3O3
Switch on LRX/EPO
0
R3B5
I3O4
Switch on LRX/AMREC
0
R3B6
I3O5
Switch on LRX/AGCI
0
R3B7
I4O1
Switch on AMPB/LTX
0
U4091BM-R
4872A–CORD–08/05
U4091BM-R
Table 10-6.
Names and Functions of the Serial Registers (Continued)
Register
R4
R5
R6
R7
R8
Group
Matrix
AGATX
MICLIM
Shut down
Sidetone
Sidetone
AGARX
EARA
Line
impedance
No.
Name
Description
Status
R4B0
I4O2
Switch on AMPB/SA
0
R4B1
I4O3
Switch on AMPB/EPO
0
R4B2
I4O4
Switch on AMPB/AMREC
0
R4B3
I4O5
Switch on AMPB/AGCI
0
R4B4
I5O1
Switch on AGCO/LTX
0
R4B5
I5O2
Switch on AGCO/SA
0
R4B6
I5O3
Switch on AGCO/EPO
0
R4B7
I5O4
Switch on AGCO/AMREC
0
R5B0
EAFS
Enable AFS block
0
R5B1
AGATX0
Gain transmit AGA LSB
0
R5B2
AGATX1
Gain transmit AGA
0
R5B3
AGATX2
Gain transmit AGA MSB
0
R5B4
MICHF
Select RF-microphone input
0
R5B5
DBM5
Maximum transmit level for anti-clipping
0
R5B6
MIC0
Gain microphone amplifier LSB
0
R5B7
MIC1
Gain microphone amplifier MSB
0
R6B0
SD
Shut down
0
R6B1
Reserved
-
0
R6B2
SL0
Slope adjustment for sidetone LSB
0
R6B3
SL1
Slope adjustment for sidetone MSB
0
R6B4
LF0
Low frequency adjustment for sidetone LSB
0
R6B5
LF1
Low frequency adjustment for sidetone
0
R6B6
LF2
Low frequency adjustment for sidetone
0
R6B7
LF3
Low frequency adjustment for sidetone MSB
0
R7B0
P0
Pole adjustment for sidetone LSB
0
R7B1
P1
Pole adjustment for sidetone
0
R7B2
P2
Pole adjustment for sidetone
0
R7B3
P3
Pole adjustment for sidetone
0
R7B4
P4
Pole adjustment for sidetone MSB
0
R7B5
AGARX0
Gain receive AGC LSB
0
R7B6
AGARX1
Gain receive AGC
0
R7B7
AGARX2
Gain receive AGC MSB
0
R8B0
EA0
Gain earpiece amplifier LSB
0
R8B1
EA1
Gain earpiece amplifier
0
R8B2
EA2
Gain earpiece amplifier
0
R8B3
EA3
Gain earpiece amplifier
0
R8B4
EA4
Gain earpiece amplifier MSB
0
R8B5
IMPH
Line impedance selection (1 = 1 kΩ)
0
R8B6
LOMAKE
Short circuit during pulse dialing
0
R8B7
AIMP
Switch for additional external line impedance
0
13
4872A–CORD–08/05
Table 10-6.
Register
R9
R10
R11
R12
R13
14
Names and Functions of the Serial Registers (Continued)
Group
AFS
SA
ADC
DTMF
CLK
RTH
TM
No.
Name
Description
Status
R9B0
AFS0
AFS gain adjustment LSB
0
R9B1
AFS1
AFS gain adjustment
0
R9B2
AFS2
AFS gain adjustment
0
R9B3
AFS3
AFS gain adjustment
0
R9B4
AFS4
AFS gain adjustment
0
R9B5
AFS5
AFS gain adjustment MSB
0
R9B6
AFS4PS
Enable 4-point sensing
0
R9B7
Reserved
-
0
R10B0
SA0
Gain speaker amplifier LSB
0
R10B1
SA1
Gain speaker amplifier
0
R10B2
SA2
Gain speaker amplifier
0
R10B3
SA3
Gain speaker amplifier
0
R10B4
SA4
Gain speaker amplifier MSB
0
R10B5
SE
Speaker amplifier single-ended mode
0
R10B6
LSCUR0
Speaker amplifier charge-current adjustment LSB
0
R10B7
LSCUR1
Speaker amplifier charge-current adjustment MSB
0
R11B0
ADC0
Input selection ADC
0
R11B1
ADC1
Input selection ADC
0
R11B2
ADC2
Input selection ADC
0
R11B3
ADC3
Input selection ADC
0
R11B4
NWT
Network tuning
0
R11B5
SOC
Start of ADC conversion
0
R11B6
ADCR
Selection of ADC range
0
R11B7
MSKIT
Mask for interrupt bits
0
R12B0
DTMFF0
DTMF frequency selection
0
R12B1
DTMFF1
DTMF frequency selection
0
R12B2
DTMFF2
DTMF frequency selection
0
R12B3
DTMFF3
DTMF frequency selection
0
R12B4
DTMFF4
DTMF frequency selection
0
R12B5
DTMFM0
Generator mode selection
0
R12B6
DTMFM1
Generator mode selection
0
R12B7
DTMFM2
Generator mode selection
0
R13B0
CLK0
Selection clock frequency for microcontroller
0
R13B1
CLK1
Selection clock frequency for microcontroller
0
R13B2
RTH0
Ringer threshold adjustment LSB
0
R13B3
RTH1
Ringer threshold adjustment
0
R13B4
RTH2
Ringer threshold adjustment
0
R13B5
RTH3
Ringer threshold adjustment MSB
0
R13B6
TME0
Test mode enable (low active)
0
R13B7
TME1
Test mode enable (high active)
0
U4091BM-R
4872A–CORD–08/05
U4091BM-R
Table 10-6.
Names and Functions of the Serial Registers (Continued)
Register
TM
CLOR
R14
R15
10.1
Group
CLOT
No.
Name
Description
Status
R14B0
TME2
Test mode enable (high active)
0
R14B1
TME3
Test mode enable (low active)
0
R14B2
Reserved
-
0
R14B3
CLOR0
Adjustment for calculated receive log amp LSB
0
R14B4
CLOR1
Adjustment for calculated receive log amp
0
R14B5
CLOR2
Adjustment for calculated receive log amp
0
R14B6
CLOR3
Adjustment for calculated receive log amp
0
R14B7
CLOR4
Adjustment for calculated receive log amp MSB
0
R15B0
Reserved
-
0
R15B1
Reserved
-
0
R15B2
Reserved
-
0
R15B3
CLOT0
Adjustment for calculated transmit log amp LSB
0
R15B4
CLOT1
Adjustment for calculated transmit log amp
0
R15B5
CLOT2
Adjustment for calculated transmit log amp
0
R15B6
CLOT3
Adjustment for calculated transmit log amp
0
R15B7
CLOT4
Adjustment for calculated transmit log amp MSB
0
Power-on Reset
To avoid undefined states of the system when it is powered on, an internal reset clears the internal registers.
The system (U4091BM-R + microcontroller) is woken up by any of the following conditions:
• VMP > 2.75V and VB > 2.95V
• and line voltage (VL)
• or ringer (VRING)
• or external supply (ES)
The power-down of the circuit is caused by a shut-down sent by the serial bus (SD = 1), low-voltage reset, or by the watchdog function (see Figure 12-2 on page 17, Figure 12-3 on page 17 and
Figure 12-4 on page 17).
11. Watchdog Function
To avoid the system operating the microcontroller in a fault state, the circuit provides a watchdog
function. The watchdog has to be retriggered every second by triggering the serial bus (sending
information to the IC or other remote components at the serial bus). If there has been no bus
transmission for more than one second, the watchdog initiates a reset.
The watchdog provides a reset for the external microcontroller, but does not change the
U4091BM-R’s registers.
15
4872A–CORD–08/05
12. Acoustic Feedback Suppression
Acoustical feedback from the loudspeaker to the hands-free microphone may cause instability of
the system. The U4091BM-R has a very efficient feedback-suppression circuit which offers a
4-point or (alternatively) a 2-point signal-sensing topology (see Figure 12-1).
Two attenuators (TXA and SAI) reduce the critical loop gain via the serial bus either in the transmit or in the receive path. The overall loop gain remains constant under all operating conditions.
The LOGs produce a logarithmically-compressed signal of the TX- and RX-envelope curve. The
AFSCON block determines whether the TX or the RX signal has to be attenuated.
The voice-switch topology can be selected by the serial bus. In 2-point-sensing mode, AFSCON
is controlled directly by the LOG outputs.
Figure 12-1. Basic System Configurations
MICRO
AGATX
TXA
MICO
STO
CTU
CTLO
CBNMT
RTU
TLDT
BNMT
INLDT
LOG
CALCT
LOG
BNM
Mode
control
Line
BNM
AGARX
LOG
CALCR
LOG
INLDR
CT
BNMR
TLDR
CCT
CBNMR
CRLO
CRU
RECO1
AFSCON
HV
DTD
SA
SAI
16
RRU
RECO2
U4091BM-R
4872A–CORD–08/05
U4091BM-R
Figure 12-2. Power-on Reset (Line)
Line
LID
IVDD
OSCOUT
ton
VMP
Reset
trt
trt - ton = 4.5 ms
ton = start-up oscillator
Figure 12-3. Power-on Reset (Ringing)
VRING
VB
IVDD
VMP
OSCOUT
ton
Reset
trt
Figure 12-4. Power-on Reset (Low Voltage Reset)
Line
LID
VMP
LVI
LVR
LVI
Reset
OSCOUT
17
4872A–CORD–08/05
12.1
Dial-tone Detector
The dial-tone detector is a comparator with one side connected to the speaker amplifier input
and the other to VM with a 35-mV offset (see Figure 12-5 on page 21). If the circuit is in idle
mode, and the incoming signal is greater than 35 mV (25 mVrms), the comparator's output will
change thus disabling the receive idle mode. This circuit prevents the dial tone (which would be
considered as continuous noise) from fading away as the circuit would have the tendency to
switch to idle mode. By disabling the receive idle mode, the dial tone remains at the normally
expected full level.
12.2
Background Noise Monitors
This circuit distinguishes speech (which consists of bursts) from background noise (a relatively
constant signal level). There are two background-noise monitors, one for the receive path and
the other for the transmit path. The receive background-noise monitor is operated on by the
receive level detector, while the transmit background noise monitor is operated on by the transmit level detector (see Figure 12-6 on page 21). They monitor the background noise by storing a
DC voltage representative of the respective noise levels in capacitors at CBNMR and CBNMT.
The voltages at these pins have slow rise times (determined by the internal current source and
an external capacitor), but fast decay times. If the signal at TLDR (or TLDT) changes slowly, the
voltage at BNMR (or BNMT) will remain more positive than the voltage at the non-inverting input
of the monitor's output comparator. When speech is present, the voltage at the non-inverting
input of the comparator will rise more quickly than the voltage at the inverting input (due to the
burst characteristic of speech), causing its output to change. This output is sensed by the modecontrol block.
12.3
4-point Sensing
In 4-point-sensing mode, the receive- and the transmit-sensing paths include additional CLOGs
(calculated logarithmic amplifiers). The block MODECON compares the detector output signals
and decides whether receive, transmit or idle mode has to be activated. Depending on the mode
decision, MODECON generates a differential voltage to control AFSCON.
The MODECON block has seven inputs:
• The output of the transmit log (LOGT) – the comparison of LOGT, CLOGR
• The output of the receive clog (CLOGR) – designated I1
• The output of the transmit clog (CLOGT) – the comparison of CLOGT, LOGR
• The output of the receive log (LOGR) – designated I2
• The output of the transmit background-noise monitor (BNMT) – designated I3
• The output of the receive background-noise monitor (BNMR) – designated I4
• The output of the dial-tone detector
The differential output (AFST, AFSR) of the block MODECON controls AFSCON. The effect of
I1-I4 in Table 12-1 on page 19.
18
U4091BM-R
4872A–CORD–08/05
U4091BM-R
Table 12-1.
Mode Decision for Signal Sensing
Input
Note:
I1
I2
I3
I4
Mode
T
T
S
X
Transmit
T
R
Y
Y
Change mode
R
T
Y
Y
Change mode
R
R
X
S
Receive
T
T
N
X
Idle
T
R
N
N
Idle
R
T
N
N
Idle
R
R
X
N
Idle
X = don’t care; Y = I3 and I4 are not both noise.
LOGT > CLOGR
LOGT < CLOGR
LOGR < CLOGT
LOGR > CLOGT
BNMT detects speech
BNMT detects noise
BNMR detects speech
BNMR detects noise
12.4
Output
I1 = T
I1 = R
I2 = T
I2 = R
I3 = S
I3 = N
I4 = S
I4 = N
Term Definitions
1. Transmit means the transmit attenuator is fully on, and the receive attenuator is at maximum attenuation.
2. Receive means the receive attenuator is fully on, and the transmit attenuator is at maximum attenuation.
3. In idle mode, the transmit and receive attenuator are at half of their maximum
attenuation.
– Change mode means both the transmit and receive speech are present in
approximately equal levels. The attenuators are quickly switched (30 ms) to the
opposite mode until one speech level dominates the other.
– Idle means speech has ceased in both transmit and receive paths. The attenuators
are then slowly switched (1.5s) to idle mode.
4. Switching to full transmit or receive modes from the idle mode is done at a fast rate
(30 ms).
19
4872A–CORD–08/05
12.5
Summary of Truth Table
1. The circuit will switch to transmit mode if
– Both transmit level detectors sense higher signal levels than the respective receive
level detectors, and
– The transmit background-noise monitor indicates the presence of speech
2. The circuit will switch to receive mode if
– Both receive level detectors sense higher signal levels than the respective transmit
level detectors, and
– The receive background-noise monitor indicates the presence of speech
3. The circuit will switch to the reverse mode if
– The level detectors disagree on the relative strengths of the signal levels, and
– At least one of the background-noise monitors indicates speech
4. The circuit will switch to idle mode when
– Both speakers are quiet (no speech present), or
– When one speaker speech level is continuously overridden by noise at the other
speaker’s location
The time required to switch the circuit between transmit, receive and idle is determined by internal current sources and the capacitor at pin CT. A diagram of the CT circuitry is shown in Figure
12-7 on page 21. It operates as follows:
• CCT is typically 4.7 µF.
• To switch to transmit mode, ITX is turned on (IRX is off), charging the external capacitor to
–240 mV below VM. (An internal clamp prevents further charging of the capacitor.)
• To switch to receive mode, IRX is turned on (ITX is off), increasing the voltage on the
capacitor to +240 mV with respect to VM.
• To switch to reverse mode, the current sources ITX, IRX are turned off, and the current
source IFI is switched on, discharging the capacitor to VM.
• To switch to idle mode, the current sources ITX, IRX, IFI are turned off, and the current
source ISI charges the capacitor to VM.
20
U4091BM-R
4872A–CORD–08/05
U4091BM-R
Figure 12-5. Dial Tone Detector
IN
OUT
+
-
35 mV
VM
to mode
control
I4
DTD
Figure 12-6. Background Noise Monitor
VB
BNMR
(BNMT)
TLDR
(TLDT)
+
-
1 µF
+
+
56 kΩ
36 mV
33 kΩ
I4
(I3)
VM
Figure 12-7. Generation of Control Voltage (CT) for Mode Switching
AFS
control
CT
CCT
to
attenuators
IRX
10 µA ITX
Control
circuit
10 µA IFI
4
I1-4
ISI
Dial tone det.
VM
VM
21
4872A–CORD–08/05
Figure 12-8. Block Diagram Hands-free Mode U4091BM-R 2-point Signal Sensing
TXA
MICRO
LOG
Line
AFS
control
LOG
SA
SAI
Figure 12-9. Block Diagram Hands-free Mode U4091BM-R 4-point Signal Sensing
TXA
MICRO
CLOGT
LOGT
BNMT
Line
Mode
control
BNMR
CLOGR
LOGR
CT
CCT
AFS
control
DTD
SA
SAI
22
U4091BM-R
4872A–CORD–08/05
U4091BM-R
13. Analog-to-Digital Converter (ADC)
This circuit is a 7-bit successive-approximation analog-to-digital converter in switched capacitor
technique. An internal band gap circuit generates a 1.25-V reference voltage which is the equivalent of 1 MSB (1 LSB = 19.5 mV). The possible input voltage at ADIN is 0V to 2.48V.
The ADC needs an SOC (Start Of Conversion) signal. In the High phase of the SOC signal, the
ADC is reset. Then, 50 µs after the beginning of the Low phase of the SOC signal, the ADC generates an EOC (End Of Conversion) signal which indicates that the conversion is finished. The
rising edge of EOC generates an interrupt at the INT output. The result can be read out by the
serial bus.
Voltages higher than 2.45V have to be divided. The signal connected to the ADC is determined
by 4 bits: ADC0, ADC1, ADC2 and ADC3. TLDR/TLDT measuring is possible relative to a preceding reference measurement. The current range of IL can be doubled by ADCR. If ADCR is
High, S has the value 0.5, otherwise S = 1.
The source impedance at ADIN must be lower than 250 kΩ.
Accuracy: 1 LSB + 3%
Figure 13-1. Timing of ADC
SOC
50 µs
EOC
Figure 13-2. ADC Input Selection
IL x 20 mV/(1 mA x S )
S OC
ADIN
0.4 x VB
MS B
0.4 x VMP S
BIT5
0.4 x VMP
BIT4
8 x (TLDR - REF)
ADC
BIT3
8 x (TLDT - REF)
BIT2
0.4 x S AO1
BIT1
0.4 x OFF1
LS B
0.4 x OFF2
0.4 x OFF3
EOC
23
4872A–CORD–08/05
Table 13-1.
Note:
24
Input Selection ADC
Decimal
ADC[1:4]
Symbol
Value
0
0000
OFF
-
1
0001
IL
I1 = S × 127 mA × D / 128
2
0010
ADIN extern
V2 = 2.5V × D / 128 (maximum 2.5V)
3
0011
VB
V3 = (2.5V / 0.4) × D / 128
4
0100
VMPS
V4 = (2.5V / 0.4) × D / 128
5
0101
VMP
V5 = (2.5V / 0.4) × D / 128
6
0110
TLDR
V6 = 8 × (Vp – Ref) × D / 128
7
0111
TLDT
V7 = 8 × (Vp – Ref) × D / 128
8
1000
Not used
-
9
1001
SAO1
V4 = (2.5V / 0.4) × D / 128
10
1010
Offcan1
Atmel’s internal use
11
1011
Offcan2
-
12
1100
Offcan3
-
13
1101
Not used
-
14
1110
Not used
-
15
1111
Not used
-
D = measured digital word (0 ≤ D ≤ 127)
S = programmable gain 0.5 or 1
Vp = peak value of the measured signal
U4091BM-R
4872A–CORD–08/05
U4091BM-R
14. Switch Matrix
The switch matrix has 5 inputs and 5 outputs. Every pair of I/Os except AGCO and AGCIN can
be connected. The inputs and outputs used must be enabled. If 2 or more inputs are switched to
an output, the sum of the inputs is available at the output.
The inputs MIC and LRX have offset cancellers with a 3-dB corner frequency of 270Hz. AMPB
has a 60-kΩ input impedance. The TXO output has a digitally-programmable gain stage with a
gain of 2 dB to 9 dB (in 1 dB steps) depending on AGATX0 (LSB), AGATX1, AGATX2 (MSB),
and a first order low-pass filter with 0.5 dB damping at 3300Hz and 3 dB damping at 9450Hz.
The outputs RXLS, EPO and AMREC have a gain of 0 dB. The offset at the outputs of the matrix
is less than 30 mV. If a switch is open, the path has a damping of more than 60 dB.
Figure 14-1. Switch Matrix Diagram
AGCO
I5
AMPB LRX DTMF
MIC
Offset
cancel
Offset
cancel
I4
I3
I2
I1
AGC
Low pass
O5
O4
O3
O2
O1
2.9 dB
AGCI
LTX
AMREC EPO RXLS
AGATX0
AGATX1
AGATX2
TXO
-10 dB
STO
25
4872A–CORD–08/05
Table 14-1.
Register
R2
R3
R4
26
Bits and Corresponding Switches
No.
Name
Description
R2B0
I1O1
Switch on MIC/LTX
R2B1
I1O2
Switch on MIC/RXLS
R2B2
I1O3
Switch on MIC/EPO
R2B3
I1O4
Switch on MIC/AMREC
R2B4
I1O5
Switch on MIC/AGCI
R2B5
I2O1
Switch on DTMF/LTX
R2B6
I2O2
Switch on DTMF/RXLS
R2B7
I2O3
Switch on DTMF/EPO
R3B0
I2O4
Switch on DTMF/AMREC
R3B1
I2O5
Switch on DTMF/AGCI
R3B2
I3O1
Switch on LRX/LTX
R3B3
I3O2
Switch on LRX/RXLS
R3B4
I3O3
Switch on LRX/EPO
R3B5
I3O4
Switch on LRX/AMREC
R3B6
I3O5
Switch on LRX/AGCI
R3B7
I4O1
Switch on AMPB/LTX
R4B0
I4O2
Switch on AMPB/RXLS
R4B1
I4O3
Switch on AMPB/EPO
R4B2
I4O4
Switch on AMPB/AMREC
R4B3
I4O5
Switch on AMPB/AGCI
R4B4
I5O1
Switch on AGCO/LTX
R4B5
I5O2
Switch on AGCO/RXLS
R4B6
I5O3
Switch on AGCO/EPO
R4B7
I5O4
Switch on AGCO/AMREC
U4091BM-R
4872A–CORD–08/05
U4091BM-R
15. Sidetone System
Figure 15-1. Principle Circuit of Sidetone Balancing
LINE
LTX
8 dB
CK
ZL
LRX
0 - 7 dB
+
MOD
DIFF1
RECIN
-10 dB
AGARX
AMP1
STO_DIFF
9 dB
STO
-10 dB
STOAMP
AMP2
STO
8.2 kΩ
Sidetone balancing
g
LF
STRC
P
CTO
33 nF
SL
STC
f
LF
P
SL
The Sidetone Balancing (STB) has the task of reducing the cross-talk from LTX (microphone) to
LRX (earpiece) in the frequency range of 0.3 kHz to 3.4 kHz. The LTX signal is converted into a
current in the MOD block. This current is transformed into a voltage signal (LINE) by the line
impedance ZL. The LINE signal is fed into the summing amplifier DIFF1 via capacitor CK and
attenuator AMP1.
On the other hand the LTX buffered by STOAMP drives an external low-pass filter (RST, CST).
The external low-pass filter and the internal STB have the transfer function drawn in the STB
box. The amplified STB output signal drives the negative input of the summing block. If both signals at the DIFF1 block are equal in level and phase, we have good suppression of the LTX
signal. In this condition, the frequency and phase response of the STB block will represent the
frequency curve on line.
In real life, the line impedance ZL varies strongly for different users. To obtain good suppression
with one application for all different line impedances, the STB function is programmable.
27
4872A–CORD–08/05
The 3 programmable parameters are
1. LF (gain at low frequency)
LF has 15 programming steps of 0.5 dB
LF(0) provides –2 dB gain, LF(15) provides 5.5 dB gain
STO_DIFF(LF) = (–10 dB – 2 dB + 0.5 dB × LF + 9 dB) × LTX
2. P (the pole position of the low-pass)
The P adjustment has 31 steps. P(0) means the lowpass determined by the external
application (RST, CST). The internally processed low-pass frequency is fixed by the following equation.
1
P
f(P) = ---------------------------------------------------- × 1.122
2 × π × CST × RST
3. SL (sidetone slope; the pole frequency of the high-pass)
The SL has 3 steps. SL(0) is a lower frequency of the high-pass. SL(3) is a higher frequency of the high-pass. SL can be used to influence the suppression at high
frequencies.
Figure 15-2. Audio Frequency Signal Management U4091BM-R
-10 dB
Offset
cancel
-3 dB to -10 dB and 7 dB (NWT)
ST
7 dB --> 0 dB and
20 dB (NWT)
Sidetone
balancing
VL
Line
32 dB --> -23dB
Offset
cancel
LRX
SAO1
Loudspeaker
6 dB
RXLS
1.5dB steps
1 dB steps
SAO2
26 dB --> -3 dB and
-10 dB (DTMF)
DTMF
generator
DTMF
DTMF
< -24 dBm/
-22 dBm >
Filter
MIC1
-->
Handset
microphone
0 dB
30 dB --> 12 dB
Offset
cancel
MIC2
Intercom
microphone
MIC3
0 dB
6 dB steps
Earpiece
DTMF
< -34 dBm/
-32 dBm >
EPO
Switching
matrix
7 dB --> -48 dB
RECO1
1 dB steps
RECO2
9 dB --> 2 dB
VL
MIC
8 dB
LTX
1 dB steps
1 dB steps
Line
MOD
AMREC
Answering
machine
28
0 dB
AMPB
AMREC
0 dB
0 dB
AGCO
AGCI
0 dB
AMPB
Answering
machine
AGC
U4091BM-R
4872A–CORD–08/05
U4091BM-R
16. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Symbol
Value
Unit
Line current
IL
140
mA
DC line voltage
VL
12
V
IRING
15
mA
Maximum input current
Junction temperature
Tj
125
°C
Ambient temperature
Tamb
–25 to +75
°C
Storage temperature
Tstg
–55 to +150
°C
Total power dissipation, Tamb = 60°C
Ptot
0.9
W
Symbol
Value
Unit
RthJA
70
K/W
17. Thermal Resistance
Parameters
Junction ambient SSO44
18. Electrical Characteristics
f = 1 kHz, 0 dBm = 775 mVrms, IVMIC = 0.3 mA, IMP = 3 mA, RDC = 1.3 MΩ, Tamb = 25°C, Zear = 68 nF + 100Ω,
RLS = 50Ω, ZM = 68 nF, resonator: f = 3.58 MHz, all bits in reset condition, unless otherwise specified.
Parameters
Test Conditions
Symbol
Min.
Typ.
Max.
Unit
DC Characteristics
DC voltage drop over circuit
IL = 2 mA
IL = 14 mA
IL = 60 mA
IL = 100 mA
8.6
1.6
4.8
7.2
9.2
GT
45.3
46.5
–1
VL
4.4
9.8
V
V
V
V
47.7
dB
0
dB
±0.5
dB
5.2
Transmission Amplifier, IL = 14 mA, VMIC = 2 mV, MICG[0:1] = 2, AGATX[0:2] = 7
ERX = ETX = ENMIC = ENSTBAL = I1O1 = I3O3 = 1, (GT = 48 dB)
Transmit amplification
MICG[0:1] = 2
AGATX[0:2] = 7
Frequency response
due to internal filters
IL ≥ 14 mA,
f = 1 kHz to 3.4 kHz
∆GT
Gain change with current
IL = 14 mA to 100 mA
∆GT
Gain deviation
Tamb = –10°C to +60°C
CMRR of microphone amplifier
∆GT
CMRR
Input resistance of MIC amplifier
Ri
dB
dt
2
%
3.0
4.2
dBm
6.0
6.6
dBm
MICHF = 1
Distortion at line
IL ≥ 14 mA, VL = 700 mVrms
VMIC = 20 mV, MICG[0:1] = 3
Note:
kΩ
±0.4
Gain difference
between MIC1/MIC2 to MIC3
DBM5 = 1
50
∆GT
Ri
IL ≥ 19 mA, d < 5%, VMIC = 10 mV
CTXA = 1 µF, DBM5 = 0
dB
kΩ
MICHF = 1
75
dB
80
300
Input resistance of MIC3 amplifier
Maximum output voltage
±0.5
60
VLmax
1.8
VLmax
4.8
VMICOmax
150
–4.2
dBm
1. This is a period of time the bus requires from the end of a data transmission and before a new transmission can be started
29
4872A–CORD–08/05
18. Electrical Characteristics (Continued)
f = 1 kHz, 0 dBm = 775 mVrms, IVMIC = 0.3 mA, IMP = 3 mA, RDC = 1.3 MΩ, Tamb = 25°C, Zear = 68 nF + 100Ω,
RLS = 50Ω, ZM = 68 nF, resonator: f = 3.58 MHz, all bits in reset condition, unless otherwise specified.
Parameters
Test Conditions
Noise at line psophometrically
weighted
IL ≥ 14 mA, MICG[0:1] = 2
AGATX[0:2] = 7
Anti-clipping
attack time
release time
Symbol
Min.
Typ.
Max.
Unit
No
–73
–70
dBmp
CTXA = 1 µF
each 3 dB overdrive
ta
tr
2
80
Gain at low operating current
IL = 8 mA, IMP = 1 mA
VMIC = 0.5 mV
IVMIC = 300 µA
GT
Distortion at low operating current
IL = 8 mA, IMP = 1 mA
VMIC = 5 mV
IVMIC = 300 µA
dt
45
ms
ms
48
dB
5
%
Receiving Amplifier
IL = 14 mA, VGEN = 300 mV,
ERX = ETX = ENMIC = ENSTBAL = I1O1 = I3O3 = 1, SL[0:1] = 0, LF[0:3] = 1, P[0:4] = 31, AFS[0:5] = 54, AGARX[0:2] = 0
Adjustment range of
receiving gain
Single ended,
IL ≥ 14 mA, Mute = 1,
EA[0:4] = 2 to 31
AGARX[0:2] = 0 to 7
Receiving amplification
Differential
AGARX[0:2] = 0
EA[0:4] = 15
EA[0:4] = 31
GR
–19
GR
–1
14.7
–1
0
15.7
+17
dB
1
16.7
dB
dB
0
dB
Frequency response
IL ≥ 14 mA, f = 1 kHz to 3.4 kHz
∆GRF
Gain change with current
IL = 14 mA to 100 mA
∆GR
±0.5
dB
Gain deviation
Tamb = –10°C to +60°C
∆GR
±0.5
dB
Ear protection differential
IL ≥ 14 mA,
VGEN = 11 Vrms
EA[0:4] = 15
EP
3
Vrms
MUTE suppression
(earpiece disconnect from matrix)
IL = 14 mA, I303 = 0
∆GR
Output voltage
d < 2% differential
IL = 14 mA
Zear = 68 nF + 100Ω
EA[0:4] = 11
Maximum output
current d < 2%
Zear = 100Ω
EA[0:4] = 31
Receiving noise
psophometrically weighted
IL = 14 mA
Zear = 68 nF + 100Ω
EA[0:4] = 15
Sidetone suppression
Z = 600Ω
Output resistance
Each output against GND
Ro
Gain at low operating
current (receive only)
IL = 6.5 mA, IMP = 1 mA
IM = 300 mA
VGEN = 200 mV
EA[0:4] = 21,
ENMIC = ETX = I101 = 0
GR
Note:
30
Iout
60
dB
0.775
Vrms
4
mAp
–79
–76
20
–2
dBmp
dB
0
10
Ω
2
dB
1. This is a period of time the bus requires from the end of a data transmission and before a new transmission can be started
U4091BM-R
4872A–CORD–08/05
U4091BM-R
18. Electrical Characteristics (Continued)
f = 1 kHz, 0 dBm = 775 mVrms, IVMIC = 0.3 mA, IMP = 3 mA, RDC = 1.3 MΩ, Tamb = 25°C, Zear = 68 nF + 100Ω,
RLS = 50Ω, ZM = 68 nF, resonator: f = 3.58 MHz, all bits in reset condition, unless otherwise specified.
Parameters
Test Conditions
Distortion at low
operating current
IL = 6.5 mA, IMP = 1 mA
IM = 300 µA, EA[0:4] = 15,
ENMIC = ETX = I101 = 0
Adjustment step: earpiece amplifier
DEA[0:4] = 1
for EA[0:4] = 2 to 31
0.8
Adjustment step: AGARX
DAGARX[0:2] = 1
0.8
Gain for DTMF signal
AMPB → RECO1/2
EA[0:4] = 1
AC impedance
IMPH = 0
IMPH = 1
Symbol
Min.
Typ.
Max.
Unit
5
%
1
1.2
dB
1
1.2
dB
dR
–10
Zimpl
Zimph
dB
595
980
625
1030
655
1080
Ω
Ω
DTMF, IL = 14 mA, ETX = I201 = 1, AGATX[0:2] = 7, DTMFM[0:2] = 4, DTMFF[0:4] = 0
DTMF level at line (mid gain)
Sum level, 600Ω,
DTMFM[0:2] = 4
–5.1
–3.6
–2.1
dBm
DTMF level at line (low gain)
Sum level, 600Ω,
DTMFM[0:2] = 5
–7.6
–6.1
–4.6
dBm
DTMF level at line (high gain)
Sum level, 600Ω,
DTMFM[0:2] = 6
AGATX[0:2] = 1
–5.2
–3.7
–2.2
dBm
Pre-emphasis
600 W, DTMFF4 = 0
DTMFF4 = 1
2
3
2.5
3.5
3
4
dBm
dBm
11
mA
Speaker Amplifier, Differential Mode
AMPB → SAO1/2
ENSACL = ENSA = ENSAO = ENAM = I4O2 = 1, SA[0:4] = 31,
ERX = ETX = ENMIC = ENSTBAL = I1O1 = I3O3 = 1
Minimum line current for operation
ENAM = I4O2 = 0
SE = 0, I3O2 = 1
IMP 1 mA, VGEN = 300 mV
ILmin
Gain from AMPB to SAO
VAMPB = 3 mV, IL = 15 mA,
SA[0:4] = 31
SA[0:4] = 0
GSA
Adjustment step speaker amplifier
DSA[0:4] = –1
Output power single ended
Load resistance:
RLS = 50Ω
VAMPB = 40 mV, SE = 1
IL = 15 mA
IL = 20 mA
Maximum output power differential
Load resistance:
RL = 50Ω
VAMPB = 60 mV, SE = 0
VB = 5V
Output noise
(input AMPB open)
psophometrically weighted
IL > 15 mA
Gain deviation
IL = 15 mA
Tamb = –10°C to +60°C
Note:
PSA
PSA
PSA
36
37
–5.5
38
dB
1.15
1.35
1.55
dB
3
7
20
mW
mW
150
mW
nSA
240
mVpsoph
∆GSA
±1
dB
1. This is a period of time the bus requires from the end of a data transmission and before a new transmission can be started
31
4872A–CORD–08/05
18. Electrical Characteristics (Continued)
f = 1 kHz, 0 dBm = 775 mVrms, IVMIC = 0.3 mA, IMP = 3 mA, RDC = 1.3 MΩ, Tamb = 25°C, Zear = 68 nF + 100Ω,
RLS = 50Ω, ZM = 68 nF, resonator: f = 3.58 MHz, all bits in reset condition, unless otherwise specified.
Parameters
Test Conditions
Symbol
Mute suppression
IL = 15 mA, VL = 0 dBm,
VAMPB = 4 mV
I4O2 = 0
Gain change with current
Max.
Unit
VSAO
–56
dBm
IL = 15 mA to 100 mA
∆GSA
1
dB
Gain change with frequency
IL = 15 mA
f = 1 kHz to 3.4 kHz
∆GSA
Attack time of anti-clipping
20 dB overdrive
Release time of anti-clipping
Min.
Typ.
–1
0
dB
tr
2
ms
tf
170
ms
Adjustment step of charge current
ENSAO = 0, SE = 1
DLSCUR[0:1] = 1
–480
–400
–320
µA
Adjustment step of
discharge current
ENSAO = 0, SE = 0
DLSCUR[0:1] = 1
320
400
480
µA
Charge current
Pin SAO2
ENSAO = 0, SE = 1
LSCUR[0:1] = 3
ICHA
–1.45
–1.2
–0.95
mA
Discharge current pin SAO2
ENSAO = 0, SE = 0
LSCUR[0:1] = 3
IDIS
0.95
1.2
1.45
mA
MICG[0:1] = 0
17.4
18.1
18.8
dB
MICG[0:1] = 1
23.2
23.7
24.6
dB
MICG[0:1] = 2
29.1
29.8
30.5
dB
Microphone Amplifier,
VB = 5V, VMIC = 2 mV, VMIC3 = 2 mV, ENMIC = ENAM = I1O4 = 1, MICHF = 0
Gain MIC amp.:
MIC1/2 →AMREC
MICG[0:1] = 3
35.0
35.7
36.4
dB
MIC3 to AMREC
MICHF = 1, MICG[0:1] = 3
35.0
35.7
36.5
dB
Input suppression:
MIC3 to MIC1/2
MICG[0:1] = 0, MICHF = 0
60
dB
MIC1/2 to MIC3
MICHF = 1
60
dB
Settling time offset cancellers
5 τ , FOFFC = 0
9
12
ms
Settling time offset cancellers in
speed-up mode
5 τ , FOFFC = 1
1.8
2.4
ms
AGC for Answering Machine, AMPB to AMREC,
ENAM = ENAGC = I4O5 = I5O4 = 1
VAMPB = 5 mV
23.5
25.5
27.5
dB
Maximum output level
VAMPB = 50 mV, d< 5%
240
300
360
mVp
Attack time
20 dB overdrive
Nominal gain
Release time
1
ms
45
ms
Switching Matrix,
VL = 0, VB = 5V, ENAM = I4O4 = 1, VAMPB = 0.6 Vrms
Input impedance AMPB
50
60
70
kΩ
Gain AMPB to AMREC
–0.7
–0.3
+0.1
dB
600
mV
VB –
600 mV
VPP
Maximum input level AMPB
I4O5 = I5O4 = 1, I4O4 = 0
Maximum output level AMREC
I4O4 = 1
Note:
32
1. This is a period of time the bus requires from the end of a data transmission and before a new transmission can be started
U4091BM-R
4872A–CORD–08/05
U4091BM-R
18. Electrical Characteristics (Continued)
f = 1 kHz, 0 dBm = 775 mVrms, IVMIC = 0.3 mA, IMP = 3 mA, RDC = 1.3 MΩ, Tamb = 25°C, Zear = 68 nF + 100Ω,
RLS = 50Ω, ZM = 68 nF, resonator: f = 3.58 MHz, all bits in reset condition, unless otherwise specified.
Parameters
Test Conditions
Symbol
Offset
I4O4: 1 to 0
∆VAMREC
Mute switching matrix
I4O4 = 0
Min.
Typ.
Max.
Unit
±30
mV
60
dB
Power-on Reset
VL = 0, VMP = 3.3V, VB = 5V, U4091 in Power-down Mode
Power-on reset by ES VB high,
VMP threshold
VB = 4V, ES = 4V,
raise VMP until RESET goes to low
Power-on reset by ES VMP high,
VB threshold
VMP = 3V, ES = 4V,
raise VB until RESET goes to low
VBon
Decrease VMP until INT
returns to high
VLVI
2.5
2.6
2.7
V
Low-voltage reset
Decrease VMP until RESET returns to
low
VLVR
2.35
2.45
2.55
V
Difference voltage between lowvoltage interrupt and reset
VLVI – VLVR
100
150
0.6
0.9
VMPon
2.65
2.75
2.85
3.2
V
V
Low-voltage Interrupt
VL = 0, VMP = 3.3V, VB = 0V
VMP decreasing
Power-off Reset
VL = 0, VMP = 3.3V, VB = 0V
mV
Logical Part
VMP = 3.3V, VB = 5V
Output impedance at OSCOUT
Pins SCL,
SDA (input mode)
Input leakage current
Low level
High level
0 < Vi < VMP
Pins INT,
SDA (output mode)
Output low
(resistance to GND)
0.2 ×
VMP
0.8 ×
VMP
–1
150
1.2
+1
230
kΩ
V
V
µA
350
Ω
5
µA
Switch for Additional Impedance (Pin IMPSW)
VMP = 3.3V, VB = 3V
Switch-off leakage current
0 < Vi < VMP
IMPSW = 0
Resistance to GND
IMPSW = 1
Maximum current
IMPSW = 1
–0.5
50
–5
80
Ω
5
mA
50
dB
AFS (Acoustic Feedback Suppression), IL = 14 mA, VGEN = 300 mV,
ERX = ETX = ENMIC = ENSTBAL = I1O1 = I3O3 = 1, SL[0:1] = 0, LF[0:3] = 1, P[0:4] = 31, AGARX[0:2] = 0
Adjustment range of attenuation
IL ≥ 15 mA
Attenuation of transmit gain
IL ≥ 15 mA, IINLDT = 0 µA
IINLDR = 10 µA
∆GT
47
50
53
dB
Attenuation of speaker amplifier
IL ≥ 15 mA, IINLDT = 10 µA
IINLDR = 0 µA
GSA
47
50
53
dB
Note:
0
1. This is a period of time the bus requires from the end of a data transmission and before a new transmission can be started
33
4872A–CORD–08/05
18. Electrical Characteristics (Continued)
f = 1 kHz, 0 dBm = 775 mVrms, IVMIC = 0.3 mA, IMP = 3 mA, RDC = 1.3 MΩ, Tamb = 25°C, Zear = 68 nF + 100Ω,
RLS = 50Ω, ZM = 68 nF, resonator: f = 3.58 MHz, all bits in reset condition, unless otherwise specified.
Parameters
Test Conditions
Symbol
Min.
Typ.
Max.
Unit
3.1
3.3
3.5
V
5.5
V
4
V
6.3
V
Supply Voltages, VMIC = 25 mV, Tamb = –10°C to + 60°C
VMP
IL = 14 mA, RDC = 680 kΩ
IMP = 3 mA
VMP
VMPS
IL = 100 mA, RDC = inf.,
IMP = 0 mA
VMPS
VMIC
IL = 14 mA, RDC = 1.3 MΩ
IM = 700 A
VMIC
VB
IB = +20 mA, IL = 0 mA
1.5
VB
5.5
PSA
15
Ringing Power Converter, IMP = 1 mA, IM = 0, RIMPA = 500 kΩ
Maximum output power
VRING = 20.6V
ENSA = ENSAO = SE = 1
VRING: high to low
Threshold
mW
7.4
V
Low to high, RINGTH [0:3] = 0
6.0
6.7
7.4
V
Low to high, RINGTH [0:3] = 15
19
21
23
V
Adjustment steps threshold
DRINGTH = 1
0.8
1
1.2
V
Input impedance
VRING = 30V
4.6
5.8
7.0
kΩ
Maximum input voltage
VRINGmax
30
ViBUS
3.0
0
V
Serial Bus SCL, SDA, AS, VMP = 3.3V, RSDA = RSCL = RINT = 12 kΩ
Input voltage
HIGH
LOW
SDA, SCL, INT
Output voltage
Acknowledge LOW
SDA
ISDA = 3 mA
Clock frequency
SCL
VDD
1.5
V
V
VO
0.4
V
fSCL
100
kHz
Rise time SDA, SCL
tr
1
µs
Fall time SDA, SCL
tf
300
ns
Period of SCL
HIGH
LOW
HIGH
LOW
tH
tL
4.0
4.7
µs
µs
tsSTA
tsDAT
tsSTOP
twSTA
4.7
250
4.7
4.7
µs
ns
µs
µs
thSTA
thDAT
4.0
0
µs
µs
Setup Time
Start condition
Data
Stop condition
Time space(1)
Hold Time
Start condition
DATA
Note:
34
1. This is a period of time the bus requires from the end of a data transmission and before a new transmission can be started
U4091BM-R
4872A–CORD–08/05
4872A–CORD–08/05
sin
+
sin
+
V
V
RCD
CIND
10Ω
9
8
7
6
5
4
3
2
1
V
36
37
38
39
40
41
42
43
V
44
V
+
sin
10
35
33
11
12
U4091BM
34
V
50Ω
13
32
V
14
31
15
30
16
29
17
28
V
18
27
V
19
26
3.58
MHz
20
25
+
PWL
21
24
+
PWL
22
23
A
U4091BM-R
19. Test Circuits
Figure 19-1. Basic Test Circuit
35
36
42
3
43
2
44
1
4
41
5
40
6
39
7
38
8
37
9
36
VB
10
35
33
11
12
U4091BM
34
V
50Ω
13
32
V
14
31
15
30
16
29
17
28
18
27
19
26
3.58
MHz
BC
556
21
24
+
68 nF
20
25
+
PWL PWL
2.2 mH
VB
SD103A
22
23
Figure 19-2. Test Circuit for Ringing
U4091BM-R
4872A–CORD–08/05
U4091BM-R
20. Bus Timing
Figure 20-1. Bus Timing Diagram
SDA
twSTA
tf
tr
thSTA
SCL
P
S
thSTA
t hDAT
tL
tH
tsSTA
tsSTOP
thDAT
P
P = Stop, S = Start
21. Ordering Information
Extended Type Number
Package
Remarks
U4091BM-RFNGY
SSO44
Tube
U4091BM-RFNG3Y
SSO44
Taped and reeled
T4091R-DDB
Die
Die on foil
22. Package Information
9.15
8.65
Package SSO44
Dimensions in mm
18.05
17.80
7.50
7.30
2.35
0.3
0.25
0.10
0.8
16.8
44
0.25
10.50
10.20
23
technical drawings
according to DIN
specifications
1
22
37
4872A–CORD–08/05
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4872A–CORD–08/05