FAN6210 Primary-Side Synchronous Rectifier (SR) Trigger Controller for Dual Forward Converter Features Description Primary-Side Trigger Controller for Dual Forward Converters with Synchronous Rectifier (SR) FAN6210 is a primary-side trigger Integrated Circuit (IC) specially designed for the synchronous rectifier (SR) in dual forward converters employing FSR660/630. Specialized SR Controller for Dual Forward Converter Programmable Turn-on Delay Time for the Powering SR (RDLY Pin) Winding Voltage Detection for Precision Control at Light-Load Condition (DET Pin) Green-Mode Operation to Improve Light-Load Efficiency FAN6210 provides drive signal for the primary-side power switches by using an output signal from PWM controller. FAN6210 can be combined with any PWM controller that can drive a dual-forward converter. To obtain optimal timing for the SR drive signals, transformer winding voltage is also monitored. To improve light-load efficiency, green mode operation is employed, which disables the SR turn-on trigger signal, minimizing gate drive power consumption at light load. FAN6210 is available in 8-pin SOP package. Differential Mode Control Signal with Better Noise Immunity VDD Over-Voltage Protection (OVP) Applications Personal Computer (PC) Power Supply Entry-Level Server Power Supply Ordering Information Part Number Operating Temperature Range FAN6210MY -40°C to +105°C Eco Status Green Package Packing Method 8-Pin Small Outline Package (SOP) Tape & Reel For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. © 2009 Fairchild Semiconductor Corporation FAN6210 Rev. 1.0.1 www.fairchildsemi.com FAN6210 — Primary-Side Synchronous Rectifier (SR) Trigger Controller for Dual Forward Converter September 2009 Figure 1. Typical Application Internal Block Diagram Rising/Falling Delay SIN 3 300ns Green Mode (D<10%) 7 SOUT 100ns Controlled Rising Delay 8 GND GM GM RDLY 4 One-shot Vibrator 700ns Rising Delay 1 XP 2/3V + 50ns - DET 5 OVP One-shot Vibrator + 25.5V Rising/Falling Delay 300ns 50ns VDD 6 One-shot Vibrator 50ns FAN6210 — Primary-Side Synchronous Rectifier (SR) Trigger Controller for Dual Forward Converter Application Diagram 2 XN + 10/8V 300ns Internal Bias Figure 2. Functional Block Diagram © 2009 Fairchild Semiconductor Corporation FAN6210 Rev. 1.0.1 www.fairchildsemi.com 2 F: Fairchild Logo Z: Plant Code X: Year Code Y: Week Code TT: Package Type T: M=SOP P: Y: Green Package M: Manufacture Flow Code Figure 3. Top Mark Pin Configuration Figure 4. Pin Configuration Pin Definitions Pin # Name Description 1 XN Pulse signal output terminal for SR off control signal. 2 XP Pulse signal output terminal for SR on control signal. 3 SIN Input signal for high- and low-side gate driver outputs. 4 RDLY 5 DET Sensing freewheel diode voltage. 6 VDD The power supply pin. 7 SOUT Gate driving to high- and low-side gate driver. 8 GND Ground. Delay time setting. This delay time is SOUT rising to trigger XP pulse delay time. © 2009 Fairchild Semiconductor Corporation FAN6210 Rev. 1.0.1 FAN6210 — Primary-Side Synchronous Rectifier (SR) Trigger Controller for Dual Forward Converter Marking Information www.fairchildsemi.com 3 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit VDD DC Supply Voltage 30 V VSIN Logic Input Voltage 30 V Low Side Output Voltage 18 V VH XP, XN 30 V VL DET, RDLY 7 V VSOUT PD θJA TJ TSTG TL ESD Power Dissipation TA < 50°C 400 mW Thermal Dissipation (Junction to Air) 150 °C/W Operating Junction Temperature -40 +125 °C Storage Temperature Range -55 +150 °C Lead Temperature (Soldering) 10 seconds 260 °C Human Body Model, JEDEC:JESD22-A114 4.0 KV Charged Device Model, JEDEC:JESD22-C101 1.5 KV Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. 2. All voltage values, except differential voltages, are given with respect to GND pin. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol TA Parameter Operating Ambient Temperature © 2009 Fairchild Semiconductor Corporation FAN6210 Rev. 1.0.1 Min. Max. Unit -40 +105 °C FAN6210 — Primary-Side Synchronous Rectifier (SR) Trigger Controller for Dual Forward Converter Absolute Maximum Ratings www.fairchildsemi.com 4 VDD=20V, TA=25℃, unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Units VDD Section DC Supply Voltage 7 24 V VDD-ON VDD Turn-On Threshold Voltage 9 10 11 V VTH-OFF Turn-Off Threshold Voltage 7 8 9 V VDD-OVP VDD Over-Voltage Protection (OVP) 23.0 25.5 28.0 V Hysteresis voltage for VDD OVP 0.3 0.8 1.3 VDD-OVP-HYS tOVP VDD OVP Debounce Time 250 V μs SIN Section VSIN Logic Input Voltage 10.5 24.5 V tDLY_OUTH Delay Time Between SIN-HIGH and SOUT-HIGH 240 tDLY_OUTL Delay Time Between SIN-LOW and SOUT-LOW 75 300 350 ns 100 150 ns SOUT Maximum On Time and Stop XP Pulse 8.5 10.0 12.0 μs VDET_H Detect Input Voltage to Send XP After SOUT Falling 2.5 3.0 3.5 V VDET_L Voltage to Drive XP Signal After SOUT Falling 1.5 2.0 2.5 V tPD_DET Delay Time to Send XP 30 50 100 ns tON_MAX DET Section XP XN Section tPLS_XN High-Level Pulsewidth of XN Signal 250 300 350 ns tPLS_XP High-Level Pulsewidth of XP Signal 600 700 800 ns Delay Time to Trigger XN by SIN Rising or Falling Edge 25 50 75 ns tPD_XN DPLS_OFF SIN Duty Ratio Shorter than DPLS_OFF Stop XP Pulse 10 % VXN XN Signal Output Voltage Level 5.5 8.0 V VXP XP Signal Output Voltage Level 5.5 8.0 V tR_XP XP Rising Time VDD = 15V; CL = 100pF; SOUT= 1V to 6V 30 ns tF_XP XP Falling Time VDD = 15V; CL = 100pF; SOUT= 7V to 2V 30 ns RDLY Section VRDLY RDLY Voltage RRDLY=24kΩ 1.08 1.20 1.32 V tDLY_XP Delay Time to Trigger XP by SOUT Rising Edge RRDLY=24kΩ 280 340 400 ns VZ Output Voltage Maximum (Clamp) VDD=25V 18.5 V VOL Output Voltage LOW VDD=15V; IO = 50mA 1.5 V VOH Output Voltage HIGH VDD=15V; IO = 50mA 10 tR SOUT Rising Time VDD = 15V; CL = 5nF; SOUT= 2V to 9V 30 70 120 ns tF SOUT Falling Time VDD = 15V; CL = 5nF; SOUT= 9V to 2V 30 50 100 ns © 2009 Fairchild Semiconductor Corporation FAN6210 Rev. 1.0.1 V FAN6210 — Primary-Side Synchronous Rectifier (SR) Trigger Controller for Dual Forward Converter Electrical Characteristics www.fairchildsemi.com 5 11.0 9.00 10.5 8.75 VTH -OFF (V) V DD-ON (V) These characteristic graphs are normalized at TA = 25°C. 10.0 8.50 8.25 9.5 8.00 9.0 -40 -25 -10 5 20 35 50 65 80 95 110 -40 125 -25 -10 5 20 35 50 65 80 95 110 125 Temperature℃ Figure 5. Turn-On Threshold Voltage Figure 6. Turn-Off Threshold Voltage 350 150 140 330 tDLY_OUTL (ns) tDLY_OUTH (ns) Temperature℃ 310 290 130 120 110 270 100 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature℃ Figure 7. Delay Time Between SIN-HIGH and SOUT-HIGH Figure 8. Delay Time Between SIN-LOW and SOUT-LOW 340 740 320 720 tP LS _XP (ns) tP LS _XN (ns) Temperature℃ 300 280 700 680 260 660 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 Temperature℃ 20 35 50 65 80 95 110 125 Temperature℃ Figure 9. High-Level Pulsewidth of XN Signal Figure 10. High-Level Pulsewidth of XP Signal 70 400 380 360 tP LS _XP (ns) tP D_XN (ns) 60 50 40 340 FAN6210 — Primary-Side Synchronous Rectifier (SR) Trigger Controller for Dual Forward Converter Typical Performance Characteristics 320 300 280 260 30 240 -40 -25 -10 5 20 35 50 65 80 95 110 125 -40 Temperature℃ -10 5 20 35 50 65 80 95 110 125 Temperature℃ Figure 11. Delay Time to Trigger XN by SIN Rising or Falling Edge © 2009 Fairchild Semiconductor Corporation FAN6210 Rev. 1.0.1 -25 Figure 12. Delay Time to Trigger XP by SOUT Rising Edge www.fairchildsemi.com 6 Figure 15 shows the typical application circuit of FAN6210. SIN is the gate drive output of the PWM controller. SOUT is obtained from SIN by adding a delay, which is used to drive two switches Q1 and Q2. Figure 13 and Figure 14 show the simplified circuit diagram of dual-forward converter and its key waveforms. Switches Q1 and Q2 are turned on and off together. Once Q1 and Q2 are turned on, input voltage is applied across the transformer primary side and power is delivered to the secondary side through the transformer, powering diode D1. During this time, the magnetizing current linearly increases. When Q1 and Q2 are turned off, the magnetizing current of the transformer forces the reset diodes (DR1 and DR2) and negative input voltage is applied across the transformer primary side. During this time, magnetizing current linearly decreases to zero and the secondary-side inductor current freewheels through diode D2. When synchronous rectifiers SR1 and SR2 are used instead of diodes D1 and D2, it is important to have proper timing between drive signals for SR1 and SR2. The value of the DET resistor is recommended as 10kΩ and DB is used to block high voltage on winding. The breakdown voltage of Zener diode DZ is typically 5~6V to protect the DET pin from over voltage. VIN + Q1 From PWM controller FAN6210 1 2 3 DR2 Q1 4 L Lm + Vx - + VIN VD DR1 SR2 Im - GND XN SOUT SIN VDD RDLY DET 8 DB 7 6 5 Q2 Dz Drv IL - SR1 SN of FSR660/630 Q2 SP of FSR660/630 Figure 13. Simplified Circuit Diagram of Dual-Forward Converter Figure 15. Typical Application Circuit Figure 16 shows the timing diagrams for heavy-load and light-load conditions. Vgs Q1,Q2 The switching operation of the secondary SR MOSFETs is determined by the SN and SP signals. FSR660/630 turns on SR MOSFETs at the rising edge of the XP signal, while it turns off SR MOSFETs at the rising edge of XN. Within one switching cycle, XP and XN are obtained two times, respectively. Vx Vin The XN signal has a 300ns pulse-width and is triggered by the rising edge and falling edge of the SIN signal after a short time delay (tPD_XN). VD Vin XP signal has a 700ns pulse-width and is triggered by the rising edge of the SOUT signal after an adjustable time delay (tDLY_XP) and by the falling edge of the DET signal. The relation between the delay resistor (RDELAY) and the delay time is shown in Figure 17. The triggering of the XP signal by DET is prohibited while the XN signal is HIGH. Therefore, the XP signal is not triggered at the falling edge of the DET signal and is delayed until the XN signal drops to zero at heavy-load condition. At light-load condition, the DET falling edge comes after the XN signal drops to zero and the XP signal is triggered at the falling edge of the DET signal after a short time delay (tPD_DET). IM IL XP Vo D2 D1 Drv ID1 ID2 Figure 14. Key Waveforms of Dual-Forward Converter © 2009 Fairchild Semiconductor Corporation FAN6210 Rev. 1.0.1 FAN6210 — Primary-Side Synchronous Rectifier (SR) Trigger Controller for Dual Forward Converter Function Description www.fairchildsemi.com 7 SOUT 300ns Programmable delay XP 300ns 100ns 50ns 700ns Programmable delay 700ns 50ns XN 50ns 50ns 300ns 300ns 300ns Gate drive for Powering SR Gate drive for Free-wheeling SR DET Light load condition SIN SOUT 300ns 50ns Programmable delay XP 300ns 100ns 700ns 700ns Programmable delay 50ns XN 50ns 50ns 300ns 300ns 300ns Gate drive for Powering SR Gate drive for Free-wheeling SR DET Figure 16. Timing Diagram t DLY_XP (ns) Under-Voltage Lockout (UVLO) 350 300 The power-on and -off threshold of FAN6210 are fixed at 10V and 8V, respectively. The VDD pin can be connected with the power source of the PWM controller. 250 VDD Pin Over-Voltage Protection VDD over-voltage protection prevents damage due to abnormal conditions. Once the VDD voltage exceeds the VDD over-voltage protection voltage (VDD-OVP) and lasts for tOVP, FAN6210 stops operation. 200 150 100 FAN6210 — Primary-Side Synchronous Rectifier (SR) Trigger Controller for Dual Forward Converter Heavy load condition SIN Green-Mode Operation 5 7.5 10 12.5 15 17.5 20 22.5 25 To improve light-load efficiency, green-mode operation is employed, which disables the SR turn-on trigger signal, minimizing gate drive power consumption at light-load condition. Green mode is enabled when the duty cycle of SIN is smaller than 10%. RRDLY (kΩ) Figure 17. Programmable Delay with Resistor © 2009 Fairchild Semiconductor Corporation FAN6210 Rev. 1.0.1 www.fairchildsemi.com 8 Application Fairchild Devices Input Voltage Range Output FAN480X FAN6210 PC Power 12V/16.5A 90~264VAC FSR660 5V/18A FSR630 VIN VAC PFC stage FCP20N60 UF1007 4.7 (primary 300µH) 1:1.2 1N4148 74:7 100µF 10k 56µH VO=12V 1.8µH 10k 1 110k 6 3 DET LPC VDD GND SN 5 2200µF 4.7 10k 10k 1N4148 1:1.2 DET FR107 FCP20N60 IPWM (To FAN480X) 470 GND 1 FSR660 2 UF1007 5 SN LPC 6 10k 4 SP VDD 3 2 10k FSR660 470pF 11µH 0.15 OPWM (From FAN480X) 1N4148 1 XP GND 8 2 XN SOUT 7 3 SIN 8.2k VDD 6 10k ZD/5.6V 1N4148 6 VO=5V 2µH 3 DET LPC VDD GND SN 5 330µF 5.1k 4 RDLY DET 5 FAN6210 1 20k 74:3 10 10 2200µF SP 4 1N4148 From VDD of FAN480X 1N4148 1N4148 1:1 (160µH) DET GND 2 5 SN LPC 6 4 SP VDD 3 1 2 220µF SP 4 FSR630 10k 12V 5V 30k 15k FSR630 3k PC817 1k 1µF FAN6210 — Primary-Side Synchronous Rectifier (SR) Trigger for Dual Forward Converter Typical Application Circuit (Dual-Forward Converter with SR) TL431 5.1k Figure 18. Application Circuit © 2009 Fairchild Semiconductor Corporation FAN6210 Rev. 1.0.1 9 www.fairchildsemi.com 5.00 4.80 A 0.65 3.81 5 8 B 6.20 5.80 PIN ONE INDICATOR 1.75 4.00 3.80 1 5.60 4 1.27 (0.33) 0.25 M 1.27 C B A LAND PATTERN RECOMMENDATION 0.25 0.10 SEE DETAIL A 1.75 MAX 0.25 0.19 C 0.10 0.51 0.33 0.50 x 45° 0.25 R0.10 C OPTION A - BEVEL EDGE GAGE PLANE R0.10 OPTION B - NO BEVEL EDGE 0.36 NOTES: UNLESS OTHERWISE SPECIFIED 8° 0° 0.90 0.406 A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AA, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M. E) DRAWING FILENAME: M08AREV13 SEATING PLANE (1.04) DETAIL A SCALE: 2:1 FAN6210 — Primary-Side Synchronous Rectifier (SR) Trigger for Dual Forward Converter Physical Dimensions Figure 19. 8-Pin Small Out-Line Package (SOP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2009 Fairchild Semiconductor Corporation FAN6210 Rev. 1.0.1 10 www.fairchildsemi.com FAN6210 — Primary-Side Synchronous Rectifier (SR) Trigger for Dual Forward Converter www.fairchildsemi.com 11 © 2009 Fairchild Semiconductor Corporation FAN6210 Rev. 1.0.1