FAIRCHILD FSEZ2016

FSEZ2016 — Low-Power Green-Mode EZSWITCH without
Secondary Side Feedback Circuitry
Features
Description
ƒ Linearly Decreasing PWM Frequency
ƒ Green Mode Under Light-load and Zero-Load
This highly integrated PWM controller provides several
features to enhance the performance of low-power
flyback converters. To minimize standby power
consumption, a proprietary green-mode function provides
off-time modulation to linearly decrease the switching
frequency under light-load and zero-load conditions. This
green mode enables the power supply to meet
international power conservation requirements. The
supply voltage VDD is also used for feedback
compensation, to regulate the output voltage without
requiring a conventional TL431 and a photo-coupler. A
typical output CV/CC characteristic is shown in Figure 1.
Conditions
ƒ Constant Voltage (CV) and Constant Current (CC)
around ±25% without Secondary Side Feedback
Circuitry
ƒ Precise Constant Voltage (CV) at ±5% by Secondary
Side Feedback Circuitry
ƒ Low Startup Current: 8μA
ƒ Low Operating Current: 3.6mA
ƒ Leading-Edge Blanking (LEB)
ƒ Constant Power Limit
ƒ Universal AC Input Range
ƒ Synchronized Slope Compensation
ƒ 140°C OTP Sensor with Hysteresis
ƒ VDD Over-Voltage Clamping
ƒ Cycle-by-Cycle Current Limiting
ƒ Under-Voltage Lockout (UVLO)
ƒ Fixed PWM Frequency with Hopping
ƒ Gate Output Maximum Voltage Clamped at 17V
Applications
General-purpose switching-mode power supplies and
flyback power converters, such as:
ƒ Battery Chargers for Cellular Phones, Cordless
Phones, PDAs, Digital Cameras, Power Tools
Another advantage of the FSEZ2016 is that the typical
startup current is only 8μA, while the typical operating
current can be as low as 3.6mA. A large startup
resistance can be used to achieve even higher power
conversion efficiency.
FSEZ2016 integrates frequency hopping function
internally to reduce EMI emissions with minimum line
filters. Also, built-in synchronized slope compensation
maintains the stability of peak current-mode control.
Proprietary internal compensation ensures constant
output power limiting over a universal range of AC input
voltages, from 90VAC to 264VAC.
The FSEZ2016 provides many protection functions.
Pulse-by-pulse current limiting ensures constant output
current, even if a short circuit occurs. The internal
protection circuit disables PWM output if VDD exceeds
22.7V. The gate output is clamped at 17V to protect the
power MOS from over-voltage damage. The built-in
over-temperature protection (OTP) function shuts down
the controller at 140°C with a 30°C hysteresis.
ƒ Power Adapters for Ink Jet Printers, Video Game
Consoles, Portable Audio Players
ƒ Open-Frame SMPS for TV/DVD Standby and
Auxiliary Supplies, Home Appliances, Consumer
Electronics
ƒ Replacement for Linear Transformers and RCC SMPS
ƒ PC 5V Standby Power
Maximum
With Secondary Feedback
Vo
8
Minimum
Without Secondary Feedback
7
6
5
4
3
2
1
Io
0
0
0.2
0.4
Figure 1.
© 2008 Fairchild Semiconductor Corporation
FSEZ2016 • Rev. 1.0.1
0.6
0.8
1
1.2
1.4
1.6
1.8
2
Typical Output V-I Characteristic
www.fairchildsemi.com
FSEZ2016 — Low-Power Green-Mode EZSWITCH without Secondary Side Feedback Circuitry
January 2010
Part Number
FSEZ2016NY
Operating
Temperature Range
Package
Packing Method
7-Lead, Dual Outline
Package (DIP-7)
Tube
Eco Status
Green
-40°C to +105°C
For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
Application Diagram
Figure 2.
Typical Application
Internal Block Diagram
Figure 3.
© 2008 Fairchild Semiconductor Corporation
FSEZ2016 • Rev. 1.0.1
FSEZ2016 — Low-Power Green-Mode EZSWITCH without Secondary Side Feedback Circuitry
Ordering Information
Functional Block Diagram
www.fairchildsemi.com
2
FSEZ2016 — Low-Power Green-Mode EZSWITCH without Secondary Side Feedback Circuitry
Marking Information
1’st line
Z: Assembly plant code
X: Year code
Y: Week code
TT: Die run code
3’rd line
T: Package type (N=DIP)
P: Y=Green package
M: Manufacture flow code
Figure 4.
Top Mark
Pin Configuration
Figure 5.
Pin Assignments
Pin Definitions
Pin #
Name
1
SOURCE
2
GND
3
VDD
Description
Power MOSFET source. This is the high-voltage power MOSFET source.
Ground
Power supply
4
FB
The FB pin provides feedback information to the internal PWM comparator. This
feedback is used to control the duty cycle. When no feedback is provided, this pin is
left open.
5
NC
No connection
6
NC
8
DRAIN
© 2008 Fairchild Semiconductor Corporation
FSEZ2016 • Rev. 1.0.1
No connection
Power MOSFET drain. This is the high-voltage power MOSFET drain.
www.fairchildsemi.com
3
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Symbol
VDD
VFB
VSENSE
PD
θJA
TJ
TSTG
TL
ESD
Parameter
DC Supply Voltage
Min.
(1, 2)
Max.
Unit
30
V
Input Voltage to FB Pin
-0.3
7.0
V
Input Voltage to Sense Pin
-0.3
7.0
V
Power Dissipation (TA=25°C)
1.2
W
Thermal Resistance (Junction to Air)
98.7
°C/W
Operating Junction Temperature
-40
150
°C
Storage Temperature Range
-55
150
°C
260
°C
Human Body Model (JEDEC:JESD22_A114)
2
KV
Charged Device Model (JEDEC:JESD22_C101)
1
KV
Lead Temperature (Wave Soldering or IR, 10 Seconds)
Electrostatic
Discharge Capability
Notes:
1. All voltage values, except differential voltages, are given with respect to GND pin.
2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
© 2008 Fairchild Semiconductor Corporation
FSEZ2016 • Rev. 1.0.1
FSEZ2016 — Low-Power Green-Mode EZSWITCH without Secondary Side Feedback Circuitry
Absolute Maximum Ratings
www.fairchildsemi.com
4
Unless otherwise noted, VDD=15V and TA=25°C.
Symbol
Parameter
Conditions
Min.
Typ.
Max. Units
VDD Section
VDD-OP
Continuously Operation Voltage
VDD-ON
Turn-on Threshold Voltage
VDD-OFF
Turn-off Threshold Voltage
With Secondary Feedback
20.0
Without Secondary Feedback
22.7
IDD-ST
Startup Current
VDD=VDD-ON – 0.1V
IDD-OP
Operating Supply Current
CL=1nF
VDD-G-OFF
V
16
17
18
7.5
8.0
8.5
V
8
20
μA
3.6
4.6
mA
VDD Low-threshold Voltage to Exit
Green-off Mode
V
VDD-OFF
+1.3
V
0.35
V/V
4.6
kΩ
Feedback Input Section
AV
Input-Voltage to Current-Sense
Attenuation
ZFB
Input Impedance
VFB-OPEN
VDD-FB
IFB=0.1mA to 0.2mA
Open-Loop Voltage
4.5
VDD Feedback Threshold Voltage
V
FB is Open
20.7
22.7
24.7
V
IFB=0.4mA
18.4
20.4
22.4
V
100
150
ns
Current-Sense Section
tPD
VSTHVA
VSTHFL
tLEB
Propagation Delay
Current Limit Valley Threshold Voltage
Current Limit Flat Threshold Voltage
VDD=18V
0.83
V
VDD=15V
0.74
V
VDD=10V
0.59
V
VDD=18V
1.15
V
VDD=15V
1.04
V
VDD=10V
0.84
V
Leading-Edge Blanking Time
220
Figure 6.
© 2008 Fairchild Semiconductor Corporation
FSEZ2016 • Rev. 1.0.1
310
400
ns
FSEZ2016 — Low-Power Green-Mode EZSWITCH without Secondary Side Feedback Circuitry
Electrical Characteristics
Saw Limit
www.fairchildsemi.com
5
Unless otherwise noted, VDD=15V and TA=25°C.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Oscillator Section
fOSC
Frequency
tHOP
Hopping Period
Center Frequency
Hopping Range
60
65
70
±4.1
±4.7
±5.3
4
fOSC-G
Green Mode Frequency
14.5
VFB-N
Green Mode Entry FB Voltage
2.3
VFB-G
VFB-Z
ms
17.0
19.5
KHz
2.6
2.9
V
VFB-N 0.75
Green Mode Ending FB Voltage
Zero Duty Cycle FB Voltage
V
1.4
SG
Green Mode Modulation Slope
40
fDV
Frequency Variation vs. VDD Deviation
VDD=10 to 22V
fDT
Frequency Variation vs. Temperature
Deviation
TA= -20 to 85°C
kHz
70
V
100
Hz/mV
5
%
1.5
5.0
%
74
79
%
Internal MOSFET Section
DCYMAX
Maximum Duty Cycle
69
BVDSS
Drain-Source Breakdown Voltage
ID=250μA, VGS=0V
ΔBVDSS/ΔTJ
Breakdown Voltage Temperature
Coefficient
ID=250μA,
Referenced to 25°C
600
V
0.6
V/°C
IS
Maximum Continuous Drain-Source
Diode Forward Current
1
A
ISM
Maximum Pulsed Drain-Source Diode
Forward Current
4
A
11.5
Ω
VDS=600V, VGS=0V,
TC=25°C
5
μA
VDS=480V, VGS=0V,
TC=100°C
10
μA
7
24
ns
Rise Time
21
52
ns
Turn-off Delay Time
13
36
ns
27
64
ns
130
170
pF
19
25
pF
RDS(ON)
IDSS
tD-ON
tr
tD-OFF
tf
Static Drain-Source On-Resistance
Drain-Source Leakage Current
Turn-on Delay Time
ID=0.5A, VGS=10V
VDS=300V, ID=1.1A,
RG=25Ω
Fall Time
CISS
Input Capacitance
COSS
Output Capacitance
VGS=0V, VDS=25V,
fS=1MHz
9.3
FSEZ2016 — Low-Power Green-Mode EZSWITCH without Secondary Side Feedback Circuitry
Electrical Characteristics (Continued)
Over Temperature Protection (OTP)
TOTP
Protection Junction Temperature
TOTP-RESTART Restart Junction Temperature
© 2008 Fairchild Semiconductor Corporation
FSEZ2016 • Rev. 1.0.1
140
°C
110
°C
www.fairchildsemi.com
6
8.4
16.8
8.2
V DD-OFF (V)
V DD-ON (V)
17
16.6
16.4
16.2
8
7.8
7.6
16
7.4
-40
-25
-10
5
20
35
50
65
80
95
110
125
-40
-25
-10
5
T emperature (℃ )
Turn-on Threshold Voltage (VDD-ON)
vs. Temperature
Figure 8.
14
3
12
2.8
IDD-OP (mA)
IDD-ST (μA)
Figure 7.
10
8
6
35
50
65
80
95
110
125
Turn-off Threshold Voltage (VDD-OFF)
vs. Temperature
2.6
2.4
2.2
4
2
-40
-25
-10
5
20
35
50
65
80
95
110
125
-40
-25
-10
5
T emperature (℃ )
Figure 9.
20
35
50
65
80
95
110
125
T emperature (℃ )
Startup Current (IDD-ST)
vs. Temperature
Figure 10. Operating Supply Current (IDD-OP)
vs. Temperature
66
77
65
76
64
75
DCY MAX (%)
fOSC (KHz)
20
T emperature (℃ )
63
62
61
74
73
72
60
FSEZ2016 — Low-Power Green-Mode EZSWITCH without Secondary Side Feedback Circuitry
Typical Performance Characteristics
71
-40
-25
-10
5
20
35
50
65
80
95
110
125
-40
T emperature (℃ )
-10
5
20
35
50
65
80
95
110
125
T emperature (℃ )
Figure 11. Center Frequency (fOSC)
vs. Temperature
© 2008 Fairchild Semiconductor Corporation
FSEZ2016 • Rev. 1.0.1
-25
Figure 12. Maximum Duty Cycle (DCYMAX)
vs. Temperature
www.fairchildsemi.com
7
2.2
2.8
2
V FB-G (V)
V FB-N (V)
3
2.6
2.4
2.2
1.8
1.6
1.4
2
1.2
-40
-25
-10
5
20
35
50
65
80
95
110
125
-40
-25
-10
5
T emperature (℃ )
Figure 13. Green-Mode Entry FB Voltage
(VFB-N) vs. Temperature
35
50
65
80
95
110
125
Figure 14. Green-Mode Ending FB Voltage
(VFB-G) vs. Temperature
380
800
750
BV DSS (V)
360
tLEB (ns)
20
T emperature (℃ )
340
320
300
700
650
600
550
280
500
-40
-25
-10
5
20
35
50
65
80
95
110
125
-40
T emperature (℃ )
-10
5
20
35
50
65
80
95
110
125
T emperature (℃ )
Figure 15. Leading-Edge Blanking Time (tLEB)
vs. Temperature
© 2008 Fairchild Semiconductor Corporation
FSEZ2016 • Rev. 1.0.1
-25
Figure 16. Drain-Source Breakdown Voltage (BVDSS)
vs. Temperature
FSEZ2016 — Low-Power Green-Mode EZSWITCH without Secondary Side Feedback Circuitry
Typical Performance Characteristics (Continued)
www.fairchildsemi.com
8
FSEZ2016 devices integrate functions for low-power
switch-mode power supplies. The following descriptions
highlight the key features of the FSEZ2016.
Oscillator Operation
Startup Current
Leading-Edge Blanking (LEB)
The required startup current is only 8μA. This allows a
high-resistance, low-wattage startup resistor to supply
the controller’s startup power. A 1.5MΩ/0.25W startup
resistor can be used over a wide input range (100V240VAC) with very little power loss.
Each time the power MOSFET is switched on, a turn-on
spike occurs at the sense-resistor. To avoid premature
termination of the switching pulse, a 310ns leadingedge blanking time is built in. Conventional RC filtering
is not necessary. During this blanking period, the
current-limit comparator is disabled and cannot switch
off the gate drive.
The oscillation frequency is fixed at 65KHz.
Operating Current
The operating current is normally 3.6mA, which results
in higher efficiency and reduces the required VDD holdup capacitance. A 10μF/25V VDD hold-up capacitor can
be used over a wide input range (90V-264VAC) with very
little power loss.
Constant Output Power Limit
When the SENSE voltage across the sense resistor RS
reaches the threshold voltage, the output GATE drive is
turned off following a small propagation delay, tPD. This
propagation delay introduces an additional current
proportional to tPD•VIN/LP. The propagation delay is
nearly constant, regardless of the input line voltage VIN.
Higher input line voltages result in larger additional
currents. Under high input-line voltages, the output
power limit is higher than under low input-line voltages.
Over a wide range of AC input voltages, the variation
can be significant. To compensate for this, the threshold
voltage is adjusted by adding a positive ramp
(Vlimit_ramp). This ramp signal can vary from 0.74V to
1.04V and flattens out at 1.04V. A smaller threshold
voltage forces the output GATE drive to terminate
earlier, reducing total PWM turn-on time and making the
output power equal to that of the low line input. This
proprietary internal compensation feature ensures a
constant output power limit over a wide range of AC
input voltages (90V-264VAC).
Green-Mode Operation
The proprietary green-mode function provides off-time
modulation to linearly decrease the switching frequency
under light-load and zero-load conditions. The on-time
is limited to provide better protection against brownouts
and other abnormal conditions. Power supplies using
the FSEZ2016 can meet international restrictions
regarding standby power-consumption.
Constant Voltage (CV) and Constant
Current (CC) without Feedback
The FSEZ2016 can tightly regulate the output voltage
and provide over-current protection without requiring
secondary-side feedback signals. For improved CV and
CC accuracy, the transformer leakage inductance
should be reduced as much as possible.
Under Voltage Lockout (UVLO)
The turn-on/turn-off thresholds are fixed internally at
17V and 8V. To enable the FSEZ2016 during startup,
the hold-up capacitor must first be charged to 17V
through the startup resistor. The hold-up capacitor
continues to supply VDD before energy can be delivered
from the auxiliary winding of the main transformer. VDD
must not drop below 8V during this startup process.
This UVLO hysteresis window ensures that the hold-up
capacitor can adequately supply VDD during startup.
Over-Temperature Protection (OTP)
The FSEZ2016 has a built-in temperature-sensing
circuit to shut down PWM output if the junction
temperature exceeds 140°C. While PWM output is shut
down, the VDD voltage gradually drops to the UVLO
voltage. Some of the internal circuits are shut down,
and VDD gradually starts increasing again. When VDD
reaches 17V, all the internal circuits, including the
temperature-sensing circuit, operate normally. If the
junction temperature is still higher than 140°C, the
PWM controller shuts down immediately. This situation
continues until the temperature drops below 110°C. The
PWM output is then turned back on. The temperature
hysteresis window for the OTP circuit is 30°C.
Gate Output
FSEZ2016 — Low-Power Green-Mode EZSWITCH without Secondary Side Feedback Circuitry
Operation Description
The BiCMOS output stage is a fast totem-pole gate
driver. Cross-conduction is avoided to minimize heat
dissipation, increase efficiency, and enhance reliability.
The output driver is clamped by an internal 17V Zener
diode to protect the power MOSFET transistors against
any harmful over-voltage gate signals.
VDD Over-Voltage Clamping
VDD over-voltage clamping is built in to prevent damage
from over-voltage conditions. When VDD exceeds 22.7V,
PWM output is shut down. Over-voltage conditions may
be caused by an open photo-coupler loop or a short
circuit in the output.
© 2008 Fairchild Semiconductor Corporation
FSEZ2016 • Rev. 1.0.1
www.fairchildsemi.com
9
Slope Compensation
Noise Immunity
The sensed voltage across the current sense resistor is
used for current mode control and pulse-by-pulse
current limiting. The built-in slope compensation
improves power supply stability. Furthermore, it
prevents sub-harmonic oscillations that normally would
occur because of peak current mode control. A
positively sloped, synchronized ramp is activated with
every switching cycle. The slope of the ramp is:
0.33 × Duty
(1)
Duty(max.)
Noise from the current sense or the control signal may
cause significant pulse-width jitter, particularly in
continuous-conduction mode. Slope compensation
helps alleviate this problem. Good placement and
layout practices should be followed. The designer
should avoid long PCB traces and component leads.
Compensation and filter components should be located
near the FSEZ2016. Finally, increasing the power-MOS
gate resistance is advised.
© 2008 Fairchild Semiconductor Corporation
FSEZ2016 • Rev. 1.0.1
FSEZ2016 — Low-Power Green-Mode EZSWITCH without Secondary Side Feedback Circuitry
Operation Description (Continued)
www.fairchildsemi.com
10
Figure 17. Reference Circuit (without Secondary-Side Feedback)
BOM
Reference
Component
Reference
Component
C1
CC 4.7nF/1kV
F1
R 1Ω/1W
C2
EC 4.7μF/400V 105°C
L2
Inductor 4.7μH
C3
EC 4.7μF/400V 105°C
L3
Inductor 470μH
C4
EC 10μF/50V 105°C
L4
Inductor 80μH
C5
CC 1nF/1kV
R1
R 750kΩ
C6
EC 560μF/10V
R2
R 750kΩ
C7
EC 560μF/10V
R3
R 100kΩ
C9
Open
R4
R 10Ω
C10
CC 1nF
R5
R 2.2Ω
D1
Diode 1N4007
R6
R 47Ω
D2
Diode 1N4007
R7
R 270Ω
D3
Diode 1N4007
R8
R 0Ω
D4
Diode 1N4007
R9
R 2kΩ
D5
Diode FR107
T1
Transformer EE-16
D6
Diode FR102
U1
IC FSEZ2016
D7
Diode SB560
© 2008 Fairchild Semiconductor Corporation
FSEZ2016 • Rev. 1.0.1
FSEZ2016 — Low-Power Green-Mode EZSWITCH without Secondary Side Feedback Circuitry
Applications Information
www.fairchildsemi.com
11
Figure 18. Reference Circuit (with Secondary-Side Feedback)
BOM
Reference
Component
Reference
Component
C1
CC 4.7nF/1kV
L3
Inductor 470μH
C2
EC 4.7μF/400V 105°C
L4
Inductor 80μH
C3
EC 4.7μF/400V 105°C
R1
R 750kΩ
C4
EC 10μF/50V 105°C
R2
R 750kΩ
C5
CC 1nF/1kV
R3
R 100kΩ
C6
EC 560μF/10V
R4
R 10Ω
C7
EC 560μF/10V
R5
R 2.2Ω
C8
CC 2.2nF
R6
R 47Ω
C9
Open
R7
R 270Ω
C10
CC 1nF
R8
R 0Ω
D1
Diode 1N4007
R9
R 2kΩ
D2
Diode 1N4007
R10
R 560Ω
D3
Diode 1N4007
R11
R 20kΩ
D4
Diode 1N4007
R12
R 20kΩ
D5
Diode FR107
R13
R 20kΩ
D6
Diode FR102
T1
Transformer EE-16
D7
Diode SB560
U1
IC FSEZ2016
F1
R 1Ω/1W
U2
IC PC817
L2
Inductor 4.7μH
U3
IC TL431
© 2008 Fairchild Semiconductor Corporation
FSEZ2016 • Rev. 1.0.1
FSEZ2016 — Low-Power Green-Mode EZSWITCH without Secondary Side Feedback Circuitry
Applications Information (Continued)
www.fairchildsemi.com
12
7
10.16
9.47
5
PIN 1
INDICATOR
6.47
6.22
4
1
(0.675)
3.556
3.048
2.794
2.286
4.318
3.680
8.128
7.620
0.35
0.20
0.508 MIN
1.78
1.14
D
3.81
2.92
(7.632)
9.271
7.870
0.508
0.356
NOTES:
A) THIS PACKAGE CONFORMS TO
JEDEC MS-001 VARIATION AA EXCEPT LEAD COUNT.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR EXTRUSIONS.
D) DIMENSION WITH TERMINALS CONSTRAINED
PERPENDICULAR TO PRINTED CIRCUIT BOARD.
E) DRAWING FILE NAME: MKT-N07CREV1
FSEZ2016 — Low-Power Green-Mode EZSWITCH without Secondary Side Feedback Circuitry
Physical Dimensions
Figure 19. 7-Pin DIP-7 Package
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2008 Fairchild Semiconductor Corporation
FSEZ2016 • Rev. 1.0.1
www.fairchildsemi.com
13
FSEZ2016 — Low-Power Green-Mode EZSWITCH without Secondary Side Feedback Circuitry
© 2008 Fairchild Semiconductor Corporation
FSEZ2016 • Rev. 1.0.1
www.fairchildsemi.com
14