Revised September 2000 74ACT823 9-Bit D-Type Flip-Flop General Description Features The ACT823 is a 9-bit buffered register. It features Clock Enable and Clear which are ideal for parity bus interfacing in high performance microprogramming systems. The ACT823 offers noninverting outputs. ■ Outputs source/sink 24 mA ■ 3-STATE outputs for bus interfacing ■ Inputs and outputs are on opposite sides ■ TTL compatible inputs Ordering Code: Order Number Package Number 74ACT823SC M24B 74ACT823MTC MTC24 74ACT823SPC N24C Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. (SPC not available in Tape and Reel.) Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names Description D0–D8 Data Inputs O0–O8 Data Outputs OE Output Enable CLR Clear CP Clock Input EN Clock Enable FACT is a trademark of Fairchild Semiconductor Corporation. © 2000 Fairchild Semiconductor Corporation DS009894 www.fairchildsemi.com 74ACT823 9-Bit D-Type Flip-Flop July 1988 74ACT823 Functional Description The ACT823 consists of nine D-type edge-triggered flipflops. These have 3-STATE outputs for bus systems organized with inputs and outputs on opposite sides. The buffered clock (CP) and buffered Output Enable (OE) are common to all flip-flops. The flip-flops will store the state of their individual D-type inputs that meet the setup and hold time requirements on the LOW-to-HIGH CP transition. With OE LOW, the contents of the flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. In addition to the Clock and Out- put Enable pins, there are Clear (CLR) and Clock Enable (EN) pins. These devices are ideal for parity bus interfacing in high performance systems. When CLR is LOW and OE is LOW, the outputs are LOW. When CLR is HIGH, data can be entered into the flip-flops. When EN is LOW, data on the inputs is transferred to the outputs on the LOW-to-HIGH clock transition. When the EN is HIGH, the outputs do not change state, regardless of the data or clock input transitions. Function Table Inputs Internal Output Q O Function OE CLR EN H X L H X L H L CP D L L Z High Z H H Z High Z X X X L Z Clear L L X X X L L Clear H H H X X NC Z Hold L H H X NC NC Hold H L X H L L Z Load H H Z Load L L L Load H H H Load H H L L H L L H L H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance = LOW-to-HIGH Transition NC = No Change Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Recommended Operating Conditions −0.5V to 7.0V Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V −20 mA VI = VCC + 0.5V +20 mA DC Input Voltage (VI) Supply Voltage (VCC) 0V to VCC Output Voltage (VO) −0.5V to VCC + 0.5V 0V to VCC −40°C to +85°C Operating Temperature (TA) Minimum Input Edge Rate (∆V/∆t) DC Output Diode Current (IOK) VO = −0.5V −20 mA VO = VCC + 0.5V DC Output Voltage (VO) 4.5V to 5.5V Input Voltage (VI) 125 mV/ns VIN from 0.8V to 2.0V +20 mA VCC @ 4.5V, 5.5V −0.5V to VCC + 0.5V DC Output Source or Sink Current ±50 mA (IO) DC VCC or Ground Current ±50 mA per Output Pin (ICC or IGND) Storage Temperature (TSTG) Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. −65°C to +150°C Junction Temperature (TJ) 140°C PDIP DC Electrical Characteristics Symbol VIH VIL VOH Parameter TA = 25°C VCC (V) Typ TA = −40°C to +85°C Units Conditions Guaranteed Limits Minimum HIGH Level 4.5 1.5 2.0 2.0 Input Voltage 5.5 1.5 2.0 2.0 Maximum LOW Level 4.5 1.5 0.8 0.8 Input Voltage 4.5 1.5 0.8 0.8 Minimum HIGH Level 4.5 4.49 4.4 4.4 5.49 5.4 5.4 3.86 3.76 V V VOUT = 0.1V or VCC −0.1V VOUT = 0.1V or VCC −0.1V V IOUT = −50 µA V IOH = −24 mA VIN = VIL or VIH 4.5 VOL IOH = −24 mA (Note 2) 4.86 4.76 Maximum LOW Level 4.5 0.001 0.1 0.1 Output Voltage 5.5 0.001 0.1 0.1 4.5 0.36 0.44 5.5 0.36 0.44 5.5 ±0.1 ±1.0 µA 5.5 ±0.5 ±5.0 µA 1.5 mA VI = VCC −2.1V VOLD = 1.65V Max V IOUT = 50 µA V IOL = 24 mA VIN = VIL or VIH IIN Maximum Input Leakage Current IOZ Maximum 3-STATE Current ICCT Maximum ICC/Input 5.5 IOLD Minimum Dynamic 5.5 75 mA IOHD Output Current (Note 3) 5.5 −75 mA ICC Maximum Quiescent Supply Current 0.6 IOL = 24 mA (Note 2) 5.5 8.0 80 µA VI = VCC, GND VI = VIL, VIH VO = VCC, GND VOHD = 3.85V Min VIN = VCC or GND Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. 3 www.fairchildsemi.com 74ACT823 Absolute Maximum Ratings(Note 1) 74ACT823 AC Electrical Characteristics Symbol Parameter Maximum Clock fMAX Frequency Propagation Delay tPLH CP to On tPHL Propagation Delay CP to On tPHL Propagation Delay CLR to On tPZH Output Enable Time VCC TA = +25°C (V) CL = 50pF OE to On tPHZ Output Disable Time OE to On tPLZ Output Disable Time OE to On Max Min Units Min Typ 5.0 120 158 5.0 1.5 5.5 9.5 1.5 10.5 ns 5.0 2.0 5.5 9.5 1.5 10.5 ns 5.0 2.5 8.0 13.5 2.0 15.5 ns 1.5 6.0 10.5 1.5 11.5 ns 5.0 2.0 6.5 11.0 1.5 12.0 ns 5.0 1.5 6.5 11.0 1.5 12.0 ns 5.0 1.5 6.0 10.5 1.5 11.5 ns 5.0 Output Enable Time CL = 50 pF (Note 4) OE to On tPZL TA = −40°C to +85°C Max 109 MHz Note 4: Voltage Range 5.0 is 5.0V ± 0.5V AC Operating Requirements Symbol tS Parameter Setup Time, HIGH or LOW D to CP tH Hold Time, HIGH or LOW Dn to CP tS Setup Time, HIGH or LOW EN to CP tH Hold Time, HIGH or LOW EN to CP CP Pulse Width tW HIGH or LOW tW CLR Pulse Width, LOW tREC CLR to CP Recovery Time VCC TA = +25°C, (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF Typ Guaranteed Minimum 5.0 0.5 2.5 2.5 ns 5.0 0 2.5 2.5 ns 5.0 0 2.0 2.5 ns 5.0 0 1.0 1.0 ns 5.0 2.5 4.5 5.5 ns 5.0 3.0 5.5 5.5 ns 5.0 1.5 3.5 4.0 ns Note 5: Voltage Range 5.0 is 5.0V ± 0.5V Capacitance Symbol Parameter Typ Units CIN Input Capacitance 4.5 pF VCC = OPEN CPD Power Dissipation Capacitance 44 pF VCC = 5.0V www.fairchildsemi.com Units (Note 5) 4 Conditions 74ACT823 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B 5 www.fairchildsemi.com 74ACT823 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC24 www.fairchildsemi.com 6 74ACT823 9-Bit D-Type Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N24C Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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