Revised October 2000 74F821 10-Bit D-Type Flip-Flop General Description Features The 74F821 is a 10-bit D-type flip-flop with 3-STATE true outputs arranged in a broadside pinout. ■ 3-STATE Outputs Ordering Code: Order Number Package Number Package Description 74F821SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F821SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 2000 Fairchild Semiconductor Corporation DS009595 www.fairchildsemi.com 74F821 10-Bit D-Type Flip-Flop April 1988 74F821 Unit Loading/Fan Out Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL D0–D9 Data Inputs 1.0/1.0 20 µA/−0.6 mA OE Output Enable 1.0/1.0 20 µA/−0.6 mA 3-STATE Input CP Clock Input O0–O9 3-STATE Outputs 1.0/1.0 20 µA/−0.6 mA 150/40 (33.3) −3.0 mA/24 mA (20 mA) Function Table Functional Description The 74F821 consists of ten D-type edge-triggered flipflops. This device has 3-STATE true outputs for bus systems organized in a broadside pinning. The buffered Clock (CP) and buffered Output Enable (OE) are common to all flip-flops. The flip-flops will store the state of their individual D inputs that meet the setup and hold times requirements on the LOW-to-HIGH CP transition. With the OE LOW the content of the flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. Inputs Internal Output Function OE CP D Q O H H X NC Z H X NC Z Hold L H Z Load H L Z Load L H L Data Available H L H Data Available H X NC NC No Change in Data L X NC NC No Change in Data H H L L L L L Hold L = LOW Voltage Level H = HIGH Voltage Level X = Immaterial Z = High Impedance = LOW-to-HIGH Transition NC = No Change Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Recommended Operating Conditions Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +150°C Supply Voltage 0°C to +70°C +4.5V to +5.5V −0.5V to +7.0V VCC Pin Potential to Ground Pin Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Current Applied to Output in LOW State (Max) twice the rated IOL (mA) DC Electrical Characteristics Symbol Parameter Min Typ Max Input HIGH Voltage VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V VOH 2.0 Units VIH Output HIGH 10% VCC 2.5 Voltage 10% VCC 2.4 5% VCC 2.7 5% VCC 2.7 VOL Output LOW Voltage IIH Input HIGH Current IBVI Input HIGH Current ICEX Output HIGH Test IOD Circuit Current Input LOW Current IOZH Output Leakage Current IOZL Output Leakage Current IOS Output Short-Circuit Current ICCZ Power Supply Current IIN = −18 mA IOH = −3 mA V Min 0.5 V Min IOL = 24 mA 5.0 µA Max VIN = 2.7V 7.0 µA Max VIN = 7.0V 50 µA Max VOUT = VCC V 0.0 3.75 µA 0.0 −0.6 mA Max VIN = 0.5V 50 µA Max VOUT = 2.7V 4.75 Output Leakage IIL Recognized as a LOW Signal Min IOH = −1 mA IOH = −3 mA 10% VCC Leakage Current Input Leakage Conditions Recognized as a HIGH Signal IOH = −1 mA Breakdown Test VID VCC V −60 78 3 IID = 1.9 µA, All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded −50 µA Max VOUT = 0.5V −150 mA Max VOUT = 0V 100 mA Max VO = HIGH Z www.fairchildsemi.com 74F821 Absolute Maximum Ratings(Note 1) 74F821 AC Electrical Characteristics Symbol Parameter TA = +25°C TA = −55°C to +125°C TA = 0°C to +70°C VCC = +5.0V VCC = +5.0V VCC = +5.0V CL = 50 pF CL = 50 pF CL = 50 pF Min Typ fMAX Maximum Clock Frequency 100 150 Max Min tPLH Propagation Delay 2.0 6.4 tPHL CP to On 2.0 6.2 9.5 2.0 tPZH Output Enable Time 2.0 5.8 10.5 2.0 tPZL OE to On 2.0 6.3 10.5 2.0 tPHZ Output Disable Time 1.5 3.4 7.0 1.0 tPLZ OE to On 1.5 3.5 7.0 1.0 Max 60 9.5 2.0 Min Max 70 10.5 Units MHz 2.0 10.5 10.5 2.0 10.5 13.0 2.0 11.5 13.0 2.0 11.5 7.5 1.5 7.5 7.5 1.5 7.5 ns ns AC Operating Requirements Symbol Parameter TA = +25°C TA = −55°C to +125°C VCC = +5.0V VCC = +5.0V Min Max Min Max TA = 0°C to +70°C VCC = +5.0V Min tS(H) Setup Time, HIGH or LOW 2.5 4.0 3.0 tS(L) Dn to CP 2.5 4.0 3.0 tH(H) Hold Time, HIGH or LOW 2.5 2.5 2.5 tH(L) Dn to CP 2.5 2.5 2.5 tW(H) CP Pulse Width 5.0 6.0 6.0 tW(L) HIGH or LOW 5.0 6.0 6.0 www.fairchildsemi.com 4 Units Max ns ns 74F821 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B 5 www.fairchildsemi.com 74F821 10-Bit D-Type Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N24C Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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