Revised November 2000 74LVTH273 Low Voltage Octal D-Type Flip-Flop with Clear General Description Features The LVTH273 is a high-speed, low-power positive-edgetriggered octal D-type flip-flop featuring separate D-type inputs for each flip-flop. A buffered Clock (CP) and Clear (CLR) are common to all flip-flops. ■ Input and output interface capability to systems at 5V VCC The state of each D-type input, one setup time before the positive clock transition, is transferred to the corresponding flip-flop’s output. ■ Outputs source/sink −32 mA/+64 mA The LVTH273 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These octal flip-flops are designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVTH273 is fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation. ■ Bushold on the data inputs eliminate the need for external pull-up resistors to hold unused inputs ■ Functionally compatible with the 74 series 273 ■ Latch-up performance exceeds 500 mA ■ ESD performance: Human-body model > 2000V Machine model > 200V Charged-device model > 1000V Ordering Code: Order Number 74LVTH273WM 74LVTH273SJ 74LVTH273MTC Package Number Package Description M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols IEEE/IEC © 2000 Fairchild Semiconductor Corporation DS500100 www.fairchildsemi.com 74LVTH273 Low Voltage Octal D-Type Flip-Flop with Clear July 1999 74LVTH273 Connection Diagram Pin Descriptions Pin Names Description D0–D7 Data Inputs CP Clock Pulse Input CLR Clear O0–O7 Outputs Truth Table Inputs Dn Outputs CLR On H H H L X H or L H Oo X X L L H L CP H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Transition Oo = Previous Oo before HIGH-to-LOW of CP Functional Description The LVTH273 consists of eight positive-edge-triggered flip-flops with individual D-type inputs. The buffered Clock and Clear are common to all flip-flops. The eight flip-flops will store the state of their individual D-type inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. When the Clock is either HIGH or LOW, the D-input signal has no effect at the output. When the Clear (CLR) is LOW, all Outputs will be forced LOW. Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Symbol Parameter Value Conditions Units VCC Supply Voltage −0.5 to +4.6 VI DC Input Voltage −0.5 to +7.0 VO DC Output Voltage −0.5 to +7.0 IIK DC Input Diode Current −50 IOK DC Output Diode Current −50 VO < GND IO DC Output Current 64 VO > VCC Output at HIGH State 128 VO > VCC Output at LOW State V V Output in HIGH or LOW State (Note 2) V VI < GND mA mA mA ICC DC Supply Current per Supply Pin ±64 mA IGND DC Ground Current per Ground Pin ±128 mA TSTG Storage Temperature −65 to +150 °C Recommended Operating Conditions Symbol Parameter Min Max 2.7 3.6 V 0 5.5 V HIGH Level Output Current −32 mA LOW Level Output Current 64 mA VCC Supply Voltage VI Input Voltage IOH IOL TA Free-Air Operating Temperature ∆t/∆V Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V Units −40 85 °C 0 10 ns/V Note 1: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 2: IO Absolute Maximum Rating must be observed. DC Electrical Characteristics Symbol VCC (V) Parameter TA =−40°C to +85°C Min Typ Max Units Conditions −1.2 V II = −18 mA V VO ≤ 0.1V or (Note 3) VIK Input Clamp Diode Voltage VIH Input HIGH Voltage 2.7–3.6 VIL Input LOW Voltage 2.7–3.6 VOH Output HIGH Voltage 2.7–3.6 VCC − 0.2 2.7 2.4 3.0 2.0 VOL II(HOLD) 2.7 Output LOW Voltage Bushold Input Minimum Drive 2.0 0.8 V IOH = −32 mA 0.2 IOL = 100 µA 2.7 0.5 IOL = 24 mA 3.0 0.4 3.0 0.5 IOL = 32 mA 3.0 0.55 IOL = 64 mA 3.0 75 Input Current Control Pins Data Pins V µA 500 µA −500 Current to Change State II IOH = −8 mA 2.7 3.0 Bushold Input Over-Drive VO ≥ VCC − 0.1V IOH = −100 µA −75 II(OD) V IOL = 16 mA VI = 0.8V VI = 2.0V (Note 4) (Note 5) 3.6 10 µA VI = 5.5V 3.6 ±1 µA VI = 0V or VCC −5 µA VI = 0V 1 µA VI = VCC 0 ±100 µA 0V ≤ VI or VO ≤ 5.5V 3.6 0.19 mA Outputs HIGH 3.6 IOFF Power Off Leakage Current ICCH Power Supply Current ICCL Power Supply Current 3.6 5 mA Outputs LOW ∆ICC Increase in Power Supply Current 3.6 0.2 mA One Input at VCC − 0.6V (Note 6) Other Inputs at VCC or GND Note 3: All typical values are at VCC = 3.3V, TA = 25°C. 3 www.fairchildsemi.com 74LVTH273 Absolute Maximum Ratings(Note 1) 74LVTH273 DC Electrical Characteristics (Continued) Note 4: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 5: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 6: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND. Dynamic Switching Characteristics Symbol VCC (V) Parameter (Note 7) TA = 25°C Min Typ Conditions Units Max CL = 50 pF, RL = 500Ω VOLP Quiet Output Maximum Dynamic VOL 3.3 0.8 V (Note 8) VOLV Quiet Output Minimum Dynamic VOL 3.3 −0.8 V (Note 8) Note 7: Characterized in SOIC package. Guaranteed parameter, but not tested. Note 8: Max number of outputs defined as (n). n−1 data inputs are driven 0V to 3V. Output under test held LOW. AC Electrical Characteristics TA = −40°C to +85°C CL = 50 pF, RL = 500Ω Symbol VCC = 3.3V ± 0.3V Parameter Min Typ VCC = 2.7V Max Min Units Max (Note 9) fMAX Maximum Clock Frequency 150 tPLH Propagation Delay 1.7 4.9 1.7 5.5 tPHL CP to On 1.9 4.8 1.9 5.1 tPHL Propagation Delay CLR to On 1.6 4.8 1.6 5.4 tW Pulse Duration 3.3 3.3 tS Setup Time Data HIGH or LOW before CP 2.3 2.7 CLR HIGH before CP 2.3 2.7 0 0 tH Hold Time Data HIGH or LOW after CP 150 MHz ns ns ns ns ns Note 9: All typical values are at VCC = 3.3V, TA = 25°C. Capacitance Symbol (Note 10) Typical Units CIN Input Capacitance Parameter VCC = 0V, VI = 0V or VCC Conditions 3 pF COUT Output Capacitance VCC = 3.0V, VO = 0V or VCC 6 pF Note 10: Capacitance is measured at frequency f = 1 MHz, per MIL-STD-883B, Method 3012. www.fairchildsemi.com 4 74LVTH273 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Package Number M20B 5 www.fairchildsemi.com 74LVTH273 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II 5.3mm Wide Package Number M20D www.fairchildsemi.com 6 74LVTH273 Low Voltage Octal D-Type Flip-Flop with Clear Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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