Revised October 1999 74ACT16646 16-Bit Transceiver/Register with 3-STATE Outputs General Description Features The ACT16646 contains sixteen non-inverting bidirectional registered bus transceivers providing multiplexed transmission of data directly from the input bus or from the internal storage registers. Each byte has separate control inputs which can be shorted together for full 16-bit operation. The DIR inputs determine the direction of data flow through the device. The CPAB and CPBA inputs load data into the registers on the LOW-to-HIGH transition. ■ Independent registers for A and B buses ■ Multiplexed real-time and stored data transfers ■ Separate control logic for each byte ■ 16-bit version of the ACT646 ■ Outputs source/sink 24 mA ■ TTL-compatible inputs Ordering Code: Order Number Package Number Package Description 74ACT16646SSC MS56A 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide 74ACT16646MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Connection Diagram FACT is a trademark of Fairchild Semiconductor Corporation. © 1999 Fairchild Semiconductor Corporation DS500345 www.fairchildsemi.com 74ACT16646 16-Bit Transceiver/Register with 3-STATE Outputs August 1999 74ACT16646 Function Table Inputs G1 DIR1 H X H X H X L H L H Data I/O (Note 1) CPAB1 CPBA1 SAB1 SBA1 A0–7 B0–7 Input Input Output Operation Mode H or L H or L X X X X X X X X L X X L X X H X A Register to Bn (Stored Mode) X H X Clock An Data into A Register and Output to Bn X L X L X H X H X L H L H H or L L L L L X L L X L L X X H = HIGH Voltage Level X X H or L X = Immaterial Isolation Clock An Data into A Register Clock Bn Data Into B Register An to Bn—Real Time (Transparent Mode) Input Output Clock An Data to A Register Bn to An—Real Time (Transparent Mode) Output L = LOW Voltage Level Input Clock Bn Data into B Register B Register to An (Stored Mode) Clock Bn into B Register and Output to An = LOW-to-HIGH Transition. Note 1: The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled; i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs. Also applies to data I/O (A and B: 8-15) and #2 control pins. Storage from Bus to Register Real Time Transfer A-Bus to B-Bus Real Time Transfer B-Bus to A-Bus Transfer from Register to Bus Logic Diagram www.fairchildsemi.com 2 Recommended Operating Conditions −0.5V to +7.0V Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V −20 mA VI = VCC + 0.5V +20 mA Supply Voltage (VCC) DC Output Diode Current (IOK) VO = −0.5V −20 mA VO = VCC + 0.5V +20 mA DC Output Voltage (VO) 0V to VCC 125 mV/ns VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V ±50 mA Note 2: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. ±50 mA per Output Pin −40°C to +85°C Operating Temperature (TA) Minimum Input Edge Rate (∆V/∆t) DC VCC or Ground Current Storage Temperature 0V to VCC Output Voltage (VO) −0.5V to VCC + 0.5V DC Output Source/Sink Current (IO) 4.5V to 5.5V Input Voltage (VI) −65°C to +150°C DC Electrical Characteristics Symbol VIH VIL VOH Parameter TA = +25°C VCC (V) Typ TA = −40°C to+85°C Guaranteed Limits Minimum HIGH 4.5 1.5 2.0 2.0 Input Voltage 5.5 1.5 2.0 2.0 Maximum LOW 4.5 1.5 0.8 0.8 Input Voltage 5.5 1.5 0.8 0.8 Minimum HIGH 4.5 4.49 4.4 4.4 Output Voltage 5.5 5.49 5.4 5.4 3.86 3.76 Units V V Conditions VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V or VCC − 0.1V V IOUT = −50 µA V IOH = −24 mA VIN = VIL or VIH 4.5 5.5 VOL IOH = −24 mA (Note 3) 4.86 4.76 Maximum LOW 4.5 0.001 0.1 0.1 Output Voltage 5.5 0.001 0.1 0.1 4.5 0.36 0.44 5.5 0.36 0.44 5.5 ±0.5 ±5.0 µA 5.5 ±0.1 ±1.0 µA VI = VCC, GND 1.5 mA VI = VCC − 2.1V 80.0 µA VIN = VCC or GND 75 mA VOLD = 1.65V Max −75 mA VOHD = 3.85V Min V IOUT = 50 µA V IOL = 24 mA VIN = VIL or VIH IOZT Maximum I/O Leakage Current IIN Maximum Input Leakage Current ICCT Maximum ICC/Input ICC Max Quiescent Supply Current IOLD Minimum Dynamic IOHD Output Current (Note 4) 5.5 0.6 5.5 8.0 5.5 IOL = 24 mA (Note 3) VIN = VIL, VIH VO = VCC, GND Note 3: All outputs loaded; thresholds associated with output under test. Note 4: Maximum test duration 2.0 ms; one output loaded at a time. 3 www.fairchildsemi.com 74ACT16646 Absolute Maximum Ratings(Note 2) 74ACT16646 AC Electrical Characteristics Symbol Parameter VCC TA = +25°C (V) CL = 50 pF (Note 5) tPHL Propagation Delay tPLH Clock to Bus tPHL Propagation Delay tPLH Bus to Bus tPHL Propagation Delay tPLH Select to Bus 5.0 5.0 5.0 TA = −40°C to +85°C CL = 50 pF Min Typ Max Min Max 4.6 6.9 9.4 3.6 10.1 4.3 6.5 8.9 3.3 9.7 4.0 6.2 8.5 2.9 9.2 4.1 6.4 8.6 3.2 9.3 4.0 6.4 8.9 3.1 9.6 4.2 6.7 9.5 3.2 10.4 5.3 7.8 10.5 3.8 11.4 4.6 6.9 9.4 3.3 10.2 3.0 5.5 8.1 2.3 8.6 3.4 5.7 8.3 2.6 8.6 5.1 8.2 11.8 4.3 12.7 4.6 7.5 10.8 3.7 11.7 2.9 5.8 9.2 2.0 9.8 3.4 6.1 9.2 2.5 9.7 Units ns ns ns (w/An or Bn HIGH or LOW) tPZL Enable Time tPZH G to An/Bn tPLZ Disable Time tPHZ G to An/Bn tPZL Enable Time tPZH DIR to An/Bn tPLZ Disable Time tPHZ DIR to An/Bn 5.0 5.0 5.0 5.0 ns ns ns ns Note 5: Voltage Range 5.0 is 5.0V ± 0.5V. AC Operating Requirements Symbol Parameter VCC TA = +25°C TA = −40°C to +85°C (V) CL = 50 pF CL = 50 pF (Note 6) tS Setup Time, H or L Bus to Clock Hold Time, H or L tH Bus to Clock tW Clock Pulse Width H or L 5.0 3.0 3.0 ns 5.0 1.5 1.5 ns 5.0 4.0 4.0 ns Note 6: Voltage Range 5.0 is 5.0V ± 0.5V. Capacitance Symbol Parameter Typ Units CIN Input Capacitance 4.5 pF VCC = 5.0V CPD Power Dissipation Capacitance 95 pF VCC = 5.0V www.fairchildsemi.com Units Guaranteed Minimum 4 Conditions 74ACT16646 Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide Package Number MS56A 5 www.fairchildsemi.com 74ACT16646 16-Bit Transceiver/Register with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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