Revised February 2000 DM74ALS646 Octal 3-STATE Bus Transceiver and Register General Description Features This device incorporates an octal bus transceiver and an octal D-type register configured to enable multiplexed transmission of data from bus to bus or internal register to bus. ■ Switching specifications at 50 pF This bus transceiver features totem-pole 3-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased high-logic level drive provides this device with the capability of being connected directly to and driving the bus lines in a bus-organized system without the need for interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. ■ Switching specifications guaranteed over full temperature and VCC range ■ Advanced oxide-isolated, ion-implanted Schottky TTL process ■ 3-STATE buffer outputs drive bus lines directly ■ Multiplexed real-time and stored data ■ Independent registers for A and B buses The registers in the DM74ALS646 are edge-triggered Dtype flip-flops. On the positive transition of the clock (CAB or CBA), the input bus data is stored into the appropriate register. The CAB input controls the transfer of data into the A register and the CBA input controls the B register. The SAB and SBA control pins are provided to select whether real-time data or stored data is transferred. A LOW input level selects real-time data, and a HIGH level selects stored data. The select controls have a “make before break” configuration to eliminate a glitch which would normally occur in a typical multiplexer during the transition between store and real-time data. The enable G and direction control pins provide four modes of operation: real-time data transfer from bus A to B, realtime data transfer from bus B to A, real-time bus A and/or B data transfer to internal storage, or internally stored data transfer to bus A or B. When the enable G pin is LOW, the direction pin selects which bus receives data. When the enable G pin is HIGH, both buses become disabled yet their input function is still enabled. Ordering Code Order Number Package Number DM74ALS646WM M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Description DM74ALS646NT N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2000 Fairchild Semiconductor Corporation DS009172 www.fairchildsemi.com DM74ALS646 Octal 3-STATE Bus Transceiver and Register October 1986 DM74ALS646 Connection Diagram Function Table Inputs Data I/O (Note 1) Operation or Function G DIR CAB CBA SAB SBA A1 thru A8 B1 thru B8 X X ↑ X X X Input X X X ↑ X X Not Specified Input Store B, A Unspecified H X ↑ ↑ X X Input Input Store A and B Data H X H/L H/L X X Input Input Isolation, Hold Storage L L X X X L Output Input Real-Time B Data to a Bus L L X H/L X H Output Input Stored B Data to a Bus L H X X L X Input Output Real-Time A Data to B Bus L H H/L X H X Input Output Stored A Data to B Bus Not Specified Store A, B Unspecified H = HIGH Logic Level L = LOW Logic Level X = Don’t Care (Either LOW or HIGH Logic Levels including transitions) H/L = Either LOW or HIGH Logic Level excluding transitions ↑ = Positive going edge of pulse Note 1: The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled, i.e., data at the bus pins will be stored on every LOW-to-HIGH transition on the clock inputs. Logic Diagram www.fairchildsemi.com 2 Supply Voltage 7V Input Voltage Control Inputs 7V I/O Ports 5.5V Note 2: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. 0°C to +70°C Operating Free-Air Temperature Range −65°C to +150°C Storage Temperature Range Typical θJA N Package 44.5°C/W M Package 80.5°C/W Recommended Operating Conditions Symbol Parameter Min Nom Max Units 5 5.5 V VCC Supply Voltage VIH HIGH Level Input Voltage VIL LOW Level Input Voltage 0.8 V IOH HIGH Level Output Current −15 mA V IOL LOW Level Output Current 24 mA fCLK Clock Frequency 40 MHz tW Pulse Duration, Clocks LOW or HIGH tSU Data Setup Time, A before CAB or B before CBA (Note 3) tH Data Hold Time, A after CAB or B after CBA (Note 3) TA Free Air Operating Temperature ns 10↑ ns 0↑ ns °C 70 Note 3: ↑ = With reference to the LOW-to-HIGH transition of the respective clock. Electrical Characteristics over recommended free air temperature range Symbol Parameter Test Conditions VIC Input Clamp Voltage VCC = Min, II = −18 mA VOH HIGH Level VCC = 4.5V to 5.5V IOH = −0.4 mA Output Voltage VCC = Min IOH = −3 mA IOH = Max VOL LOW Level VCC = Min Output Voltage II Input Current at Maximum VCC = Max Input Voltage 0.5 0.5 I/O Ports, VI = 5.5V 100 Control Inputs, VI = 7V 100 I/O Ports VCC = Max V 0.35 Control Inputs Supply Current 3.2 2 IOL = 48 mA VCC = Max, VI = 2.7V (Note 4) ICC 2.4 0.4 VCC = Max, VCC = Max, VO = 2.25V V VCC − 2 0.35 LOW Level VI = 0.4V, (Note 4) Units 0.25 HIGH Level Input Current Output Drive Current Max −1.2 IOL = 24 mA IIH Input Current Typ IOL = 12 mA IIL IO Min 20 −200 −200 −30 −112 Outputs HIGH 47 Outputs LOW 55 88 Outputs Disabled 55 88 V µA µA µA mA 76 mA Note 4: For I/O ports the 3-STATE output currents (IOZH and IOZL ) are included in the IIH and IIL parameters. 3 www.fairchildsemi.com DM74ALS646 Absolute Maximum Ratings(Note 2) DM74ALS646 Switching Characteristics over recommended operating free air temperature range Symbol tPLH tPHL tPLH Parameter Conditions Propagation Delay Time VCC = 4.5V to 5.5V, LOW-to-HIGH Level Output CL = 50 pF, to A or B Propagation Delay Time R1 = R2 = 500Ω, CBA or CAB HIGH-to-LOW Level Output TA = Min to Max to A or B Propagation Delay Time A or B to B or A Propagation Delay Time A or B to HIGH-to-LOW Level Output tPLH To (Output) CBA or CAB LOW-to-HIGH Level Output tPHL From (Input) B or A Propagation Delay Time Min Max Units 10 30 ns 5 17 ns 5 20 ns 3 12 ns 12 35 ns 5 20 ns 6 25 ns 5 20 ns 3 17 ns 5 20 ns 1 10 ns 2 16 ns 6 30 ns 5 25 ns 1 10 ns 2 16 ns SBA or SAB LOW-to-HIGH Level Output to A or B (with A or B LOW) (Note 5) tPHL Propagation Delay Time SBA or SAB HIGH-to-LOW Level Output to A or B (with A or B LOW) (Note 5) tPLH Propagation Delay Time SBA or SAB LOW-to-HIGH Level Output to A or B (with A or B HIGH) (Note 5) tPHL Propagation Delay Time SBA or SAB HIGH-to-LOW Level Output to A or B (with A or B HIGH) (Note 5) tPZH Output Enable Time G to to HIGH Level Output tPZL tPHZ A or B Output Enable Time G to to LOW Level Output A or B Output Disable Time G to from HIGH Level Output tPLZ tPZH tPZL tPHZ tPLZ A or B Output Disable Time G to from LOW Level Output A or B Output Enable Time DIR to to HIGH Level Output A or B Output Enable Time DIR to to LOW Level Output A or B Output Disable Time DIR to from HIGH Level Output A or B Output Disable Time DIR to from LOW Level Output A or B Note 5: These parameters are measured with the internal output state of the storage register opposite to that of the bus input. www.fairchildsemi.com 4 DM74ALS646 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B 5 www.fairchildsemi.com DM74ALS646 Octal 3-STATE Bus Transceiver and Register Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Package Number N24C Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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