www.fairchildsemi.com TDC1044A Monolithic Video A/D Converter 4-Bit, 25 Msps Features Description • • • • • • The TDC1044A is a 25 Msps (Megasample per second) fullparallel analog-to-digital converter, capable of converting an analog signal with full-power frequency components up to 12.5 MHz into 4-bit digital words. Use of a sample-and-hold circuit is not necessary for operation of the TDC1044A. All digital inputs and outputs are TTL compatible. 4-bit resolution 1/4 LSB non-linearity Sample-and-hold circuit not required 25 Msps conversion rate Selectable output format 16-lead DIP and 20-lead PLCC packages The TDC1044A consists of 15 latching comparators, encoding logic, and an output register. A single convert signal controls the conversion operation. Output formats are true/inverted binary or true/inverted offset two’s complement codes. Applications • • • • Digital communications Video special effects Radar data conversion Medical imaging Block Diagram NMINV NLINV CONV VIN RT R1 1 R 2 R R 8 RM 15 TO 4 DECODER LATCH D1–D4 4 R R 14 65-1044A-01 R 15 R/2 RB REFERENCE RESISTOR CHAIN DIFFERENTIAL COMPARATORS (15) Rev. 1.1.2 TDC1044A Functional Description General Information The TDC1044A has three functional sections: a comparator array, encoding logic, and an output register. The comparator array compares the input signal with 15 reference voltages to produce an N-of-15 thermometer code. All the comparators referred to voltages more positive than the input signal will be off, and those referred to voltages more negative than the input signal will be on. Encoding logic converts the N-of-15 code into binary or two’s complement coding and can invert either output code. This coding function is controlled by DC signals on pins NMINV and NLINV. The output register holds the output constant between updates. Power The TDC1044A operates from two power supply voltages, +5.0V and -5.2V. The return for ICC (the current drawn from the +5.0V supply) is DGND. The return for IEE (the current drawn from the -5.2V supply) is AGND. All power and ground pins must be connected. Reference The TDC1044A converts analog signals in the range VRB £ VIN £ VRB into digital form. VRB (the voltage applied to RB at the bottom of the reference resistor chain) and VRT (the voltage applied to RB at the top of the reference resistor chain) should be between +0.1V and -1.1V. VRT should be more positive than VRB within that range. The voltage applied across the reference resistor chain (VRT – VRB) must be between 0.4V and 1.3V. Nominal voltages are VRT = 0.00V and VRB = -1.00V. These voltages may be varied dynamically up to 10MHz. Due to slight variation in the reference currents with clock and input signals, RT and RB should be low-impedance points. For circuits in which the reference is not varied, a bypass capacitor to ground is recommended. If the reference inputs are varied dynamically (as in an Automatic Gain Control circuit), a low-impedance reference source is required. A reference middle, RM, is also provided; this may be used as an input to adjust the mid-scale point in order to improve integral linearity. This point may also be used as a tap to supply a mid-scale voltage to offset the analog input. If VRM is used as an output, it must be connected to a high input impedance device which has small input current. Noise at this point may adversely affect the performance of this device. 2 PRODUCT SPECIFICATION Controls Two function control pins, NMINV and NLINV, set the output format to be either straight binary or offset two’s complement, in either true or inverted sense, according to Table 1. These pins are active LOW as signified by the prefix "N" in the signal name. They may be tied to VCC for a logic "1" and DGND for a logic "0." NMINV controls the MSB, D1; NLINV controls the three LSBs: D2, D3 and D4. Convert The TDC1044A requires a CONVert (CONV) signal. A sample is taken (the comparators are latched) within tSTO after a rising edge of CONV. The coded result is translated to the output latches on the next rising edge. The outputs hold the previous data a minimum time (tHO) after the rising edge of the CONV signal. New data becomes valid after a maximum delay time, tD. Analog Input The TDC1044A uses latching comparators which cause the input impedance to vary slightly with the signal level. For optimal performance, the source impedance of the driving circuit must less than 25 Ohms. Within the range of VEE to +0.5V, the input signal will not damage the device. If the input signal is at a voltage between VRT and VRB, the output will be a binary code between 0 and 15 inclusive. A signal outside this range will indicate either full-scale positive or full-scale negative, depending on whether the signal is offscale in the positive or negative direction. Outputs TDC1044A outputs are TTL compatible, and capable of driving four low-power Schottky TTL (54/74 LS) unit loads. The outputs hold the previous data a minimum time (tHO) after the rising edge of the CONV signal. Data becomes valid after a maximum delay time (tD) after the rising edge of CONV. For optimum performance, 2.2 kOhm pull-up resistors are recommended. No Connects Pin 3 of the TDC1044A is labeled No Connect (NC), and has no connection to the chip. Connect this pin to AGND for best noise performance. PRODUCT SPECIFICATION TDC1044A Table 1. Output Coding1 Binary Range -1.00V FS Offset Two’s Complement True Inverted True Inverted NMINV = 1 0 0 1 NLINV = 1 0 1 0 0.000V 0000 1111 1000 0111 -0.067V 0001 1110 1001 0110 -0.133V 0010 1101 1010 0101 -0.200V 0011 1100 1011 0100 -0.267V 0100 1011 1100 0011 -0.333V 0101 1010 1101 0010 -0.400V 0110 1001 1110 0001 -0.467V 0111 1000 1111 0000 -0.533V 1000 0111 0000 1111 -0.600V 1001 0110 0001 1110 -0.667V 1010 0101 0010 1101 -0.733V 1011 0100 0011 1100 -0.800V 1100 0011 0100 1011 -0.867V 1101 0010 0101 1010 -0.933V 1110 0001 0110 1001 -1.000V 1111 0000 0111 1000 Note: 1. Input voltages are at code centers. D3 D2 D1 (MSB) DGND 17 16 15 14 19 D4 (LSB) NC 18 Pin Assignments 13 VCC CONV 20 12 NMINV AGND 1 11 RM VIN 2 10 NLINV 9 4 5 6 7 8 NC NC RB VEE 3 RT NC 20 Lead PLCC NC 65-1044A-02 AGND 1 16 CONV VIN NC 2 15 3 14 RT RB VEE NLINV RM 4 13 5 12 6 11 7 10 8 9 D4 (LSB) D3 D2 D1 (MSB) DGND VCC NMINV 65-1044A-03 16 Lead DIP 3 TDC1044A PRODUCT SPECIFICATION Pin Descriptions Pin Number Pin Name DIP PLCC Value Description VCC 10 13 +5.0V Positive Supply Voltage VEE 6 8 -5.2V Negative Supply Voltage DGND 11 14 0.0V Digital Ground AGND 1 1 0.0V Analog Ground RT 4 4 0.0V Reference Resistor, Top RM 8 11 -0.5V Reference Resistor, Middle RB 5 7 -1.0V Reference Resistor, Bottom NMINV 9 12 TTL Not MSB Invert NLINV 7 10 TTL Not LSB Invert 16 20 TTL Convert 2 2 0V to -1V D1 12 15 TTL D2 13 16 TTL Power Reference Control Convert CONV Analog Input VIN Analog Input Signal Output 4 MSB Output D3 14 17 TTL D4 15 18 TTL LSB Output NC 3 3, 5, 6, 9, 19 AGND No Connect PRODUCT SPECIFICATION TDC1044A Absolute Maximum Ratings (beyond which the device may be damaged)1 Type Parameter Min Max Unit Supply Voltages VCC (measured to DGND) -0.5 7.0 V VEE (measured to AGND) +0.5 -7.0 V Input Voltages AGND (measured to DGND) -0.5 +0.5 V CONV, NMINV, NLINV (measured to DGND) -0.5 +5.5 V VIN, VRT, VRB (measured to AGND) +0.5 VEE V -2.2 +2.2 V Applied voltage (measured to DGND -0.5 +5.5 V forced3,4 -1.0 +6.0 mA 1 sec +125 °C Operating, junction +150 °C Lead, soldering (10 seconds) +300 °C +150 °C VRT (measured to VRB) Output )2 Applied current, externally Short circuit duration (single output in high state to ground) Temperature Operating, ambient -55 Storage -65 Notes: 1. Absolute maximum ratings are limiting values applied individually while all other parameters are within specified operating conditions. Functional operation under any of these conditions is NOT implied. 2. Applied voltage must be current limited to specified range. 3. Forcing voltage must be limited to specified range. 4. Current is specified as positive when flowing into the device. Operating Conditions Parameter Min. Nom. Max. Units VCC Positive Supply Voltage (measured to DGND) 4.75 5.0 5.25 V VEE Negative Supply Voltage (measured to AGND) -4.9 -5.2 -5.5 V VAGND Analog Ground Voltage (measured to DGND) -0.1 0.0 0.1 V tPWL CONV Pulse Width, LOW 17 ns tPWH CONV Pulse Width, HIGH 17 ns VIL Input Voltage, Logic LOW VIH Input Voltage, Logic HIGH IOL Output Current, Logic LOW 0.8 2.0 V V 4.0 mA IOH Output Current, Logic HIGH -400 mA VRT Most Positive Reference -1.9 0.0 0.1 V VRB Most Negative Reference -2.1 -1.0 -0.1 V VRT – VRB Reference Differential 0.2 1.0 2.0 V VIN Input Voltage VRB VRT V TA Ambient Temperature, Still Air 0 70 °C 5 TDC1044A PRODUCT SPECIFICATION Electrical Characteristics Within specified operating conditions Parameter Test Conditions Min. static1 ICC Positive Supply Current VCC = Max, IEE Negative Supply Current VEE = Max, static Max. Units 15 mA TA = 0°C to 70°C -50 mA TA = 70°C -40 mA 2 mA IREF Reference Current VRT, VRB = Nom RREF Total Reference Resistance RIN Input Equivalent Resistance CIN Input Capacitance ICB Input Constant Bias Current VEE = Max IIL Input Current, Logic LOW VCC = Max, VI - 0.5V VRT, VRB = Nom, VIN = VRB 500 Ohms 250 Kohms 25 pF 40 mA CONV -0.8 mA NMINV, NLINV -0.8 mA IIH Input Current, Logic HIGH VCC = Max, VI = 2.4V 200 mA II Input Current, Max Input Voltage VCC = Max, VI = 5.5V 1.0 mA VOL Output Voltage, Logic LOW VCC = Min, IOL = Max 0.5 V VOH Output Voltage, Logic HIGH VCC = Min, IOH = Max IOS Short Circuit Output Current VCC = Max, One pin to ground, one second duration, Output HIGH CI Digital Input Capacitance TA = 25°C, F = 1 MHz 2.4 V -300 mA 15 pF Max. Units Note: 1. Worst case: all digital inputs and outputs LOW. Switching Characteristics Within specified operating conditions 6 Parameter Test Conditions FS Maximum Conversion Rate VCC = Min, VEE = Min tSTO Sampling Time Offset VCC = Min, VEE = Min tD Digital Output Delay VCC = Min, VEE = Min, Load 1 tHO Digital Output Hold Time VCC = Max, VEE = Max, Load 1 Min. 25 5 Msps 10 ns 30 ns ns PRODUCT SPECIFICATION TDC1044A System Performance Characteristics Within specified operating conditions Parameter Test Conditions ELI Linearity Error Integral Independent ELD Linearity Error Differential Min. VRB = Nom 75 Max. Units 1.6 % 1.6 % CS Code Size VRT, VRB = Nom 125 % Nominal EOT Offset Error Top VIN = VRT +30 mV EOB Offset Error Bottom VIN = VRB +40 mV TCO Offset Error Temperature Coefficient ±20 mV/°C BW Bandwidth, Full Power Input tTR Transient Response, Full Scale 10 ns EAP Aperture Error 30 ps 12.5 MHz Timing Diagram 1 FS CONV SAMPLE N tPWH SAMPLE N+1 tPWL SAMPLE N+2 ANALOG INPUT tSTO DATA N–1 DIGITAL OUTPUT tHO DATA N DATA N+1 65-1044A-04 tD 7 TDC1044A PRODUCT SPECIFICATION Equivalent Circuits VIN VIN 1-OF-15 COMPARATORS CIN RIN ICB VRB VEE REFERENCE RESISTOR CHAIN VEEA 65-1044A-05 VEE Figure 1. Simplified Analog Input Equivalent Circuit +VCC VCC TO OUTPUT PIN 810½ VCC 20K 10K OUTPUT 40pF 1N3062 INPUT 65-1044A-06 OUTPUT EQUIVALENT CIRCUIT LOAD 1 TEST LOAD FOR DELAY MEASUREMENTS 65-1044A-07 Figure 2. Digital Input Equivalent Circuit 8 Figure 3. Output Circuits PRODUCT SPECIFICATION Applications Discussion Calibration To calibrate the TDC1044A, adjust VRT and VRB to set the 1st and 15th thresholds to the desired voltages. Assuming a 0V to -1V desired range, continuously strobe the converter with -0.0033V (1/2 LSB from 0.000V) on the analog input, and adjust VRT for output toggling between codes 0000 and 0001. Then apply -0.976V (1/2 LSB from -1.000V) and adjust VRB for toggling between codes 1110 and 1111. Instead of adjusting VRT, RT can be connected to analog ground and the 0V end of the range calibrated with an amplifier offset control. RB is a convenient point for gain adjustment that is not in the analog signal path. Typical Interface Circuit The TDC1044A does not require a special input buffer amplifier to drive the analog input because of its low input capacitance. A terminated low-impedance transmission line (<100 Ohms) connected to the VIN terminal of the device is sufficient if the input voltage levels match those of the A/D converter. However, many driver circuits lack sufficient offset control, drive current, or gain stability. The typical interface circuit in Figure 4 shows a simple amplifier and voltage reference circuit that may be used with the device. U2 is a wide-band operational amplifier with a gain factor of -1. As the video TDC1044A input increases from zero to one volt, VIN of the TDC1044A decreases from zero to -1 volt. With true binary selected (NMINV = 1 and NLINV = 1), output codes increase from 0000 to 1111. A small value resistor, R12, serves to isolate the small input capacitance of the A/D converter from the amplifier output and insure frequency stability. Pulse and frequency response of the amplifier are optimized by variable capacitor C12. The reference voltage for the TDC1044A is generated by amplifier U3. System gain is adjusted by varying R9, which controls the reference voltage level to the A/D converter. Input voltage range and input impedance for the circuit are determined by resistors R1 and R2. Formulas for calculating values for these input resistors are: 1 R1 = ----------------------------------2VR 1 æ ------------ ö – ----------è Z IN ø 1000 and 1000 R1 R2 = Z IN – æ -------------------------ö è 1000 + R1 ø where VR is the input voltage range of the circuit, ZIN is the input impedance of the circuit, and the constant 1000 comes from the value of R3. As shown, the circuit is set up for 1Vp-p 75 Ohm video input. 9 TDC1044A PRODUCT SPECIFICATION +5V L1 FERRITE BEAD INDUCTOR R5 220 C1 10 25V + 10 C12 1–6pF VIDEO INPUT 1Vp-p R1 37.4 R3 1K R2 39.2 R6 2K 1 + 3 C3 + 10 24V U4 LM313 C7 0.1 50V R9 2K 10-TURN "GAIN" C8 0.1 50V R8 2K 10-TURN "OFFSET" 2 3 3 8 R12 27 2 C10 0.1 50V 1 4 – C5 0.1 50V 8 + 4 5 C11 0.1 50V VIN D2 C6 0.1 50V CLK AGND R16 2.2K RT 15 RM RB DGND NLINV DGND NMINV 16 7 9 CONV VEE 4 –5.2V 14 U1 TDC1044A 11 6 U3 LM741C 13 R15 2.2K D3 (LSB) R11 10K 7 R14 2.2K AGND L2 FERRITE BEAD INDUCTOR C4 10 25V 12 NC D1 C9 10 0.1 14 – 50V R7 1K D0 (MSB) R4 2K U2 HA-2539 R13 2.2K VCC + C2 10 25V 65-1044A-08 Figure 4. Typical Interface Circuit 10 PRODUCT SPECIFICATION TDC1044A Notes: 11 TDC1044A Notes: 12 PRODUCT SPECIFICATION PRODUCT SPECIFICATION TDC1044A Mechanical Dimensions 16-Lead Ceramic DIP Package Inches Symbol Min. A b1 b2 c1 D E e eA L Q s1 a Notes: Millimeters Max. Min. — .200 .014 .023 .050 .065 .008 .015 .745 .840 .220 .310 .100 BSC .300 BSC .115 .160 .015 .060 .005 — 90¡ 105¡ Notes Max. — 5.08 .36 .58 1.27 1.65 .20 .38 18.92 21.33 5.59 7.87 2.54 BSC 7.62 BSC 2.92 4.06 .38 1.52 .13 — 90¡ 105¡ 1. Index area: a notch or a pin one identification mark shall be located adjacent to pin one. The manufacturer's identification shall not be used as pin one identification mark. 8 2 2. The minimum limit for dimension "b2" may be .023 (.58mm) for leads number 1, 8, 9 and 16 only. 8 4 3. Dimension "Q" shall be measured from the seating plane to the base plane. 4 5, 9 7 4. This dimension allows for off-center lid, meniscus and glass overrun. 3 6 5. The basic pin spacing is .100 (2.54mm) between centerlines. Each pin centerline shall be located within ±.010 (.25mm) of its exact longitudinal position relative to pins 1 and 16. 6. Applies to all four corners (leads number 1, 8, 9, and 16). 7. "eA" shall be measured at the center of the lead bends or at the centerline of the leads when "a" is 90¡. 8. All leads – Increase maximum limit by .003 (.08mm) measured at the center of the flat, when lead finish applied. 9. Fourteen spaces. D 8 1 9 16 NOTE 1 E s1 eA e A Q L a c1 b1 13 TDC1044A PRODUCT SPECIFICATION Mechanical Dimensions (continued) 16-Lead Plastic DIP Package Inches Symbol Min. Max. Min. Max. A A1 A2 — .015 .115 .210 — .195 — .38 2.93 5.33 — 4.95 B B1 C D D1 E E1 e eB .014 .022 .045 .070 .008 .015 .745 .840 .005 — .300 .325 .240 .280 .100 BSC — .430 .115 .160 16 L N Notes: Millimeters Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E1" do not include mold flashing. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. Terminal numbers are shown for reference only. 4. "C" dimension does not include solder finish thickness. .36 .56 1.14 1.78 .20 .38 18.92 21.33 .13 — 7.62 8.26 6.10 7.11 2.54 BSC — 10.92 2.92 4.06 16 5. Symbol "N" is the maximum number of terminals. 4 2 2 5 D 8 1 9 16 E1 D1 E e A2 A A1 C L B1 14 B eB PRODUCT SPECIFICATION TDC1044A Mechanical Dimensions (continued) 20-Lead PLCC Package Inches Symbol Min. A A1 A2 B B1 D/E D1/E1 D3/E3 e J ND/NE N ccc Max. .165 .180 .090 .120 .020 — .013 .021 .026 .032 .385 .395 .350 .356 .200 BSC .050 BSC .042 .048 5 20 — .004 Millimeters Min. Notes: Notes 1. All dimensions and tolerances conform to ANSI Y14.5M-1982 Max. 4.19 4.57 2.29 3.05 .51 — .33 .53 .66 .81 9.78 10.03 8.89 9.04 5.08 BSC 1.27 BSC 1.07 1.22 5 20 — 0.10 2. Corner and edge chamfer (J) = 45¡ 3. Dimension D1 and E1 do not include mold protrusion. Allowable protrusion is .245" (.101mm) 3 2 E E1 D J D1 D3/E3 e B1 J A A1 A2 B –C– LEAD COPLANARITY ccc C 15 TDC1044A PRODUCT SPECIFICATION Ordering Information Product Number Temperature Range Screening Package Package Marking TDC1044AB9C 0°C to 70°C Commercial 16-Lead Ceramic DIP 1044AB9C TDC1044AN9C 0°C to 70°C Commercial 16-Lead Plastic DIP 1044AN9C TDC1044AR4C 0°C to 70°C Commercial 20-Lead PLCC 1044AR4C LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS7001044A Ó 1998 Fairchild Semiconductor Corporation