ONSEMI 74HCT14

74HCT14
Hex Schmitt−Trigger
Inverter with LSTTL
Compatible Inputs
High−Performance Silicon−Gate CMOS
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The 74HCT14 may be used as a level converter for interfacing TTL
or NMOS outputs to high−speed CMOS inputs.
The HCT14 is useful to “square up” slow input rise and fall times.
Due to the hysteresis voltage of the Schmitt trigger, the HCT14 finds
applications in noisy environments.
Features
•
•
•
•
•
•
•
•
•
MARKING
DIAGRAMS
14
SOIC−14
D SUFFIX
CASE 751A
14
Output Drive Capability: 10 LSTTL Loads
TTL/NMOS−Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1.0 mA
In Compliance With the JEDEC Standard No. 7A Requirements
ESD Performance: HBM > 2000 V; Machine Model > 200 V
Chip Complexity: 72 FETs or 18 Equivalent Gates
These are Pb−Free Devices
1
HCT14G
AWLYWW
1
14
14
1
TSSOP−14
DT SUFFIX
CASE 948G
1
HCT
14
ALYW G
G
HCT14 = Device Code
A
= Assembly Location
L, WL
= Wafer Lot
Y
= Year
W, WW = Work Week
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2007
March, 2007 − Rev. 1
1
Publication Order Number:
74HCT14/D
74HCT14
PIN ASSIGNMENT
A1
1
14
VCC
Y1
2
13
A6
A2
3
12
Y6
Y2
4
11
A5
A3
5
10
Y5
Y3
6
9
A4
GND
7
8
Y4
LOGIC DIAGRAM
A1
A2
A3
A4
FUNCTION TABLE
Input
A
Output
Y
L
H
H
L
A5
A6
1
2
3
4
5
6
9
8
11
10
13
12
Y=A
Y1
Y2
Y3
Y4
Y5
Y6
PIN 14 = VCC
PIN 7 = GND
ORDERING INFORMATION
Package
Shipping †
SOIC−14
(Pb−Free)
2500 / Tape & Reel
Device
74HCT14DR2G
74HCT14DTR2G
TSSOP−14*
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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2
74HCT14
MAXIMUM RATINGS
Symbol
VCC
Parameter
Value
Unit
DC Supply Voltage
(Referenced to GND)
*0.5 to )7.0
V
VI
DC Input Voltage
(Referenced to GND)
*0.5 to VCC )0.5
V
VO
DC Output Voltage
(Referenced to GND)
*0.5 to VCC )0.5
V
IIK
DC Input Diode Current
$20
mA
IOK
DC Output Diode Current
$25
mA
IO
DC Output Sink Current
$25
mA
ICC
DC Supply Current per Supply Pin
$50
mA
IGND
DC Ground Current per Ground Pin
$50
mA
TSTG
Storage Temperature Range
*65 to )150
_C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
TJ
Junction Temperature under Bias
qJA
Thermal Resistance
PD
Power Dissipation in Still Air at 85_C
MSL
Moisture Sensitivity
FR
Flammability Rating
VESD
ILatchup
_C
_C
SOIC
TSSOP
125
170
_C/W
SOIC
TSSOP
500
450
mW
Level 1
Oxygen Index: 30% − 35%
ESD Withstand Voltage
Latchup Performance
260
)150
UL 94 V−0 @ 0.125 in
Human Body Model (Note 1)
Machine Model (Note 2)
>2000
>200
V
Above VCC and Below GND at 85_C (Note 3)
$300
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Tested to EIA/JESD22−A114−A.
2. Tested to EIA/JESD22−A115−A.
3. Tested to EIA/JESD78.
4. For high frequency or heavy load considerations, see the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VI, VO
Min
Max
Unit
DC Supply Voltage
Parameter
(Referenced to GND)
4.5
5.5
V
DC Input Voltage, Output Voltage
(Referenced to GND)
0
VCC
V
*55
)125
_C
−
(Note 5)
ns
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time (Figure 1)
5. No Limit when VI [ 50% VCC, ICC > 1 mA.
6. Unused inputs may not be left open. All inputs must be tied to a high−logic voltage level or a low−logic input voltage level.
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3
74HCT14
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Temperature Limit
VCC
Min
Max
Min
VT)max
Maximum Positive−Going
Input Threshold Voltage
VO = 0.1 V or VCC – 0.1 V
|Iout| v 20 mA
4.5
5.5
VT)min
Minimum Positive−Going
Input Threshold Voltage
VO = 0.1 V or VCC – 0.1 V
|Iout| v 20 mA
4.5
5.5
VT*max
Maximum Negative−Going
Input Threshold Voltage
VO = 0.1 V or VCC – 0.1 V
|Iout| v 20 mA
4.5
5.5
VT*min
Minimum Negative−Going
Input Threshold Voltage
VO = 0.1 V or VCC – 0.1 V
|Iout| v 20 mA
4.5
5.5
VH max
Maximum Hysteresis
Voltage
VO = 0.1 V or VCC – 0.1 V
|Iout| v 20 mA
4.5
5.5
VH min
Minimum Hysteresis
Voltage
VO = 0.1 V or VCC – 0.1 V
|Iout| v 20 mA
4.5
5.5
0.4
0.4
0.4
0.4
0.4
04
VOH
Minimum High−Level
Output Voltage
VI < VT*min
|Iout| v 20 mA
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
VI < VT*min
|Iout| v 4.0 mA
4.5
3.98
3.84
3.7
VI ≥ VT)max
|Iout| v 20 mA
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
VI ≥ VT)max
|Iout| v 4.0 mA
4.5
0.26
0.33
0.4
1.9
2.1
1.2
1.4
Max
v125_C
Parameter
Maximum Low−Level
Output Voltage
(V)
v85_C
Symbol
VOL
Test Conditions
*55_C to 25_C
1.9
2.1
1.2
1.4
1.2
1.4
0.5
0.6
Min
Unit
1.9
2.1
V
1.2
1.4
1.2
1.4
0.5
0.6
1.4
1.5
Max
V
1.2
1.4
0.5
0.6
1.4
1.5
1.4
1.5
V
V
IIK
Maximum Input
Leakage Current
VI = VCC or GND
5.5
$0.1
$1.0
$1.0
mA
ICC
Maximum Quiescent
Supply Current
(per package)
VI = VCC or GND
Iout = 0 mA
5.5
2.0
20
40
mA
DICC
Additional Quiescent
Supply Current
VI = 2.4 V, Any One Input
VI = VCC or GND, Other Inputs
lout = 0 mA
5.5
w*55_C
25_C to 125_C
2.9
2.4
mA
7. Information on typical parametric values can be found in the ON Semiconductor High−Speed CMOS Data Book (DL129/D).
AC CHARACTERISTICS (CL = 50 pF; Input tr = tf = 6.0 ns)
Guaranteed Limit
*55_C to 25_C
Symbol
Parameter
Test Conditions
Figures
Min
Max
tPLH,
tPHL
Maximum Propagation
Delay, Input A to Output
Y (L to H)
VCC = 5.0 V $10%
CL = 50 pF, Input tr = tf = 6.0 ns
1&2
32
tTLH,
tTHL
Maximum Output
Transition Time, Any
Output
VCC = 5.0 V $10%
CL = 50 pF, Input tr = tf = 6.0 ns
1&2
15
v85_C
Min
Max
v125_C
Min
Max
Unit
40
48
ns
19
22
ns
8. For propagation delays with loads other than 50 pF, and information on typical parametric values, see the ON Semiconductor High−Speed
CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD
Power Dissipation Capacitance, per Inverter (Note 9)
32
9. Used to determine the no−load dynamic power consumption: P D = CPD VCC
Semiconductor High−Speed CMOS Data Book (DL129/D).
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4
2f
pF
+ ICC VCC . For load considerations, see the ON
74HCT14
tf
INPUT A 2.7 V
1.3 V
0.3 V
OUTPUT Y
tr
tPLH
tPHL
90%
1.3 V
10%
tTLH
tTHL
Figure 1. Switching Waveforms
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
CL*
*Includes all probe and jig capacitance.
Figure 2. Test Circuit
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5
3V
GND
74HCT14
PACKAGE DIMENSIONS
SOIC−14
CASE 751A−03
ISSUE H
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
−A−
14
8
−B−
P 7 PL
0.25 (0.010)
M
7
1
G
−T−
D 14 PL
0.25 (0.010)
T B
S
A
DIM
A
B
C
D
F
G
J
K
M
P
R
J
M
K
M
F
R X 45 _
C
SEATING
PLANE
B
M
S
SOLDERING FOOTPRINT*
7X
7.04
14X
1.52
1
14X
0.58
1.27
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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6
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337 0.344
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0_
7_
0.228 0.244
0.010 0.019
74HCT14
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G−01
ISSUE B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
14X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
S
S
N
2X
14
L/2
M
B
−U−
L
PIN 1
IDENT.
N
F
7
1
0.15 (0.006) T U
0.25 (0.010)
8
S
DETAIL E
K
A
−V−
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
K1
J J1
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
SECTION N−N
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
D
H
G
DETAIL E
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
7
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.50
0.60
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN MAX
0.193 0.200
0.169 0.177
−−− 0.047
0.002 0.006
0.020 0.030
0.026 BSC
0.020 0.024
0.004 0.008
0.004 0.006
0.007 0.012
0.007 0.010
0.252 BSC
0_
8_
74HCT14
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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74HCT14/D