SN74LS156 Dual 1-of-4 Decoder/ Demultiplexer The SN74LS156 is a high speed Dual 1-of-4 Decoder/ Demultiplexer. This device has two decoders with common 2-bit Address inputs and separate gated Enable inputs. Decoder “a” has an Enable gate with one active HIGH and one active LOW input. Decoder “b” has two active LOW Enable inputs. If the Enable functions are satisfied, one output of each decoder will be LOW as selected by the address inputs. The LS156 has open collector outputs for wired-OR (DOT-AND) decoding and function generator applications. The LS156 is fabricated with the Schottky barrier diode process for high speed and are completely compatible with all ON Semiconductor TTL families. • • • • • • http://onsemi.com LS156–OPEN–COLLECTOR LOW POWER SCHOTTKY Schottky Process for High Speed Multifunction Capability Common Address Inputs True or Complement Data Demultiplexing Input Clamp Diodes Limit High Speed Termination Effects ESD > 3500 Volts 16 1 PLASTIC N SUFFIX CASE 648 GUARANTEED OPERATING RANGES Symbol VCC Parameter Supply Voltage Min Typ Max Unit 4.75 5.0 5.25 V 0 25 70 °C TA Operating Ambient Temperature Range VOH Output Voltage – High 5.5 V IOL Output Current – Low 8.0 mA 16 1 SOIC D SUFFIX CASE 751B ORDERING INFORMATION Semiconductor Components Industries, LLC, 1999 December, 1999 – Rev. 0 110 Device Package Shipping SN74LS156N 16 Pin DIP 2000 Units/Box SN74LS156D 16 Pin 2500/Tape & Reel Publication Order Number: SN74LS156/D SN74LS156 CONNECTION DIAGRAM DIP (TOP VIEW) VCC Eb Eb A0 O3b O2b O1b O0b 16 15 14 13 12 11 10 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 1 Ea 2 Ea 3 A1 4 O3a 5 O2a 6 O1a 8 GND 7 O0a LOADING (Note a) HIGH LOW 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 U.L. PIN NAMES A0, A1 Ea, Eb Ea O0 – O3 Address Inputs Enable (Active LOW) Inputs Enable (Active HIGH) Input Active LOW Outputs NOTES: a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW. LOGIC SYMBOL 1 2 13 3 E A0 DECODER a 14 15 E A0 0 1 2 3 A1 A1 0 7 6 5 4 9 DECODER b 1 3 10 11 12 VCC = PIN 16 GND = PIN 8 http://onsemi.com 111 2 SN74LS156 LOGIC DIAGRAM Ea Ea 1 7 A0 2 6 O0a Eb Eb 3 5 O1a A1 13 4 O2a 14 9 O3a 10 O0b 11 O1b 15 12 O2b O3b VCC = PIN 16 GND = PIN 8 = PIN NUMBERS FUNCTIONAL DESCRIPTION Fig. a. The LS156 has the further advantage of being able to AND the minterm functions by tying outputs together. Any number of terms can be wired-AND as shown below. The LS156 is a Dual 1-of-4 Decoder/Demultiplexer with common Address inputs and separate gated Enable inputs. When enabled, each decoder section accepts the binary weighted Address inputs (A0, A1) and provides four mutually exclusive active LOW outputs (O0 – O3). If the Enable requirements of each decoder are not met, all outputs of that decoder are HIGH. Each decoder section has a 2-input enable gate. The enable gate for Decoder “a” requires one active HIGH input and one active LOW input (Ea•Ea). In demultiplexing applications, Decoder “a” can accept either true or complemented data by using the Ea or Ea inputs respectively. The enable gate for Decoder “b” requires two active LOW inputs (Eb•Eb). The LS155 or LS156 can be used as a 1-of-8 Decoder/Demultiplexer by tying Ea to Eb and relabeling the common connection as (A2). The other Eb and Ea are connected together to form the common enable. The LS156 can be used to generate all four minterms of two variables. These four minterms are useful in some applications replacing multiple gate functions as shown in f = (E + A0 + A1) ⋅ (E + A0 + A1) ⋅ (E + A0 + A1) ⋅ (E + A0 + A1) where E = Ea + Ea; E = Eb + Eb E A0 A1 E O0 A0 A1 O0 E A0 A1 E O1 A0 A1 O1 E A0 A1 E O2 A0 A1 O2 E A0 A1 E O3 A0 A1 O3 Figure a TRUTH TABLE ADDRESS ENABLE “a” OUTPUT “a” ENABLE “b” OUTPUT “b” A0 A1 Ea Ea O0 O1 O2 O3 Eb Eb O0 O1 O2 O3 X X L H L H X X L L H H L X H H H H X H L L L L H H L H H H H H H L H H H H H H L H H H H H H L H X L L L L X H L L L L H H L H H H H H H L H H H H H H L H H H H H H L H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care http://onsemi.com 112 SN74LS156 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage IOH Output HIGH Current VOL O Output LOW Voltage IIH Input HIGH Current IIL Input LOW Current ICC Power Supply Current Min Typ Unit Max Test Conditions V Guaranteed Input HIGH Voltage for All Inputs V Guaranteed Input LOW Voltage for All Inputs – 1.5 V VCC = MIN, IIN = – 18 mA 100 µA VCC = MIN, VOH = MAX 0.25 0.4 V IOL = 4.0 mA 0.35 0.5 V IOL = 8.0 mA 20 µA VCC = MAX, VIN = 2.7 V 0.1 mA VCC = MAX, VIN = 7.0 V – 0.4 mA VCC = MAX, VIN = 0.4 V 10 mA VCC = MAX Typ Max Unit 2.0 0.8 – 0.65 VCC = VCC MIN, VIN = VIL or VIH per Truth Table AC CHARACTERISTICS (TA = 25°C) Limits Symbol Parameter Min Test Conditions tPLH tPHL Propagation Delay Address, Ea or Eb to Output 25 34 40 51 ns Figure 1 tPLH tPHL Propagation Delay Address to Output 31 34 46 51 ns Figure 2 tPLH tPHL Propagation Delay Ea to Output 32 32 48 48 ns Figure 1 VCC = 5.0 V CL = 15 pF RL = 2.0 kΩ AC WAVEFORMS VIN VOUT 1.3 V 1.3 V VIN tPHL tPLH 1.3 V 1.3 V VOUT Figure 1. 1.3 V tPHL tPLH 1.3 V 1.3 V Figure 2. http://onsemi.com 113 1.3 V