NSC 54ACT138L

54AC138 • 54ACT138
1-of-8 Decoder/Demultiplexer
General Description
Features
The ’AC/’ACT138 is a high-speed 1-of-8 decoder/
demultiplexer. This device is ideally suited for high-speed bipolar memory chip select address decoding. The multiple input enables allow parallel expansion to a 1-of-24 decoder
using just three ’AC/’ACT138 devices or a 1-of-32 decoder
using four ’AC/’ACT138 devices and one inverter.
n
n
n
n
n
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n
Logic Symbols
Connection Diagrams
ICC reduced by 50%
Demultiplexing capability
Multiple input enable for easy expansion
Active LOW mutually exclusive outputs
Outputs source/sink 24 mA
’ACT138 has TTL-compatible inputs
Standard Microcircuit Drawing (SMD)
— ’AC138: 5962-87622
— ’ACT138: 5962-87554
Pin Assignment
for DIP and Flatpak
DS100268-1
IEEE/IEC
DS100268-2
Pin Assignment
for LCC
DS100268-7
Pin Names
Description
A0–A2
Address Inputs
E1–E2
Enable Inputs
E3
Enable Input
O0–O7
Outputs
DS100268-3
FACT ® is a registered trademark of Fairchild Semiconductor Corporation.
© 1998 National Semiconductor Corporation
DS100268
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54AC138 • 54ACT138 1-of-8 Decoder/Demultiplexer
August 1998
Functional Description
pansion of the device to a 1-of-32 (5 lines to 32 lines) decoder with just four ’AC/’ACT138 devices and one inverter
(see Figure 1). The ’AC/’ACT138 can be used as an 8-output
demultiplexer by using one of the active LOW Enable inputs
as the data input and the other Enable inputs as strobes. The
Enable inputs which are not used must be permanently tied
to their appropriate active-HIGH or active-LOW state.
The ’AC/’ACT138 high-speed 1-of-8 decoder/demultiplexer
accepts three binary weighted inputs (A0, A1, A2) and, when
enabled, provides eight mutually exclusive active-LOW outputs (O0–O7). The ’AC/’ACT138 features three Enable inputs, two active-LOW (E1, E2) and one active-HIGH (E3). All
outputs will be HIGH unless E1 and E2 are LOW and E3 is
HIGH. This multiple enable function allows easy parallel ex-
Truth Table
Inputs
Outputs
E1
E2
E3
A0
A1
A2
O0
O1
O2
O3
O4
O5
O6
O7
H
X
X
X
X
X
H
H
H
H
H
H
H
H
X
H
X
X
X
X
H
H
H
H
H
H
H
H
X
X
L
X
X
X
H
H
H
H
H
H
H
H
L
L
H
L
L
L
L
H
H
H
H
H
H
H
L
L
H
H
L
L
H
L
H
H
H
H
H
H
L
L
H
L
H
L
H
H
L
H
H
H
H
H
L
L
H
H
H
L
H
H
H
L
H
H
H
H
L
L
H
L
L
H
H
H
H
H
L
H
H
H
L
L
H
H
L
H
H
H
H
H
H
L
H
H
L
L
H
L
H
H
H
H
H
H
H
H
L
H
L
L
H
H
H
H
H
H
H
H
H
H
H
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
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2
Logic Diagram
DS100268-4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
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FIGURE 1. Expansion to 1-of-32 Decoding
DS100268-5
Logic Diagram
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(Continued)
4
Absolute Maximum Ratings (Note 1)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI = −0.5V
VI = VCC + 0.5V
DC Input Voltage (VI)
DC Output Diode Current (IOK)
VO = −0.5V
VO = VCC + 0.5V
DC Output Voltage (VO)
DC Output Source
or Sink Current (IO)
DC VCC or Ground Current
per Output Pin (ICC or IGND)
Storage Temperature (TSTG)
Junction Temperature (TJ)
CDIP
Supply Voltage (VCC)
’AC
’ACT
Input Voltage (VI)
Output Voltage (VO)
Operating Temperature (TA)
54AC/ACT
Minimum Input Edge Rate (∆V/∆t)
’AC Devices
VIN from 30% to 70% of VCC
VCC @ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (∆V/∆t)
’ACT Devices
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
−0.5V to +7.0V
−20 mA
+20 mA
−0.5V to VCC + 0.5V
−20 mA
+20 mA
−0.5V to VCC + 0.5V
± 50 mA
± 50 mA
−65˚C to +150˚C
175˚C
2.0V to 6.0V
4.5V to 5.5V
0V to VCC
0V to VCC
−55˚C to +125˚C
125 mV/ns
125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recommend operation of FACT ® circuits outside databook specifications.
DC Characteristics for ’AC Family Devices
Symbol
Parameter
VCC
54AC
TA =
(V)
−55˚C to +125˚C
Units
Conditions
Guaranteed Limits
VIH
VIL
VOH
Minimum High
Level Input Voltage
Maximum Low
Level Input Voltage
Minimum High
Level Output
Voltage
3.0
2.1
4.5
3.15
5.5
3.85
3.0
0.9
4.5
1.35
5.5
1.65
3.0
2.9
4.5
4.4
5.5
5.4
3.0
2.4
4.5
3.7
5.5
4.7
3.0
0.1
4.5
0.1
5.5
0.1
3.0
0.50
4.5
0.50
VOUT = 0.1V
V
or VCC − 0.1V
V
or VCC − 0.1V
VOUT = 0.1V
IOUT = −50 µA
V
(Note 2) VIN = VIL or VIH
VOL
Maximum Low
Level Output
Voltage
−12 mA
V
IOH
−24 mA
−24 mA
IOUT = 50 µA
V
(Note 2) VIN = VIL or VIH
IIN
Maximum Input
12 mA
V
IOL 24 mA
5.5
0.50
5.5
± 1.0
µA
VI = VCC, GND
24 mA
5.5
50
mA
VOLD = 1.65V Max
5.5
−50
mA
VOHD = 3.85V Min
Leakage Current
IOLD
IOHD
(Note 3) Minimum
Dynamic Output
Current
5
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DC Characteristics for ’AC Family Devices
Symbol
Parameter
(Continued)
VCC
54AC
TA =
(V)
−55˚C to +125˚C
Units
Conditions
Guaranteed Limits
ICC
Maximum
Quiescent Supply
Current
VIN = VCC or GND
5.5
80.0
µA
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. ICC for 54AC @ 25˚C is identical to 74AC @ 25˚C.
DC Characteristics for ’ACT Family Devices
Symbol
Parameter
VCC
54ACT
TA =
(V)
−55˚C to +125˚C
Units
Conditions
Guaranteed Limits
VIH
VIL
VOH
VOL
IIN
V
VOUT = 0.1V
V
or VCC − 0.1V
VOUT = 0.1V
V
or VCC − 0.1V
IOUT = −50 µA
Minimum High
Level Input Voltage
4.5
2.0
5.5
2.0
Maximum Low
Level Input Voltage
4.5
0.8
5.5
0.8
4.5
4.4
5.5
5.4
4.5
3.70
5.5
4.70
4.5
0.1
5.5
0.1
4.5
0.50
5.5
0.50
5.5
± 1.0
µA
VI = VCC, GND
5.5
1.6
mA
VI = VCC − 2.1V
Minimum High
Level Output
Voltage
Maximum Low
Level Output
Voltage
Maximum Input
(Note 5) VIN = VIL or VIH
V
IOH −24 mA
−24 mA
V
IOUT = 50 µA
(Note 5) VIN = VIL or VIH
V
IOL 24 mA
24 mA
Leakage Current
ICCT
Maximum
ICC/Input
IOLD
IOHD
ICC
(Note 6) Minimum
Dynamic Output
Current
Maximum
Quiescent Supply
Current
5.5
50
mA
VOLD = 1.65V Max
5.5
−50
mA
VOHD = 3.85V Min
5.5
80.0
µA
VIN = VCC or GND
Note 5: All outputs loaded; thresholds on input associated with output under test.
Note 6: Maximum test duration 2.0 ms, one output loaded at a time.
Note 7: ICC for 54ACT @ 25˚C is identical to 74ACT @ 25˚C.
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AC Electrical Characteristics
54AC
TA = −55˚C
VCC
Symbol
Parameter
(V)
to +125˚C
CL = 50 pF
(Note 8)
Min
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
Fig.
Units
No.
Max
Propagation Delay
3.3
1.0
16.0
An to On
5.0
1.5
12.0
Propagation Delay
3.3
1.0
15.0
An to On
5.0
1.5
11.5
Propagation Delay
3.3
1.0
16.5
E1 or E2 to On
5.0
1.5
13.0
Propagation Delay
3.3
1.0
15.5
E1 or E2 to On
5.0
1.5
12.0
Propagation Delay
3.3
1.0
17.0
E3 to On
5.0
1.5
13.5
Propagation Delay
3.3
1.0
15.0
E3 to On
5.0
1.5
11.0
ns
ns
ns
ns
ns
ns
Note 8: Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
AC Electrical Characteristics
54ACT
TA = −55˚C
VCC
Symbol
Parameter
(V)
to +125˚C
CL = 50 pF
(Note 9)
tPLH
Propagation Delay
Fig.
Units
Min
Max
5.0
1.5
12.5
ns
5.0
1.5
12.5
ns
5.0
1.5
13.5
ns
5.0
1.5
12.5
ns
5.0
1.5
14.0
ns
5.0
1.5
12.0
ns
No.
An to On
tPHL
Propagation Delay
An to On
tPLH
Propagation Delay
E1 or E2 to On
tPHL
Propagation Delay
E1 or E2 to On
tPLH
Propagation Delay
E3 to O n
tPHL
Propagation Delay
E3 to O n
Note 9: Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
Symbol
CIN
CPD
Typ
Units
Input Capacitance
Parameter
4.5
pF
Power Dissipation
60.0
pF
Conditions
VCC = OPEN
VCC = 5.0V
Capacitance
7
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Physical Dimensions
inches (millimeters) unless otherwise noted
20 Terminal Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
16 Lead Ceramic Dual-In-Line Package (D)
NS Package Number J16A
9
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54AC138 • 54ACT138 1-of-8 Decoder/Demultiplexer
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
16 Lead Ceramic Flatpak (F)
NS Package Number W16A
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ure to perform when properly used in accordance
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