MC14066B Quad Analog Switch/Quad Multiplexer The MC14066B consists of four independent switches capable of controlling either digital or analog signals. This quad bilateral switch is useful in signal gating, chopper, modulator, demodulator and CMOS logic implementation. The MC14066B is designed to be pin−for−pin compatible with the MC14016B, but has much lower ON resistance. Input voltage swings as large as the full supply voltage can be controlled via each independent control input. Features • • • • • • • Triple Diode Protection on All Control Inputs Supply Voltage Range = 3.0 Vdc to 18 Vdc Linearized Transfer Characteristics Low Noise − 12 nV/√Cycle, f ≥ 1.0 kHz typical Pin−for−Pin Replacement for CD4016, CD4016, MC14016B For Lower RON, Use The HC4066 High−Speed CMOS Device Pb−Free Packages are Available MAXIMUM RATINGS (Voltages Referenced to VSS) Symbol VDD Parameter DC Supply Voltage Range Value Unit −0.5 to +18.0 V Vin, Vout Input or Output Voltage Range (DC or Transient) −0.5 to VDD + 0.5 V Iin Input Current (DC or Transient) per Control Pin ± 10 mA ISW Switch Through Current ± 25 mA PD Power Dissipation, per Package (Note 1) 500 mW TA Ambient Temperature Range −55 to +125 °C Tstg Storage Temperature Range −65 to +150 °C TL Lead Temperature (8−Second Soldering) 260 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/C From 65C To 125C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. © Semiconductor Components Industries, LLC, 2006 October, 2006 − Rev. 7 1 http://onsemi.com MARKING DIAGRAMS 14 PDIP−14 P SUFFIX CASE 646 MC14066BCP AWLYYWWG 1 14 SOIC−14 D SUFFIX CASE 751A 14066BG AWLYWW 1 14 14 066B ALYW TSSOP−14 DT SUFFIX CASE 948G 1 14 SOEIAJ−14 F SUFFIX CASE 965 MC14066B ALYWG 1 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or = Pb−Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. Publication Order Number: MC14066B/D MC14066B PIN ASSIGNMENT IN 1 1 14 VDD OUT 1 2 13 CONTROL 1 OUT 2 3 12 CONTROL 4 IN 2 4 11 IN 4 CONTROL 2 5 10 OUT 4 CONTROL 3 6 9 OUT 3 VSS 7 8 IN 3 LOGIC DIAGRAM AND TRUTH TABLE (1/4 OF DEVICE SHOWN) BLOCK DIAGRAM CONTROL 1 IN 1 CONTROL 2 IN 2 CONTROL 3 IN 3 CONTROL 4 IN 4 13 2 1 OUT 1 IN/OUT 5 3 4 CONTROL OUT 2 6 9 8 OUT 3 Control Switch 0 = VSS OFF 1 = VDD ON 12 10 11 OUT 4 VDD = PIN 14 VSS = PIN 7 CIRCUIT SCHEMATIC (1/4 OF CIRCUIT SHOWN) VDD VDD VDD VSS VDD CMOS INPUT OUT/IN VDD VDD VDD 300 W VSS VSS http://onsemi.com 2 Logic Diagram Restrictions VSS ≤ Vin ≤ VDD VSS ≤ Vout ≤ VDD MC14066B ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎ ÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎ ÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎ ÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎ ÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎ ÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎ ELECTRICAL CHARACTERISTICS − 55C Characteristic Symbol VDD Test Conditions 25C 125C Min Max Min Typ (2) Max Min Max Unit 3.0 18 3.0 − 18 3.0 18 V − − − 0.25 0.5 1.0 − − − 0.005 0.010 0.015 0.25 0.5 1.0 − − − 7.5 15 30 mA SUPPLY REQUIREMENTS (Voltages Referenced to VEE) Power Supply Voltage Range VDD — Quiescent Current Per Package IDD 5.0 10 15 Control Inputs: Vin = VSS or VDD, Switch I/O: VSS v VI/O v VDD, and DVswitch v 500 mV (3) ID(AV) 5.0 10 15 TA = 25C only The channel component, (Vin – Vout)/Ron, is not included.) Total Supply Current (Dynamic Plus Quiescent, Per Package Typical mA (0.07 mA/kHz) f + IDD (0.20 mA/kHz) f + IDD (0.36 mA/kHz) f + IDD CONTROL INPUTS (Voltages Referenced to VSS) Low−Level Input Voltage VIL 5.0 10 15 Ron = per spec, Ioff = per spec − − − 1.5 3.0 4.0 − − − 2.25 4.50 6.75 1.5 3.0 4.0 − − − 1.5 3.0 4.0 V High−Level Input Voltage VIH 5.0 10 15 Ron = per spec, Ioff = per spec 3.5 7.0 11 − − − 3.5 7.0 11 2.75 5.50 8.25 − − − 3.5 7.0 11 − − − V Input Leakage Current Iin 15 Vin = 0 or VDD − ± 0.1 − ±0.00001 ± 0.1 − ± 1.0 mA Input Capacitance Cin − − − − 5.0 7.5 − − pF SWITCHES IN AND OUT (Voltages Referenced to VSS) Recommended Peak−to− Peak Voltage Into or Out of the Switch VI/O − Channel On or Off 0 VDD 0 − VDD 0 VDD Vp–p Recommended Static or Dynamic Voltage Across the Switch (3) (Figure 1) DVswitch − Channel On 0 600 0 − 600 0 300 mV VOO − Vin = 0 V, No Load − − − 10 − − − mV − − − 800 400 220 − − − 250 120 80 1050 500 280 − − − 1200 520 300 W − − − 70 50 45 − − − 25 10 10 70 50 45 − − − 135 95 65 W Output Offset Voltage ON Resistance (3), Ron 5.0 10 15 DRon 5.0 10 15 Ioff 15 Vin = VIL or VIH (Control) Channel to Channel or Any One Channel − ±100 − ± 0.05 ±100 − ± 1000 nA Capacitance, Switch I/O CI/O − Switch Off − − − 10 15 − − pF Capacitance, Feedthrough (Switch Off) CI/O − − − − − 0.47 − − − pF DON Resistance Between Any Two Channels in the Same Package Off−Channel Leakage Current (Figure 6) DVswitch v 500 mV Vin = VIL or VIH (Control), and Vin = 0 to VDD (Switch) 2. Data labeled “Typ” is not to be used for design purposes, but is intended as an indication of the IC’s potential performance. 3. For voltage drops across the switch (DVswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD current may be drawn; i.e. the current out of the switch may contain both VDD and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. (See first page of this data sheet.) http://onsemi.com 3 MC14066B ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS (Note 4) (CL = 50 pF, TA = 25C unless otherwise noted.) Characteristic Propagation Delay Times Input to Output (RL = 10 kW) tPLH, tPHL = (0.17 ns/pF) CL + 15.5 ns tPLH, tPHL = (0.08 ns/pF) CL + 6.0 ns tPLH, tPHL = (0.06 ns/pF) CL + 4.0 ns Symbol VSS = 0 Vdc Control to Output (RL = 1 kW) (Figure 2) Output “1” to High Impedance VDD Vdc Min Typ (5) Max tPLH, tPHL tPHZ Unit ns 5.0 10 15 − − − 20 10 7.0 40 20 15 5.0 10 15 − − − 40 35 30 80 70 60 ns Output “0” to High Impedance tPLZ 5.0 10 15 − − − 40 35 30 80 70 60 ns High Impedance to Output “1” tPZH 5.0 10 15 − − − 60 20 15 120 40 30 ns High Impedance to Output “0” tPZL 5.0 10 15 − − − 60 20 15 120 40 30 ns Second Harmonic Distortion VSS = – 5 Vdc (Vin = 1.77 Vdc, RMS Centered @ 0.0 Vdc, RL = 10 kW, f = 1.0 kHz) − 5.0 − 0.1 − % Bandwidth (Switch ON) (Figure 3) VSS = – 5 Vdc (RL = 1 kW, 20 Log (Vout/Vin) = − 3 dB, CL = 50 pF, Vin = 5 Vp−p) − 5.0 − 65 − MHz Feedthrough Attenuation (Switch OFF) VSS = – 5 Vdc (Vin = 5 Vp−p, RL = 1 kW, fin = 1.0 MHz) (Figure 3) − 5.0 − – 50 − dB Channel Separation (Figure 4) (Vin = 5 Vp−p, RL = 1 kW, fin = 8.0 MHz) (Switch A ON, Switch B OFF) VSS = – 5 Vdc − 5.0 − – 50 − dB Crosstalk, Control Input to Signal Output (Figure 5) VSS = – 5 Vdc (R1 = 1 kW, RL = 10 kW, Control tTLH = tTHL = 20 ns) − 5.0 − 300 − 4. The formulas given are for the typical characteristics only at 25C. 5. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. http://onsemi.com 4 mVp−p MC14066B ORDERING INFORMATION Device Package MC14066BCP PDIP−14 MC14066BCPG PDIP−14 (Pb−Free) MC14066BD SOIC−14 MC14066BDG SOIC−14 (Pb−Free) MC14066BDR2 SOIC−14 MC14066BDR2G SOIC−14 (Pb−Free) MC14066BDTR2 TSSOP−14* MC14066BDTR2G TSSOP−14* MC14066BF SOEIAJ−14 MC14066BFG SOEIAJ−14 (Pb−Free) MC14066BFEL SOEIAJ−14 MC14066BFELG SOEIAJ−14 (Pb−Free) Shipping † 25 Units / Rail 55 Units / Rail 2500 / Tape & Reel 50 Units / Rail 2000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. http://onsemi.com 5 MC14066B TEST CIRCUITS Vout VC RL ON SWITCH CONTROL SECTION OF IC 20 ns VC tPZH LOAD Vout V 10% 90% Vout SOURCE CL Vx Vin VDD 90% 50% 10% VSS tPHZ 90% tPZL tPLZ Vin = VDD Vx = VSS Vin = VSS Vx = VDD 10% Figure 2. Turn−On Delay Time Test Circuit and Waveforms Figure 1. DV Across Switch VDD − VSS 2 VC = VDD FOR BANDWIDTH TEST VC = VSS FOR FEEDTHROUGH TEST Vin VDD − VSS 2 Vin VDD Vout RL CL RL CL CL VC VDD RL VSS VSS Figure 3. Bandwidth and Feedthrough Attenuation Figure 4. Channel Separation OFF CHANNEL UNDER TEST Vin A Vout 1k RL 10 k CONTROL SECTION OF IC CL = 50 pF VDD VSS VSS VDD VC = −5.0 V TO +5.0 V SWING Figure 5. Crosstalk, Control to Output Figure 6. Off Channel Leakage http://onsemi.com 6 MC14066B VDD KEITHLEY 160 DIGITAL MULTIMETER 10 k 1 kW RANGE VDD X−Y PLOTTER VSS Figure 7. Channel Resistance (RON) Test Circuit 350 300 300 250 200 150 TA = 125°C 100 25°C −55 °C 50 0 −10 RON , ON" RESISTANCE (OHMS) R ON , ON" RESISTANCE (OHMS) 350 −8.0 −6.0 −4.0 −2.0 0 0.2 4.0 6.0 8.0 250 200 150 25°C −55 °C 50 −8.0 −6.0 −4.0 −2.0 0 0.2 4.0 6.0 Vin, INPUT VOLTAGE (VOLTS) Vin, INPUT VOLTAGE (VOLTS) Figure 8. VDD = 7.5 V, VSS = − 7.5 V Figure 9. VDD = 5.0 V, VSS = − 5.0 V 700 350 600 300 500 400 300 TA = 125°C 200 25°C 100 0 −10 TA = 125°C 100 0 −10 10 RON , ON" RESISTANCE (OHMS) R ON , ON" RESISTANCE (OHMS) TYPICAL RESISTANCE CHARACTERISTICS −55 °C −8.0 −6.0 −4.0 −2.0 0 0.2 4.0 6.0 8.0 VDD = 2.5 V 200 150 5.0 V 100 7.5 V 50 −8.0 −6.0 −4.0 −2.0 0 0.2 4.0 6.0 8.0 Vin, INPUT VOLTAGE (VOLTS) Vin, INPUT VOLTAGE (VOLTS) Figure 10. VDD = 2.5 V, VSS = − 2.5 V Figure 11. Comparison at 25°C, VDD = − VSS http://onsemi.com 7 10 TA = 25°C 250 0 −10 10 8.0 10 MC14066B APPLICATIONS INFORMATION V DD and/or below V SS are anticipated on the analog channels, external diodes (Dx) are recommended as shown in Figure B. These diodes should be small signal types able to absorb the maximum anticipated current surges during clipping. The absolute maximum potential difference between V DD and V SS is 18 V. Most parameters are specified up to 15 V which is the recommended maximum difference between V DD and V SS. Figure A illustrates use of the Analog Switch. The 0−to−5 V digital control signal is used to directly control a 5 V peak−to−peak analog signal. The digital control logic levels are determined by V DD and VSS. The VDD voltage is the logic high voltage, the VSS voltage is logic low. For the example, V DD = + 5 V = logic high at the control inputs; VSS = GND = 0 V = logic low. The maximum analog signal level is determined by VDD and VSS. The analog voltage must not swing higher than V DD or lower than V SS. The example shows a 5 V peak−to−peak signal which allows no margin at either peak. If voltage transients above +5 V VSS VDD +5.0 V 5 Vp−p SWITCH IN ANALOG SIGNAL SWITCH OUT +5 V 5 Vp−p ANALOG SIGNAL + 2.5 V GND EXTERNAL CMOS DIGITAL CIRCUITRY 0−TO−5 V DIGITAL MC14066B CONTROL SIGNALS Figure A. Application Example VDD VDD DX DX SWITCH IN SWITCH OUT DX DX VSS VSS Figure B. External Germanium or Schottky Clipping Diodes http://onsemi.com 8 MC14066B PACKAGE DIMENSIONS PDIP−14 CASE 646−06 ISSUE P 14 8 1 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. B A F L N C −T− SEATING PLANE H G D 14 PL J K 0.13 (0.005) M M http://onsemi.com 9 DIM A B C D F G H J K L M N INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 −−− 10 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 −−− 10 0.38 1.01 MC14066B PACKAGE DIMENSIONS SOIC−14 CASE 751A−03 ISSUE H NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. −A− 14 8 −B− P 7 PL 0.25 (0.010) M 7 1 G −T− D 14 PL 0.25 (0.010) T B S A DIM A B C D F G J K M P R J M K M F R X 45 C SEATING PLANE B M S SOLDERING FOOTPRINT* 7X 7.04 14X 1.52 1 14X 0.58 1.27 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 10 MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.228 0.244 0.010 0.019 MC14066B PACKAGE DIMENSIONS TSSOP−14 CASE 948G−01 ISSUE B 14X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S N 2X 14 L/2 0.25 (0.010) 8 M B −U− L PIN 1 IDENT. N F 7 1 0.15 (0.006) T U NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. S S DETAIL E K A −V− ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ K1 J J1 DIM A B C D F G H J J1 K K1 L M SECTION N−N −W− C 0.10 (0.004) −T− SEATING PLANE D H G DETAIL E SOLDERING FOOTPRINT* 7.06 1 0.65 PITCH 14X 0.36 14X 1.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 11 MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0 8 INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0 8 MC14066B PACKAGE DIMENSIONS SOEIAJ−14 CASE 965−01 ISSUE A 14 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). LE 8 Q1 E HE M L 7 1 DETAIL P Z D VIEW P A e A1 b 0.13 (0.005) c M 0.10 (0.004) DIM A A1 b c D E e HE 0.50 LE M Q1 Z MILLIMETERS MIN MAX −−− 2.05 0.05 0.20 0.35 0.50 0.10 0.20 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 0 0.70 0.90 −−− 1.42 INCHES MIN MAX −−− 0.081 0.002 0.008 0.014 0.020 0.004 0.008 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 0 0.028 0.035 −−− 0.056 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 http://onsemi.com 12 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative MC14066B/D