TL594 Precision Switchmode Pulse Width Modulation Control Circuit The TL594 is a fixed frequency, pulse width modulation control circuit designed primarily for Switchmode power supply control. http://onsemi.com Features • • • • • • • • • Complete Pulse Width Modulation Control Circuitry On−Chip Oscillator with Master or Slave Operation On−Chip Error Amplifiers On−Chip 5.0 V Reference, 1.5% Accuracy Adjustable Deadtime Control Uncommitted Output Transistors Rated to 500 mA Source or Sink Output Control for Push−Pull or Single−Ended Operation Undervoltage Lockout Pb−Free Packages are Available* MARKING DIAGRAMS 16 PDIP−16 N SUFFIX CASE 648 TL594CN AWLYYWWG 1 1 16 SO−16 D SUFFIX CASE 751B TL594CDG AWLYWW 1 1 16 MAXIMUM RATINGS Rating 1 Symbol Value Unit Power Supply Voltage VCC 42 V Collector Output Voltage VC1, VC2 42 V Collector Output Current (Each Transistor) (Note 1) IC1, IC2 500 mA Amplifier Input Voltage Range VIR −0.3 to +42 V Power Dissipation @ TA ≤ 45°C PD 1000 mW Thermal Resistance Junction−to−Ambient (PDIP) Junction−to−Air (TSSOP) Junction−to−Ambient (SOIC) RqJA Operating Junction Temperature TJ 125 °C Inv Input 2 Storage Temperature Range Tstg −55 to +125 °C °C Compen/PWN Comp Input 3 Deadtime Control 4 °C CT 5 °C/W 80 140 135 Operating Ambient Temperature Range TL594CD, CN, CDTB TA Derating Ambient Temperature TA 1 A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week G or G = Pb−Free Package (Note: Microdot may be in either location) PIN CONNECTIONS Noninv Input 1 −40 to 85 45 Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Maximum thermal limits must be observed. TL59 4DTB ALYWG G TSSOP−16 DTB SUFFIX CASE 948F + Error 1 Amp − + 2 Error Amp − VCC 5.0 V REF ≈ 0.1 V Noninv 16 Input Inv 15 Input 14 Vref Output 13 Control 12 VCC Oscillator 11 C2 RT 6 Q2 Ground 7 C1 8 10 E2 Q1 9 E1 (Top View) *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2005 November, 2005 − Rev. 5 1 ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet. Publication Order Number: TL594/D TL594 RECOMMENDED OPERATING CONDITIONS Characteristics Symbol Min Typ Max Unit VCC 7.0 15 40 V VC1, VC2 − 30 40 V IC1, IC2 − − 200 mA Vin 0.3 − VCC − 2.0 V Current Into Feedback Terminal lfb − − 0.3 mA Reference Output Current lref − − 10 mA Timing Resistor RT 1.8 30 500 kW Timing Capacitor CT 0.0047 0.001 10 mF Oscillator Frequency fosc 1.0 40 300 kHz − 0.3 − 5.3 V Power Supply Voltage Collector Output Voltage Collector Output Current (Each transistor) Amplified Input Voltage PWM Input Voltage (Pins 3, 4, 13) ELECTRICAL CHARACTERISTICS (VCC = 15 V, CT = 0.01 mF, RT = 12 kW, unless otherwise noted.) For typical values TA = 25°C, for min/max values TA is the operating ambient temperature range that applies, unless otherwise noted. Characteristics Symbol Min Typ Max Unit 4.925 4.9 5.0 − 5.075 5.1 − 2.0 25 mV REFERENCE SECTION Reference Voltage (IO = 1.0 mA, TA = 25°C) (IO = 1.0 mA) Vref V Line Regulation (VCC = 7.0 V to 40 V) Regline Load Regulation (IO = 1.0 mA to 10 mA) Regload − 2.0 15 mV Short Circuit Output Current (Vref = 0 V) ISC 15 40 75 mA Collector Off−State Current (VCC = 40 V, VCE = 40 V) IC(off) − 2.0 100 mA Emitter Off−State Current (VCC = 40 V, VC = 40 V, VE = 0 V) IE(off) − − −100 mA VSAT(C) VSAT(E) − − 1.1 1.5 1.3 2.5 IOCL IOCH − − 0.1 2.0 − 20 − − 100 100 200 200 − − 40 40 100 100 OUTPUT SECTION Collector−Emitter Saturation Voltage (Note 1) Common−Emitter (VE = 0 V, IC = 200 mA) Emitter−Follower (VC = 15 V, IE = −200 mA) V mA Output Control Pin Current Low State (VOC ≤ 0.4 V) High State (VOC = Vref) Output Voltage Rise Time Common−Emitter (See Figure 13) Emitter−Follower (See Figure 14) tr Output Voltage Fall Time Common−Emitter (See Figure 13) Emitter−Follower (See Figure 14) tf ns ns ERROR AMPLIFIER SECTION Input Offset Voltage (VO (Pin 3) = 2.5 V) VIO − 2.0 10 mV Input Offset Current (VO (Pin 3) = 2.5 V) IIO − 5.0 250 nA IIB − −0.1 −1.0 mA Input Bias Current (VO (Pin 3) = 2.5 V) Input Common Mode Voltage Range (VCC = 40 V, TA = 25°C) Inverting Input Voltage Range Open Loop Voltage Gain (DVO = 3.0 V, VO = 0.5 V to 3.5 V, RL = 2.0 kW) Unity−Gain Crossover Frequency (VO = 0.5 V to 3.5 V, RL = 2.0 kW) VICR 0 to VCC−2.0 V VIR(INV) −0.3 to VCC−2.0 V AVOL 70 95 − dB fC − 700 − kHz φm − 65 − deg. Common Mode Rejection Ratio (VCC = 40 V) CMRR 65 90 − dB Power Supply Rejection Ratio (DVCC = 33 V, VO = 2.5 V, RL = 2.0 kW) PSRR − 100 − dB Phase Margin at Unity−Gain (VO = 0.5 V to 3.5 V, RL = 2.0 kW) Output Sink Current (VO (Pin 3) = 0.7 V) IO− 0.3 0.7 − mA Output Source Current (VO (Pin 3) = 3.5 V) IO+ −2.0 −4.0 − mA 1. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient temperature as possible. http://onsemi.com 2 TL594 ELECTRICAL CHARACTERISTICS (VCC = 15 V, CT = 0.01 mF, RT = 12 kW, unless otherwise noted.) For typical values TA = 25°C, for min/max values TA is the operating ambient temperature range that applies, unless otherwise noted. Characteristics Symbol Min Typ Max Unit VTH − 3.6 4.5 V II− 0.3 0.7 − mA Input Bias Current (Pin 4) (VPin 4 = 0 V to 5.25 V) IIB (DT) − −2.0 −10 mA Maximum Duty Cycle, Each Output, Push−Pull Mode (VPin 4 = 0 V, CT = 0.01 mF, RT = 12 kW) (VPin 4 = 0 V, CT = 0.001 mF, RT = 30 kW) DCmax 45 − 48 45 50 − − 0 2.8 − 3.3 − − 9.2 9.0 40 10 − − 10.8 12 PWM COMPARATOR SECTION (Test Circuit Figure 11) Input Threshold Voltage (Zero Duty Cycle) Input Sink Current (VPin 3 = 0.7 V) DEADTIME CONTROL SECTION (Test Circuit Figure 11) Input Threshold Voltage (Pin 4) (Zero Duty Cycle) (Maximum Duty Cycle) % VTH V OSCILLATOR SECTION Frequency (CT = 0.001 mF, RT = 30 kW) (CT = 0.01 mF, RT = 12 kW, TA = 25°C) (CT = 0.01 mF, RT = 12 kW, TA = Tlow to Thigh) fosc Standard Deviation of Frequency* (CT = 0.001 mF, RT = 30 kW) σfosc − 1.5 − % Frequency Change with Voltage (VCC = 7.0 V to 40 V, TA = 25°C) Dfosc (DV) − 0.2 1.0 % Frequency Change with Temperature (DTA = Tlow to Thigh, CT = 0.01 mF, RT = 12 kW) Dfosc (DT) − 4.0 − % 4.0 3.5 5.2 − 6.0 6.5 100 50 150 150 300 300 − − 8.0 8.0 15 18 − 11 − kHz UNDERVOLTAGE LOCKOUT SECTION Turn−On Threshold (VCC Increasing, Iref = 1.0 mA) TA = 25°C TA = Tlow to Thigh Vth Hysteresis TL594C,I TL594M VH V mV TOTAL DEVICE Standby Supply Current (Pin 6 at Vref, All other inputs and outputs open) (VCC = 15 V) (VCC = 40 V) Average Supply Current (VPin 4 = 2.0 V, CT = 0.01 mF, RT = 12 kW, VCC = 15 V, See Figure 11) ICC mA mA *Standard deviation is a measure of the statistical distribution about the mean as derived from the formula, σ http://onsemi.com 3 N Σ (Xn − X)2 n=1 N−1 TL594 VCC Output Control 13 8 6 D Oscillator RT CT 5 − ≈ 0.12V Q Q1 Q Q2 11 Deadtime Comparator Ck + 4 Deadtime Control 9 Flip− Flop 10 ≈ 0.7V − + 1 2 − 1 2 Error Amp 1 + PWM Comparator 0.7mA 12 − + 3 UV Lockout + − 3.5V 15 Feedback PWM Comparator Input Reference Regulator − + 16 14 Error Amp 2 Ref. Output This device contains 46 active transistors. Figure 1. Representative Block Diagram Capacitor CT Feedback/PWM Comp. Deadtime Control Flip−Flop Clock Input Flip−Flop Q Flip−Flop Q Output Q1 Emitter Output Q2 Emitter Output Control Figure 2. Timing Diagram http://onsemi.com 4 VCC 4.9V 7 Gnd TL594 APPLICATIONS INFORMATION Description common−mode input range from −0.3 V to (VCC − 2 V), and may be used to sense power−supply output voltage and current. The error−amplifier outputs are active high and are ORed together at the noninverting input of the pulse−width modulator comparator. With this configuration, the amplifier that demands minimum output on time, dominates control of the loop. The TL594 is a fixed−frequency pulse width modulation control circuit, incorporating the primary building blocks required for the control of a switching power supply. (See Figure 1) An internal−linear sawtooth oscillator is frequency− programmable by two external components, RT and CT. The approximate oscillator frequency is determined by: 1.1 RT • CT Functional Table Input/Output Controls For more information refer to Figure 3. Grounded Output pulse width modulation is accomplished by comparison of the positive sawtooth waveform across capacitor CT to either of two control signals. The NOR gates, which drive output transistors Q1 and Q2, are enabled only when the flip−flop clock−input line is in its low state. This happens only during that portion of time when the sawtooth voltage is greater than the control signals. Therefore, an increase in control−signal amplitude causes a corresponding linear decrease of output pulse width. (Refer to the Timing Diagram shown in Figure 2.) The control signals are external inputs that can be fed into the deadtime control, the error amplifier inputs, or the feedback input. The deadtime control comparator has an effective 120 mV input offset which limits the minimum output deadtime to approximately the first 4% of the sawtooth−cycle time. This would result in a maximum duty cycle on a given output of 96% with the output control grounded, and 48% with it connected to the reference line. Additional deadtime may be imposed on the output by setting the deadtime−control input to a fixed voltage, ranging between 0 V to 3.3 V. The pulse width modulator comparator provides a means for the error amplifiers to adjust the output pulse width from the maximum percent on−time, established by the deadtime control input, down to zero, as the voltage at the feedback pin varies from 0.5 V to 3.5 V. Both error amplifiers have a CT = 0.001 mF 100 k VCC = 15 V 0.01 mF 10 k 0.1 mF 1.0 k 500 1.0 k 2.0 k 5.0 k 10 k 20 k 50 k 100 k 200 k RT, TIMING RESISTANCE (W) Single−ended PWM @ Q1 and Q2 1.0 Push−pull Operation 0.5 When capacitor CT is discharged, a positive pulse is generated on the output of the deadtime comparator, which clocks the pulse−steering flip−flop and inhibits the output transistors, Q1 and Q2. With the output−control connected to the reference line, the pulse−steering flip−flop directs the modulated pulses to each of the two output transistors alternately for push−pull operation. The output frequency is equal to half that of the oscillator. Output drive can also be taken from Q1 or Q2, when single−ended operation with a maximum on−time of less than 50% is required. This is desirable when the output transformer has a ringback winding with a catch diode used for snubbing. When higher output−drive currents are required for single−ended operation, Q1 and Q2 may be connected in parallel, and the output−mode pin must be tied to ground to disable the flip−flop. The output frequency will now be equal to that of the oscillator. The TL594 has an internal 5.0 V reference capable of sourcing up to 10 mA of load current for external bias circuits. The reference has an internal accuracy of ±1.5% with a typical thermal drift of less than 50 mV over an operating temperature range of 0° to 70°C. A VOL, OPEN LOOP VOLTAGE GAIN (dB) f OSC, OSCILLATOR FREQUENCY (Hz) 500 k @ Vref fout fosc = Output Function 500 k 1.0 M 120 110 100 90 80 70 60 50 40 30 20 10 0 1.0 Figure 3. Oscillator Frequency versus Timing Resistance VCC = 15 V DVO = 3.0 V RL = 2.0 kW AVOL 10 100 1.0 k 10 k f, FREQUENCY (Hz) 100 k 0 20 40 60 80 φ 100 120 140 160 180 1.0 M Figure 4. Open Loop Voltage Gain and Phase versus Frequency http://onsemi.com 5 φ , EXCESS PHASE (DEGREES) fosc ≈ % DC, PERCENT DUTY CYCLE (EACH OUTPUT % DT, PERCENT DEADTIME (EACH OUTPUT) TL594 20 18 16 CT = 0.001 mF 14 12 10 8.0 6.0 0.01 mF 4.0 2.0 0 500 k 1.0 k 10 k 100 k 500 k 30 20 10 0 0 1.0 2.0 3.0 Figure 5. Percent Deadtime versus Oscillator Frequency Figure 6. Percent Duty Cycle versus Deadtime Control Voltage 3.5 2.0 V CE(sat) , SATURATION VOLTAGE (V) 1.7 1.6 1.5 1.4 1.3 1.2 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0 100 200 300 400 200 300 400 Figure 7. Emitter−Follower Configuration Output Saturation Voltage versus Emitter Current Figure 8. Common−Emitter Configuration Output Saturation Voltage versus Collector Current 10 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0 100 IC, COLLECTOR CURRENT (mA) 9.8 0 0 IE, EMITTER CURRENT (mA) V TH , UNDERVOLTAGE LOCKOUT THRESHOLD (V) V CE(sat) , SATURATION VOLTAGE (V) VCC = 15 V VOC = Vref 1.C T = 0.01 mF 1.RT = 10 kW 2.C T = 0.001 mF 1.RT = 30 kW 2 VDT, DEADTIME CONTROL VOLTAGE (IV) 1.8 I CC , SUPPLY CURRENT (mA) 1 40 fosc, OSCILLATOR FREQUENCY (Hz) 1.9 1.1 50 5.0 10 15 20 25 30 VCC, SUPPLY VOLTAGE (V) 35 40 6.0 Turn On 5.5 Turn Off 5.0 4.5 4.0 0 Figure 9. Standby Supply Current versus Supply Voltage 5.0 10 15 20 25 30 IL, REFERENCE LOAD CURRENT (mA) 35 Figure 10. Undervoltage Lockout Thresholds versus Reference Load Current http://onsemi.com 6 40 TL594 VCC = 15V + Vin VCC Deadtime Test Inputs Error Amplifier Under Test Feedback RT CT (+) (−) Error (+) (−) Output Control Gnd − Feedback Terminal (Pin 3) + Vref − 150 2W 50k 150 2W C1 E1 Output 1 C2 E2 Output 2 Ref Out Other Error Amplifier Figure 11. Error−Amplifier Characteristics Figure 12. Deadtime and Feedback Control Circuit 15V 15V RL 68 C Each Output Transistor C VC Each Output Transistor CL 15pF Q Q VEE E RL 68 E 90% VEE 90% 90% 90% CL 15pF VCC 10% 10% tr Gnd 10% 10% tr tf tf Figure 14. Emitter−Follower Configuration Test Circuit and Waveform Figure 13. Common−Emitter Configuration Test Circuit and Waveform http://onsemi.com 7 TL594 VO Vref To Output Voltage of System Error Amp 3 1 Vref + − R2 − 2 Error Amp 3 R1 Negative Output Voltage 2 VO = Vref Positive Output Voltage R2 1 + R1 R1 R2 VO To Output Voltage of System R1 R2 VO = Vref 1 + Figure 15. Error−Amplifier Sensing Techniques Output Control R1 Vref Output DT Q 4 CT RT R2 5 6 0.001 30k CS Vref Output Q DT 4 RS 80 Max. % on Time, each output ≈ 45 − R1 1 + R2 Figure 16. Deadtime Control Circuit Figure 17. Soft−Start Circuit C1 C1 QC Q1 2.4 V ≤ VOC ≤ Vref Q1 E1 Output Control 1.0 mA to 500 mA Single−Ended Q2 E2 1.0 mA to 250 mA Push−Pull C2 0 ≤ VOC ≤ 0.4 V E1 Output Control C2 Q2 QE E2 Figure 18. Output Connections for Single−Ended and Push−Pull Configurations http://onsemi.com 8 1.0 mA to 250 mA TL594 Vref 6 RT Master 5 CT RT CT VCC RS 12 Vin > 40V Vref 1N975A VZ = 39V 6 RT 5 Slave (Additional Circuits) CT 5.0V Ref 270 Gnd 7 Figure 19. Slaving Two or More Control Circuits Figure 20. Operation with Vin > 40 V Using External Zener +Vin = 8.0V to 20V 12 1 + 2 1.0M 33k 0.01 0.01 47 VCC C1 − 3 − 16 C2 + 8 Tip 32 TL594 Comp 15 T1 OC 13 VREF DT 14 4 CT 5 E1 RT Gnd 6 7 9 11 E2 Tip 32 L1 22 k + + 50 25V 47 10 50 35V 4.7k + 1.0 1N4934 + 4.7k 4.7k +VO = 28V IO = 0.2A 1N4934 240 10 10k 15k 0.001 All capacitors in mF Figure 21. Pulse Width Modulated Push−Pull Converter Test Conditions Results Line Regulation Vin = 10 V to 40 V 14 mV 0.28% Load Regulation Vin = 28 V, IO = 1.0 mA to 1.0 A 3.0 mV 0.06% Output Ripple Vin = 28 V, IO = 1.0 A 65 mVpp P.A.R.D. Short Circuit Current Vin = 28 V, RL = 0.1 W 1.6 A Efficiency Vin = 28 V, IO = 1.0 A 71% http://onsemi.com 9 L1 − 3.5 mH @ 0.3 A T1 − Primary: 20T C.T. #28 AWG T1 − Secondary: 12OT C.T. #36 AWG T1 − Core: Ferroxcube 1408P−L00−3CB 50 35V TL594 1.0mH @ 2.0A +Vin = 10V to 40V +VO = 5.0V Tip 32A IO = 1.0A 47 150 12 8 VCC 47k 0.1 11 C1 C2 + 50 50V TL594 CT RT 5 4 13 7 E2 9 3 − 2 + 1 Vref D.T. O.C. Gnd E1 6 Comp 1.0M 5.1k 5.1k 14 − 15 16 + 500 10V MR850 5.1k + + 10 50 10V 150 0.001 47k 0.1 Figure 22. Pulse Width Modulated Step−Down Converter Test Conditions Results Line Regulation Vin = 8.0 V to 40 V Load Regulation Vin = 12.6 V, IO = 0.2 mA to 200 mA Output Ripple Vin = 12.6 V, IO = 200 mA Short Circuit Current Vin = 12.6 V, RL = 0.1 W Efficiency Vin = 12.6 V, IO = 200 mA 3.0 mV 0.01% 5.0 mV 0.02% 40 mVpp P.A.R.D. 250 mA 72% ORDERING INFORMATION Operating Temperature Range Package Shipping † −40 to 85°C SOIC−16 48 Units/Rail −40 to 85°C SOIC−16 (Pb−Free) 48 Units/Rail −40 to 85°C SOIC−16 2400 Tape & Reel −40 to 85°C SOIC−16 (Pb−Free) 2400 Tape & Reel −40 to 85°C PDIP−16 25 Units/Rail −40 to 85°C PDIP−16 (Pb−Free) 25 Units/Rail TL594CDTBG* −40 to 85°C TSSOP−16* 96 Units/Rail TL594CDTBR2G −40 to 85°C TSSOP−16* 2500 Tape & Reel Device TL594CD TL594CDG TL594CDR2 TL594CDR2G TL594CN TL594CNG †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free. http://onsemi.com 10 TL594 PACKAGE DIMENSIONS PDIP−16 N SUFFIX CASE 648−08 ISSUE T NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. −A− 16 9 1 8 B F C L DIM A B C D F G H J K L M S S −T− SEATING PLANE K H D M J G 16 PL 0.25 (0.010) T A M M INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 SOIC−16 D SUFFIX CASE 751B−05 ISSUE J NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. −A− 16 9 −B− 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C −T− SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A S http://onsemi.com 11 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 TL594 PACKAGE DIMENSIONS TSSOP−16 DTB SUFFIX CASE 948F−01 ISSUE A 16X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S S ÇÇÇ ÉÉÉ ÇÇÇ ÉÉÉ ÇÇÇ K K1 2X L/2 16 9 J1 B −U− L SECTION N−N J PIN 1 IDENT. 8 1 N 0.25 (0.010) 0.15 (0.006) T U S A −V− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. M N F DETAIL E −W− C 0.10 (0.004) −T− SEATING PLANE H D DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ DETAIL E G ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082−1312 USA Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada Phone: 81−3−5773−3850 Email: [email protected] http://onsemi.com 12 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. TL594/D