ONSEMI UC3843AD1R2G

UC3842A, UC3843A,
UC2842A, UC2843A
High Performance
Current Mode Controllers
The UC3842A, UC3843A series of high performance fixed
frequency current mode controllers are specifically designed for
off−line and DC−to−DC converter applications offering the designer a
cost effective solution with minimal external components. These
integrated circuits feature a trimmed oscillator for precise duty cycle
control, a temperature compensated reference, high gain error
amplifier, current sensing comparator, and a high current totem pole
output ideally suited for driving a power MOSFET.
Also included are protective features consisting of input and
reference undervoltage lockouts each with hysteresis, cycle−by−cycle
current limiting, programmable output deadtime, and a latch for single
pulse metering.
These devices are available in an 8−pin dual−in−line plastic package
as well as the 14−pin plastic surface mount (SOIC−14). The SOIC−14
package has separate power and ground pins for the totem pole output
stage.
The UCX842A has UYLO thresholds of 16 V (on) and 10 V (off),
ideally suited for off−line converters. The UCX843A is tailored for
lower voltage applications having UVLO thresholds of 8.5 V (on) and
7.6 V (off).
PDIP−8
N SUFFIX
CASE 626
8
1
SOIC−14
D SUFFIX
CASE 751A
14
1
SOIC−8
D1 SUFFIX
CASE 751
8
1
PIN CONNECTIONS
Features
• Trimmed Oscillator Discharge Current for Precise Duty Cycle
•
•
•
•
•
•
•
•
•
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Control
Current Mode Operation to 500 kHz
Automatic Feed Forward Compensation
Latching PWM for Cycle−By−Cycle Current Limiting
Internally Trimmed Reference with Undervoltage Lockout
High Current Totem Pole Output
Undervoltage Lockout with Hysteresis
Low Startup and Operating Current
Direct Interface with ON Semiconductor SENSEFET™ Products
Pb−Free Packages are Available
Compensation 1
8
Vref
Voltage Feedback 2
7
VCC
Current Sense 3
6
Output
RT/CT 4
5
GND
(Top View)
Compensation
1
14 Vref
NC
2
13 NC
Voltage Feedback
3
12 VCC
NC
4
11 VC
Current Sense
5
10 Output
NC
6
9
GND
RT/CT
7
8
Power Ground
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 15 of this data sheet.
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 16 of this data sheet.
© Semiconductor Components Industries, LLC, 2005
November, 2005 − Rev. 8
1
Publication Order Number:
UC3842A/D
UC3842A, UC3843A, UC2842A, UC2843A
VCC
Vref
5.0V
Reference
8(14)
R
RTCT
VCC
Undervoltage
Lockout
Vref
Undervoltage
Lockout
R
7(12)
VC
7(11)
Output
Oscillator
4(7)
Latching
PWM
Voltage
Feedback
Input
+
−
2(3)
Output
Compensation
1(1)
Error
Amplifier
6(10)
Power
Ground
5(8)
Current
Sense
3(5) Input
GND
5(9)
Pin numbers in parenthesis are for the D suffix SOIC−14 package.
Figure 1. Simplified Block Diagram
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Bias and Driver Voltages (Zero Series Impedance, see also Total Device spec)
VCC, VC
30
V
Total Power Supply and Zener Current
(ICC + IZ)
30
mA
Output Current, Source or Sink (Note 1)
IO
1.0
A
Output Energy (Capacitive Load per Cycle)
W
5.0
J
Current Sense and Voltage Feedback Inputs
Vin
− 0.3 to + 5.5
V
Error Amp Output Sink Current
IO
10
mA
PD
RJA
862
145
mW
°C/W
PD
RJA
1.25
100
W
°C/W
Operating Junction Temperature
TJ
+ 150
°C
Operating Ambient Temperature
UC3842A, UC3843A
UC2842A, UC2843A
TA
Storage Temperature Range
Tstg
Power Dissipation and Thermal Characteristics
D Suffix, Plastic Package
Maximum Power Dissipation @ TA = 25°C
Thermal Resistance, Junction−to−Air
N Suffix, Plastic Package
Maximum Power Dissipation @ TA = 25°C
Thermal Resistance, Junction−to−Air
°C
0 to + 70
− 25 to + 85
− 65 to + 150
°C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. Maximum Package power dissipation limits must be observed.
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UC3842A, UC3843A, UC2842A, UC2843A
ELECTRICAL CHARACTERISTICS (VCC = 15 V, [Note 2], RT = 10 k, CT = 3.3 nF, TA = Tlow to Thigh [Note 3],
unless otherwise noted.)
UC284XA
UC384XA
Symbol
Min
Typ
Max
Min
Typ
Max
Unit
Vref
4.95
5.0
5.05
4.9
5.0
5.1
V
Line Regulation (VCC = 12 V to 25 V)
Regline
−
2.0
20
−
2.0
20
mV
Load Regulation (IO = 1.0 mA to 20 mA)
Regload
−
3.0
25
−
3.0
25
mV
Temperature Stability
TS
−
0.2
−
−
0.2
−
mV/°C
Total Output Variation over Line, Load, Temperature
Vref
4.9
−
5.1
4.82
−
5.18
V
Output Noise Voltage (f = 10 Hz to 10 kHz,
TJ = 25°C)
Vn
−
50
−
−
50
−
V
Long Term Stability (TA = 125°C for 1000 Hours)
S
−
5.0
−
−
5.0
−
mV
ISC
− 30
− 85
− 180
− 30
− 85
− 180
mA
47
46
52
−
57
60
47
46
52
−
57
60
Characteristics
REFERENCE SECTION
Reference Output Voltage (IO = 1.0 mA, TJ = 25°C)
Output Short Circuit Current
OSCILLATOR SECTION
Frequency
TJ = 25°C
TA = Tlow to Thigh
fosc
kHz
Frequency Change with Voltage (VCC = 12 V to 25 V)
fosc/V
−
0.2
1.0
−
0.2
1.0
%
Frequency Change with Temperature
TA = Tlow to Thigh
fosc/T
−
5.0
−
−
5.0
−
%
Vosc
−
1.6
−
−
1.6
−
Oscillator Voltage Swing (Peak−to−Peak)
Discharge Current (Vosc = 2.0 V)
TJ = 25°C
TA = Tlow to Thigh
Idischg
V
mA
7.5
7.2
8.4
−
9.3
9.5
7.5
7.2
8.4
−
9.3
9.5
2.45
2.5
2.55
2.42
2.5
2.58
ERROR AMPLIFIER SECTION
Voltage Feedback Input (VO = 2.5 V)
Input Bias Current (VFB = 2.7 V)
Open Loop Voltage Gain (VO = 2.0 V to 4.0 V)
Unity Gain Bandwidth (TJ = 25°C)
Power Supply Rejection Ratio (VCC = 12 V to 25 V)
Output Current
Sink (VO = 1.1 V, VFB = 2.7 V)
Source (VO = 5.0 V, VFB = 2.3 V)
Output Voltage Swing
High State (RL = 15 k to ground, VFB = 2.3 V)
Low State (RL = 15 k to Vref, VFB = 2.7 V)
VFB
V
IIB
−
−0.1
−1.0
−
−0.1
−2.0
A
AVOL
65
90
−
65
90
−
dB
BW
0.7
1.0
−
0.7
1.0
−
MHz
PSRR
60
70
−
60
70
−
dB
ISink
2.0
−0.5
12
−1.0
−
−
2.0
−0.5
12
−1.0
−
−
5.0
−
6.2
0.8
−
1.1
5.0
−
6.2
0.8
−
1.1
mA
ISource
V
VOH
VOL
2. Adjust VCC above the Startup threshold before setting to 15 V.
3. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
Tlow = 0°C for UC3842A, UC3843A
Thigh = +70°C for UC3842A, UC3843A
−25°C for UC2842A, UC2843A
+85°C for UC2842A, UC2843A
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UC3842A, UC3843A, UC2842A, UC2843A
ELECTRICAL CHARACTERISTICS (VCC = 15 V, [Note 4], RT = 10 k, CT = 3.3 nF, TA = Tlow to Thigh [Note 5],
unless otherwise noted.)
UC284XA
Characteristics
UC384XA
Symbol
Min
Typ
Max
Min
Typ
Max
Unit
Current Sense Input Voltage Gain (Notes 6 & 7)
AV
2.85
3.0
3.15
2.85
3.0
3.15
V/V
Maximum Current Sense Input Threshold (Note 6)
Vth
0.9
1.0
1.1
0.9
1.0
1.1
V
−
70
−
−
70
−
IIB
−
−2.0
−10
−
−2.0
−10
A
tPLH(in/out)
−
150
300
−
150
300
ns
VOL
−
−
13
12
0.1
1.6
13.5
13.4
0.4
2.2
−
−
−
−
13
12
0.1
1.6
13.5
13.4
0.4
2.2
−
−
−
0.1
1.1
−
0.1
1.1
CURRENT SENSE SECTION
Power Supply Rejection Ratio
VCC = 12 to 25 V (Note 6)
Input Bias Current
Propagation Delay (Current Sense Input to Output)
PSRR
dB
OUTPUT SECTION
Output Voltage
Low State (ISink = 20 mA)
Low State (ISink = 200 mA)
High State (ISink = 20 mA)
High State (ISink = 200 mA)
Output Voltage with UVLO Activated
VCC = 6.0 V, ISink = 1.0 mA
V
VOH
VOL(UVLO)
V
Output Voltage Rise Time (CL = 1.0 nF, TJ = 25°C)
tr
−
50
150
−
50
150
ns
Output Voltage Fall Time (CL = 1.0 nF, TJ = 25°C)
tf
−
50
150
−
50
150
ns
15
7.8
16
8.4
17
9.0
14.5
7.8
16
8.4
17.5
9.0
9.0
7.0
10
7.6
11
8.2
8.5
7.0
10
7.6
11.5
8.2
94
−
96
−
−
0
94
−
96
−
−
0
UNDERVOLTAGE LOCKOUT SECTION
Startup Threshold
UCX842A
UCX843A
Minimum Operating Voltage After Turn−On
UCX842A
UCX843A
Vth
V
VCC(min)
V
PWM SECTION
Duty Cycle
Maximum
Minimum
%
DCmax
DCmin
TOTAL DEVICE
Power Supply Current (Note 4)
Startup:
(VCC = 6.5 V for UCX843A,
(VCC = 14 V for UCX842A) Operating
ICC
Power Supply Zener Voltage (ICC = 25 mA)
VZ
mA
−
−
0.5
12
1.0
17
−
−
0.5
12
1.0
17
30
36
−
30
36
−
4. Adjust VCC above the Startup threshold before setting to 15 V.
5. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.
Tlow = 0°C for UC3842A, UC3843A
Thigh = +70°C for UC3842A, UC3843A
−25°C for UC2842A, UC2843A
+85°C for UC2842A, UC2843A
6. This parameter is measured at the latch trip point with VFB = 0 V.
V Output Compensation
7. Comparator gain is defined as: AV
V Current Sense Input
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4
V
UC3842A, UC3843A, UC2842A, UC2843A
100
% DT, PERCENT OUTPUT DEADTIME
80
20
8.0
5.0
0.8
VCC = 15 V
TA = 25°C
10 k
20 k
50 k
100 k
200 k
500 k
I dischg , DISCHARGE CURRENT (mA)
10
5.0
2.0
10 k
20 k
50 k
100 k
200 k
500 k
fOSC, OSCILLATOR FREQUENCY (Hz)
fOSC, OSCILLATOR FREQUENCY (Hz)
Figure 2. Timing Resistor versus
Oscillator Frequency
Figure 3. Output Deadtime versus
Oscillator Frequency
9.0
100
VCC = 15 V
VOSC = 2.0 V
8.5
8.0
7.5
7.0
−55
20
1.0
1.0 M
VCC = 15 V
TA = 25°C
50
−25
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
100
125
90
VCC = 15 V
CT = 3.3 nF
TA = 25°C
80
Idischg = 7.2 mA
70
60
50
40
800
1.0 k
2.0 k
3.0 k
4.0 k
6.0 k
8.0 k
Figure 5. Maximum Output Duty Cycle
versus Timing Resistor
VCC = 15 V
AV = −1.0
TA = 25°C
VCC = 15 V
AV = −1.0
TA = 25°C
3.0 V
20 mV/DIV
2.5 V
Idischg = 9.5 mA
RT, TIMING RESISTOR ()
Figure 4. Oscillator Discharge Current
versus Temperature
2.55 V
1.0 M
200 mV/DIV
2.0
Dmax , MAXIMUM OUTPUT DUTY CYCLE (%)
RT, TIMING RESISTOR (kΩ )
50
2.5 V
2.0 V
2.45 V
0.5 s/DIV
0.1 s/DIV
Figure 6. Error Amp Small Signal
Transient Response
Figure 7. Error Amp Large Signal
Transient Response
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VCC = 15 V
VO = 2.0 V to 4.0 V
RL = 100 K
TA = 25°C
80
Gain
60
0
30
60
40
90
Phase
20
120
0
150
−20
10
100
1.0 k
10 k
100 k
1.0 M
180
10 M
Vth, CURRENT SENSE INPUT THRESHOLD (V
100
φ, EXCESS PHASE (DEGREES)
A VOL , OPEN LOOP VOLTAGE GAIN (dB)
UC3842A, UC3843A, UC2842A, UC2843A
1.2
VCC = 15 V
1.0
0.8
TA = 25°C
0.6
TA = 125°C
0.4
TA = −55°C
0.2
0
2.0
4.0
6.0
VO, ERROR AMP OUTPUT VOLTAGE (V)
0
f, FREQUENCY (Hz)
Figure 9. Current Sense Input Threshold
versus Error Amp Output Voltage
ISC, REFERENCE SHORT CIRCUIT CURRENT (mA)
Δ V ref , REFERENCE VOLTAGE CHANGE (mV)
Figure 8. Error Amp Open Loop Gain and
Phase versus Frequency
110
0
VCC = 15 V
−4.0
−8.0
−12
−16
TA = 125°C
−20
TA = 55°C
TA = 25°C
20
40
60
80
100
120
90
70
50
−55
−25
0
25
50
75
100
Iref, REFERENCE SOURCE CURRENT (mA)
TA, AMBIENT TEMPERATURE (°C)
Figure 10. Reference Voltage Change
versus Source Current
Figure 11. Reference Short Circuit Current
versus Temperature
VCC = 15 V
IO = 1.0 mA to 20 mA
TA = 25°C
VCC = 12 V to 25 V
TA = 25°C
O
ΔV
O
ΔV
VCC = 15 V
RL ≤ 0.1 , OUTPUT VOLTAGE CHANGE (2.0 mV/DIV)
0
, OUTPUT VOLTAGE CHANGE (2.0 mV/DIV)
−24
8.0
2.0 ms/DIV
2.0 ms/DIV
Figure 13. Reference Line Regulation
Figure 12. Reference Load Regulation
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125
0
Source Saturation
(Load to Ground)
VCC
−1.0
TA = 25°C
−2.0
VCC = 15 V
80 s Pulsed Load
120 Hz Rate
VCC = 15 V
CL = 1.0 nF
TA = 25°C
90%
TA = −55°C
3.0
TA = −55°C
2.0
TA = 25°C
1.0
0
Sink Saturation
(Load to VCC)
0
10%
GND
200
400
600
IO, OUTPUT LOAD CURRENT (mA)
50 ns/DIV
800
Figure 15. Output Waveform
20
15
10
UCX843A
I CC , SUPPLY CURRENT (mA)
25
20 V/DIV
VCC = 30 V
CL = 15 pF
TA = 25°C
100 mA/DIV
I CC , SUPPLY CURRENT
V O , OUTPUT VOLTAGE
Figure 14. Output Saturation Voltage
versus Load Current
5
RT = 10 k
CT = 3.3 nF
VFB = 0 V
ISense = 0 V
TA = 25°C
UCX842A
V sat , OUTPUT SATURATION VOLTAGE (V)
UC3842A, UC3843A, UC2842A, UC2843A
0
0
100 ns/DIV
10
20
30
VCC , SUPPLY VOLTAGE
Figure 16. Output Cross Conduction
Figure 17. Supply Current versus
Supply Voltage
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40
UC3842A, UC3843A, UC2842A, UC2843A
VCC
VCC
Vref
8(14)
R
Internal
Bias
2.5V
RT
R
3.6V
+
+ −
−
7(12)
36V
+
Reference
Regulator
VCC
UVLO
−
Vin
+
−
VC
7(11)
Vref
UVLO
Output
Q1
Oscillator
4(7)
+
CT
Voltage Feedback
Input
2(3)
Output
Compensation
1(1)
6(10)
T Q
1.0mA
Power Ground
S
+
−
−
+
2R
Error
Amplifier
R
Q
R
5(8)
PWM
Latch
Current Sense Input
1.0V
Current Sense
Comparator
GND
5(9)
3(5)
+
−
=
Sink Only
Positive True Logic
Pin numbers in parenthesis are for the D suffix SOIC−14 package.
Figure 18. Representative Block Diagram
Capacitor CT
Latch
‘‘Set’’ Input
Output/
Compensation
Current Sense
Input
Latch
‘‘Reset’’ Input
Output
Large RT/Small CT
Small RT/Large CT
Figure 19. Timing Diagram
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RS
UC3842A, UC3843A, UC2842A, UC2843A
OPERATING DESCRIPTION
The UC3842A, UC3843A series are high performance,
fixed frequency, current mode controllers. They are
specifically designed for Off−Line and DC−to−DC
converter applications offering the designer a cost effective
solution with minimal external components. A
representative block diagram is shown in Figure 18.
is removed, or at the beginning of a soft−start interval
(Figures 24, 25). The Error Amp minimum feedback
resistance is limited by the amplifier’s source current
(0.5 mA) and the required output voltage (VOH) to reach the
comparator’s 1.0 V clamp level:
Rf(min) ≈
Oscillator
The oscillator frequency is programmed by the values
selected for the timing components RT and CT. Capacitor CT
is charged from the 5.0 V reference through resistor RT to
approximately 2.8 V and discharged to 1.2 V by an internal
current sink. During the discharge of CT, the oscillator
generates and internal blanking pulse that holds the center
input of the NOR gate high. This causes the Output to be in
a low state, thus producing a controlled amount of output
deadtime. Figure 2 shows RT versus Oscillator Frequency
and Figure 3, Output Deadtime versus Frequency, both for
given values of CT. Note that many values of RT and CT will
give the same oscillator frequency but only one combination
will yield a specific output deadtime at a given frequency.
The oscillator thresholds are temperature compensated, and
the discharge current is trimmed and guaranteed to within
±10% at TJ = 25°C. These internal circuit refinements
minimize variations of oscillator frequency and maximum
output duty cycle. The results are shown in Figures 4 and 5.
In many noise sensitive applications it may be desirable to
frequency−lock the converter to an external system clock.
This can be accomplished by applying a clock signal to the
circuit shown in Figure 21. For reliable locking, the
free−running oscillator frequency should be set about 10%
less than the clock frequency. A method for multi unit
synchronization is shown in Figure 22. By tailoring the
clock waveform, accurate Output duty cycle clamping can
be achieved.
3.0 (1.0 V) + 1.4 V
= 8800 0.5 mA
Current Sense Comparator and PWM Latch
The UC3842A, UC3843A operate as a current mode
controller, whereby output switch conduction is initiated by
the oscillator and terminated when the peak inductor current
reaches the threshold level established by the Error
Amplifier Output/Compensation (Pin 1). Thus the error
signal controls the peak inductor current on a
cycle−by−cycle basis. The current Sense Comparator PWM
Latch configuration used ensures that only a single pulse
appears at the Output during any given oscillator cycle. The
inductor current is converted to a voltage by inserting the
ground referenced sense resistor RS in series with the source
of output switch Q1. This voltage is monitored by the
Current Sense Input (Pin 3) and compared a level derived
from the Error Amp Output. The peak inductor current under
normal operating conditions is controlled by the voltage at
pin 1 where:
Ipk =
V(Pin 1) − 1.4 V
3 RS
Abnormal operating conditions occur when the power
supply output is overloaded or if output voltage sensing is
lost. Under these conditions, the Current Sense Comparator
threshold will be internally clamped to 1.0 V. Therefore the
maximum peak switch current is:
Ipk(max) =
1.0 V
RS
When designing a high power switching regulator it
becomes desirable to reduce the internal clamp voltage in
order to keep the power dissipation of RS to a reasonable
level. A simple method to adjust this voltage is shown in
Figure 23. The two external diodes are used to compensate
the internal diodes yielding a constant clamp voltage over
temperature. Erratic operation due to noise pickup can result
if there is an excessive reduction of the Ipk(max) clamp
voltage.
A narrow spike on the leading edge of the current
waveform can usually be observed and may cause the power
supply to exhibit an instability when the output is lightly
loaded. This spike is due to the power transformer
interwinding capacitance and output rectifier recovery time.
The addition of an RC filter on the Current Sense Input with
a time constant that approximates the spike duration will
usually eliminate the instability; refer to Figure 27.
Error Amplifier
A fully compensated Error Amplifier with access to the
inverting input and output is provided. It features a typical
dc voltage gain of 90 dB, and a unity gain bandwidth of
1.0 MHz with 57 degrees of phase margin (Figure 8). The
noninverting input is internally biased at 2.5 V and is not
pinned out. The converter output voltage is typically divided
down and monitored by the inverting input. The maximum
input bias current is −2.0 A which can cause an output
voltage error that is equal to the product of the input bias
current and the equivalent input divider source resistance.
The Error Amp Output (Pin 1) is provide for external loop
compensation (Figure 31). The output voltage is offset by
two diode drops (≈ 1.4 V) and divided by three before it
connects to the inverting input of the Current Sense
Comparator. This guarantees that no drive pulses appear at
the Output (Pin 6) when Pin 1 is at its lowest state (VOL).
This occurs when the power supply is operating and the load
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UC3842A, UC3843A, UC2842A, UC2843A
PIN FUNCTION DESCRIPTION
Pin
8−Pin
14−Pin
Function
1
1
Compensation
2
3
Voltage
Feedback
This is the inverting input of the Error Amplifier. It is normally connected to the switching power supply output through a resistor divider.
3
5
Current Sense
A voltage proportional to inductor current is connected to this input. The PWM uses this information to terminate the output switch conduction.
4
7
RT/CT
The Oscillator frequency and maximum Output duty cycle are programmed by connecting
resistor RT to Vref and capacitor CT to ground. Operation to 500 kHz is possible.
5
−
GND
This pin is the combined control circuitry and power ground (8−pin package only).
6
10
Output
7
12
VCC
This pin is the positive supply of the control IC.
8
14
Vref
This is the reference output. It provides charging current for capacitor CT through
resistor RT.
−
8
Power Ground
−
11
VC
−
9
GND
−
2,4,6,13
NC
Description
This pin is Error Amplifier output and is made available for loop compensation.
This output directly drives the gate of a power MOSFET. Peak currents up to 1.0 A are
sourced and sunk by this pin.
This pin is a separate power ground return (14−pin package only) that is connected back
to the power source. It is used to reduce the effects of switching transient noise on the control
circuitry.
The Output high state (VOH) is set by the voltage applied to this pin (14−pin package only).
With a separate power source connection, it can reduce the effects of switching transient
noise on the control circuitry.
This pin is the control circuitry ground return (14−pin package only) and is connected back to
the power source ground.
No connection (14−pin package only). These pins are not internally connected.
Undervoltage Lockout
and has a typical rise and fall time of 50 ns with a 1.0 nF load.
Additional internal circuitry has been added to keep the
Output in a sinking mode whenever an undervoltage lockout
is active. This characteristic eliminates the need for an
external pull−down resistor.
The SOIC−14 surface mount package provides separate
pins for VC (output supply) and Power Ground. Proper
implementation will significantly reduce the level of
switching transient noise imposed on the control circuitry.
This becomes particularly useful when reducing the Ipk(max)
clamp level. The separate VC supply input allows the
designer added flexibility in tailoring the drive voltage
independent of VCC. A zener clamp is typically connected
to this input when driving power MOSFETs in systems
where VCC is greater than 20 V. Figure 26 shows proper
power and control ground connections in a current sensing
power MOSFET application.
Two undervoltage lockout comparators have been
incorporated to guarantee that the IC is fully functional
before the output stage is enabled. The positive power
supply terminal (VCC) and the reference output (Vref) are
each monitored by separate comparators. Each has built−in
hysteresis to prevent erratic output behavior as their
respective thresholds are crossed. The VCC comparator
upper and lower thresholds are 16 V/10 V for the UCX842A,
and 8.4 V/7.6 V for the UCX843A. The Vref comparator
upper and lower thresholds are 3.6V/3.4 V. The large
hysteresis and low startup current of the UCX842A makes
it ideally suited in off−line converter applications where
efficient bootstrap startup techniques are required
(Figure 34). The UCX843A is intended for lower voltage dc
to dc converter applications. A 36 V zener is connected as
a shunt regulator form VCC to ground. Its purpose is to
protect the IC from excessive voltage that can occur during
system startup. The minimum operating voltage for the
UCX842A is 11 V and 8.2 V for the UCX843A.
Reference
The 5.0 V bandgap reference is trimmed to ±1.0%
tolerance at TJ = 25°C on the UC284XA, and ± 2.0% on the
UC384XA. Its primary purpose is to supply charging current
to the oscillator timing capacitor. The reference has short
circuit protection and is capable of providing in excess of
20 mA for powering additional control system circuitry.
Output
These devices contain a single totem pole output stage that
was specifically designed for direct drive of power
MOSFETs. It is capable of up to ±1.0 A peak drive current
http://onsemi.com
10
UC3842A, UC3843A, UC2842A, UC2843A
DESIGN CONSIDERATIONS
Do not attempt to construct the converter on
wire−wrap or plug−in prototype boards. High Frequency
circuit layout techniques are imperative to prevent pulse
width jitter. This is usually caused by excessive noise
pick−up imposed on the Current Sense or Voltage Feedback
inputs. Noise immunity can be improved by lowering circuit
impedances at these points. The printed circuit layout should
contain a ground plane with low−current signal and
high−current switch and output grounds returning on
separate paths back to the input filter capacitor. Ceramic
bypass capacitors (0.1 F) connected directly to VCC, VC,
and Vref may be required depending upon circuit layout.
This provides a low impedance path for filtering the high
frequency noise. All high current loops should be kept as
short as possible using heavy copper runs to minimize
radiated EMI. The Error Amp compensation circuitry and
the converter output voltage divider should be located close
to the IC and as far as possible from the power switch and
other noise generating components.
Current mode converters can exhibit subharmonic
oscillations when operating at a duty cycle greater than 50%
with continuous inductor current. This instability is
independent of the regulators closed−loop characteristics
and is caused by the simultaneous operating conditions of
fixed frequency and peak current detecting. Figure 20A
shows the phenomenon graphically. At t0, switch
conduction begins, causing the inductor current to rise at a
slope of m1. This slope is a function of the input voltage
divided by the inductance. At t1, the Current Sense Input
reaches the threshold established by the control voltage.
This causes the switch to turn off and the current to decay at
a slope of m2 until the next oscillator cycle. The unstable
condition can be shown if a perturbation is added to the
control voltage, resulting in a small I (dashed line). With
a fixed oscillator period, the current decay time is reduced,
and the minimum current at switch turn−on (t2) is increased
by I + I m2/m1. The minimum current at the next cycle
(t3) decreases to (I + I m2/m1) (m2/m1). This perturbation
is multiplied by m2.m1 on each succeeding cycle, alternately
increasing and decreasing the inductor current at switch
turn−on. Several oscillator cycles may be required before
the inductor current reaches zero causing the process to
commence again. If m2/m1 is greater than 1, the converter
will be unstable. Figure 20B shows that by adding an
artificial ramp that is synchronized with the PWM clock to
the control voltage, the I perturbation will decrease to zero
on succeeding cycles. This compensation ramp (m3) must
have a slope equal to or slightly greater than m2/2 for
stability. With m2/2 slope compensation, the average
inductor current follows the control voltage yielding true
current mode operation. The compensating ramp can be
derived from the oscillator and added to either the Voltage
Feedback or Current Sense inputs (Figure 33).
(A)
I
Control Voltage
m2
m1
Inductor
Current
I + I m2
m1
m2
I + I m
1
Oscillator Period
t1
t0
m2
m1
t3
t2
(B)
Control Voltage
I
m3
m1
m2
Inductor
Current
Oscillator Period
t4
t5
Figure 20. Continuous Current Waveforms
http://onsemi.com
11
t6
UC3842A, UC3843A, UC2842A, UC2843A
Vref
8(14)
R
Bias
RT
RB
6
CT
4(7)
47
2(3)
5
2
+
−
2R
R
EA
5.0k
0.01
+
5.0k
+
−
+
−
Bias
R
Osc
R
3
Q
S
+
−
7
2(3)
1(1)
5(9)
1.44
f=
(RA + 2RB)C
The diode clamp is required if the Sync amplitude is large enough to
cause the bottom side of CT to go more than 300 mV below ground.
VCC
+
−
+
R
Bias
R
+
+
−
2(3)
7(11)
−
Osc
R2
−
+
−
+
8(14)
R
Bias
6(10)
R
S
1.0mA
Q
R
Comp/Latch
−
+
2R
R
+
4(7)
+
−
RS
2(3)
1.0M
5(9)
1.67
R2
R1
+ 0.33 x 10 − 3
R1 R2
R1 + R2
VClamp
RS
Ipk(max) =
+1
C
2R
R
EA
Vin
7(12)
R
Bias
R
5(9)
+
Osc
+
4(7)
+
−
2(3)
5.0Vref
7(11)
Q1
1.0mA
−
+
2R
R
R2
S
Q
R
Comp/Latch
1.0V
R1
VClamp =
1.67
R1
Ipk(max) =
+1
VClamp
RS
tSoftstart = − In
(11)
3(5)
Control CIrcuitry
Ground:
To Pin (9)
RS Ipk rDS(on)
rDM(on) + RS
S
M
K
(8)
(5)
5(9)
R2
−
+
−
S
Q
−
R
+
Comp/Latch
RS
MPSA63
+
(10) G
5(8)
1(1)
C
+
−
VPin 5 =
If: SENSEFET = MTP10N10M
RS = 200
Then: Vpin 5 = 0.075 Ipk
D SENSEFET
−
6(10)
VClamp
EA
+
−
Vin
(12)
+
−
+
−
Q
1.0V
VCC
8(14)
R
Figure 24. Soft−Start Circuit
VCC
+
−
−
+
1(1)
Figure 23. Adjustable Reduction of Clamp Level
5.0Vref
S
1.0mA
tSoft−Start 3600C in F
Where: 0 ≤ VClamp ≤ 1.0 V
+
−
−
Osc
3(5)
1(1)
VClamp =
+
5(8)
1.0V
R1
5.0Vref
Q1
VClamp
EA
RA + 2RB
Vin
7(12)
5.0Vref
Dmax =
5(9)
To
Additional
UCX84XA’s
RB
Figure 22. External Duty Cycle Clamp and
Multi Unit Synchronization
Figure 21. External Clock Synchronization
4(7)
2R
R
EA
1
1(1)
8(14)
+
4(7)
5.0k MC1455
C
R
4
8
Osc
External
Sync
Input
8(14)
RA
R
RS
1/4 W
Power Ground
To Input Source
Return
Where: 0 ≤ VClamp ≤ 1.0 V
1−
VC
3VClamp
C
R1 R2
R1 + R2
Figure 25. Adjustable Buffered Reduction of
Clamp Level with Soft−Start
Virtually lossless current sensing can be achieved with the implementation of a
SENSEFET power switch. For proper operation during over current conditions, a
reduction of the Ipk(max) clamp level must be implemented. Refer to Figures 23 and 25.
Figure 26. Current Sensing Power MOSFET
http://onsemi.com
12
UC3842A, UC3843A, UC2842A, UC2843A
VCC
VCC
Vin
7(12)
+
−
5.0Vref
+
+
−
5.0Vref
+
−
+
−
7(11)
+
−
+
−
+
7(11)
−
+
Q1
6(10)
6(10)
S
Rg
−
Q1
−
Vin
7(12)
S
Q
5(8)
R
Comp/Latch
Q
R
Comp/Latch
−
+
R
5(8)
3(5)
3(5)
C
RS
RS
Series gate resistor Rg will damp any high frequency parasitic oscillations
caused by the MOSFET input capacitance and any series wiring inductance
in the gate−source circuit.
The addition of the RC filter will eliminate instability caused by the leading
edge spike on the current waveform.
Figure 27. Current Waveform Spike Suppression
IB
Figure 28. MOSFET Parasitic Oscillations
Vin
+
VCC
Vin
7(12)
0
Base
Charge
Removal
−
5.0Vref
C1
+
Q1
+
−
Isolation
Boundary
+
−
+
−
+
0
−
−
6(1)
6(1)
5(8)
S
Q
−
R
+
Comp/Latch
3(5)
50% DC
Ipk =
5(8)
R
RS
ÉÉ
É
É
É ÉÉ
VGS Waveforms
Q1
7(11)
3(5) C
NS
RS
+
0
−
25% DC
V(pin 1) − 1.4
3 RS
Np
The totem−pole output can furnish negative base current for enhanced
transistor turn−off, with the addition of capacitor C1.
Figure 29. Bipolar Transistor Drive
Figure 30. Isolated MOSFET Drive
From VO
2.5V
Ri
8(14)
R
Rd
Bias
2(3)
CI
+
1.0mA
+
−
2R
R
EA
Rf
R
1(1)
Osc
+
−
2(3)
5(9)
+
4(7)
1.0mA
EA
Error Amp compensation circuit for stabilizing any current−mode topology except
for boost and flyback converters operating with continuous inductor current.
2R
R
From VO
2.5V
1(1)
MCR
101
2N
3905
Rp
5(9)
2N
3903
Cp
2(3)
Ri
Rd
CI
Rf
+
−
+
1.0mA
EA
2R
R
1(1)
5(9)
The MCR101 SCR must be selected for a holding of less than 0.5 mA at TA(min).
The simple two transistor circuit can be used in place of the SCR as shown. All
resistors are 10 k.
Error Amp compensation circuit for stabilizing current−mode boost and flyback
topologies operating with continuous inductor current.
Figure 31. Latched Shutdown
Figure 32. Error Amplifier Compensation
http://onsemi.com
13
NP
NS
UC3842A, UC3843A, UC2842A, UC2843A
VCC
Vin
7(12)
8(14)
+
−
5.0Vref
R
RT
Bias
MPS3904
R
RSlope
−
+
−
7(11)
−
4(7)
Osc
From VO
CT
Ri
2(3)
Rd
+
+
Cf
+
6(10)
−m
1.0mA
+
−
S
−
+
2R
R
EA
Rf
R
Q
5(8)
Comp/Latch
1.0V
3(5)
m
1(1)
RS
−3.0 m
5(9)
The buffered oscillator ramp can be resistively summed with either the voltage feedback or current sense inputs to provide slope compensation.
Figure 33. Slope Compensation
4.7
+
MDA
202
3300pF
4.7k
250
T1
1N4935
+
68
+
+
−
5.0Vref
0.01
Bias
+
Osc
2.7k
6(10)
18k
150k
12V/0.3A
+
−12V/0.3A
L3
1N4937
22
+
+
−
10
+
MUR110
680pF
7(11)
4(7)
4700pF
+
+
+
−
5.0V/4.0A
±12V RTN
1000
1N4937
10k
L2
10
47
100
8(14)
100pF
+
5.0V RTN
+
1000
7(12)
4.7k
1000
MUR110
1N4935
2(3)
+
2200
56k
115Va
c
L1
MBR1635
S
−
+
EA
Q
R
5(8)
Comp/Latch
3(5)
MTP
4N50
1.0k
470pF
1(1)
0.5
5(9)
Figure 34. 27 Watt Off−Line Flyback Regulator
Test
Conditions
L1 − 15 H at 5.0 A, Coilcraft Z7156.
L2, L3 − 25 H at 1.0 A, Coilcraft Z7157.
T1 − Primary: 45 Turns # 26 AWG
T1 − Secondary ± 12 V: 9 Turns # 30 AWG
T1 − (2 strands) Bifiliar Wound
T1 − Secondary 5.0 V: 4 Turns (six strands)
T1 − #26 Hexfiliar Wound
T1 − Secondary Feedback: 10 Turns #30 AWG
T1 − (2 strands) Bifiliar Wound
T1 − Core: Ferroxcube EC35−3C8
T1 − Bobbin: Ferroxcube EC35PCB1
T1 − Gap ≈ 0.01" for a primary inductance of 1.0 mH
Results
Line Regulation: 5.0 V
± 12 V
Vin = 95 Vac to 130 Vac
= 50 mV or ± 0.5%
= 24 mV or ± 0.1%
Load Regulation: 5.0 V
± 12 V
Vin = 115 Vac, Iout = 1.0 A to 4.0 A
Vin = 115 Vac, Iout = 100 mA to 300 mA
= 300 mV or ± 3.0%
= 60 mV or ± 0.25%
Output Ripple:
Vin = 115 Vac
40 mVpp
80 mVpp
Vin = 115 Vac
70%
Efficiency
5.0 V
± 12 V
All outputs are at nominal load currents, unless otherwise noted.
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14
UC3842A, UC3843A, UC2842A, UC2843A
ORDERING INFORMATION
Device
Operating Temperature Range
UC3842AN
Package
Shipping †
PDIP−8
UC3842ANG
PDIP−8
(Pb−Free)
UC3842AN2
PDIP−8
50 Units / Rail
UC3842AN2G
PDIP−8
(Pb−Free)
UC3842AD
SOIC−14
55 Units / Rail
UC3842ADG
SOIC−14
(Pb−Free)
55 Units / Rail
UC3842ADR2
SOIC−14
2500 / Tape & Reel
UC3842ADR2G
SOIC−14
(Pb−Free)
2500 / Tape & Reel
UC3843AN
PDIP−8
UC3843ANG
PDIP−8
(Pb−Free)
UC3843AN2
PDIP−8
UC3843AN2G
TA = 0° to +70°C
50 Units / Rail
PDIP−8
(Pb−Free)
UC3843AD
SOIC−14
55 Units / Rail
UC3843ADG
SOIC−14
(Pb−Free)
55 Units / Rail
UC3843ADR2
SOIC−14
2500 / Tape & Reel
UC3843ADR2G
SOIC−14
(Pb−Free)
2500 / Tape & Reel
SOIC−8
98 Units / Rail
UC3843AD1G
SOIC−8
(Pb−Free)
98 Units / Rail
UC3843AD1R2
SOIC−8
UC3843AD1
UC3843AD1R2G
SOIC−8
(Pb−Free)
UC3843AD2R2
SOIC−14
UC3843AD2R2G
SOIC−14
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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15
UC3842A, UC3843A, UC2842A, UC2843A
ORDERING INFORMATION
Package
Shipping †
PDIP−8
50 Units / Rail
UC2842ANG
PDIP−8
(Pb−Free)
50 Units / Rail
UC2842AD
SOIC−14
55 Units / Rail
UC2842ADG
SOIC−14
(Pb−Free)
55 Units / Rail
UC2842ADR2
SOIC−14
2500 / Tape & Reel
UC2842ADR2G
SOIC−14
(Pb−Free)
2500 / Tape & Reel
PDIP−8
50 Units / Rail
PDIP−8
(Pb−Free)
50 Units / Rail
SOIC−14
55 Units / Rail
UC2843ADG
SOIC−14
(Pb−Free)
55 Units / Rail
UC2843ADR2
SOIC−14
2500 / Tape & Reel
UC2843ADR2G
SOIC−14
(Pb−Free)
2500 / Tape & Reel
SOIC−8
98 Units / Rail
UC2843AD1G
SOIC−8
(Pb−Free)
98 Units / Rail
UC2843AD1R2
SOIC−8
2500 / Tape & Reel
SOIC−8
(Pb−Free)
2500 / Tape & Reel
Device
Operating Temperature Range
UC2842AN
UC2843AN
UC2843ANG
TA = −25° to +85°C
UC2843AD
UC2843AD1
UC2843AD1R2G
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
MARKING DIAGRAMS
PDIP−8
N SUFFIX
CASE 626
8
SOIC−14
D SUFFIX
CASE 751A
14
UCx84xAN
AWL
YYWWG
SOIC−8
D1 SUFFIX
CASE 751
8
x843
ALYW
G
UCx84xADG
AWLYWW
1
1
1
x
A
WL, L
YY, Y
WW, W
G or G
= 2 or 3
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
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16
UC3842A, UC3843A, UC2842A, UC2843A
PACKAGE DIMENSIONS
PDIP−8
N SUFFIX
CASE 626−05
ISSUE L
8
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5
−B−
1
4
DIM
A
B
C
D
F
G
H
J
K
L
M
N
F
−A−
NOTE 2
L
C
J
−T−
MILLIMETERS
MIN
MAX
9.40
10.16
6.10
6.60
3.94
4.45
0.38
0.51
1.02
1.78
2.54 BSC
0.76
1.27
0.20
0.30
2.92
3.43
7.62 BSC
−−−
10 _
0.76
1.01
INCHES
MIN
MAX
0.370
0.400
0.240
0.260
0.155
0.175
0.015
0.020
0.040
0.070
0.100 BSC
0.030
0.050
0.008
0.012
0.115
0.135
0.300 BSC
−−−
10_
0.030
0.040
N
SEATING
PLANE
D
M
K
G
H
0.13 (0.005)
M
T A
M
B
M
SOIC−14
D SUFFIX
CASE 751A−03
ISSUE G
−A−
14
8
−B−
P 7 PL
0.25 (0.010)
M
B
M
7
1
G
F
R X 45 _
C
−T−
SEATING
PLANE
D 14 PL
0.25 (0.010)
M
T B
J
M
K
S
A
S
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17
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337 0.344
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0_
7_
0.228 0.244
0.010 0.019
UC3842A, UC3843A, UC2842A, UC2843A
PACKAGE DIMENSIONS
SOIC−8
D1 SUFFIX
CASE 751−07
ISSUE AG
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
−X−
A
8
5
S
B
1
0.25 (0.010)
M
Y
M
4
K
−Y−
G
C
N
X 45 _
DIM
A
B
C
D
G
H
J
K
M
N
S
SEATING
PLANE
−Z−
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SENSEFET is a trademark of Semiconductor Components Industries, LLC.
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UC3842A/D