HI-524 ® Data Sheet April 2002 4-Channel Wideband and Video Multiplexer Features • Crosstalk (10MHz) . . . . . . . . . . . . . . . . . . . . . . . .< -60dB The HI-524 is a 4-Channel CMOS analog multiplexer designed to process single-ended signals with bandwidths up to 10MHz. The chip includes a 1 of 4 decoder for channel selection and an enable input to inhibit all channels (chip select). Three CMOS transmission gates are used in each channel, as compared to the single gate in more conventional CMOS multiplexers. This provides a double barrier to the unwanted coupling of signals from each input to the output. In addition, Dielectric Isolation (DI) processing helps to insure the Crosstalk is less than -60dB at 10MHz. The HI-524 is designed to operate into a wideband buffer amplifier such as the Intersil HA-2541. The multiplexer chip includes two “ON” switches in series, for use as a feedback element with the amplifier. This feedback resistance matches and tracks the channel ON resistance, to minimize the amplifier VOS and its variation with temperature. • Fast Access Time . . . . . . . . . . . . . . . . . . . . . . . . . 150ns • Fast Settling Time . . . . . . . . . . . . . . . . . . . . . . . . . 200ns • TTL Compatible Applications • Wideband Switching • Radar • TV Video • ECM Functional Diagram IN1 The HI-524 is well suited to the rapid switching of video and other wideband signals in telemetry, instrumentation, radar and video systems. SIG GND Ordering Information SIG GND PART NUMBER HI1-0524-5 TEMP. RANGE (oC) 0 to 75 FN3148.3 FB (IN) IN2 FB (OUT) OUTPUT IN3 PACKAGE 18 Ld CERDIP PKG. NO. F18.3 SIG GND IN4 Pinout HI-524 (CERDIP) TOP VIEW +V 1 SIG GND SIG GND 1 -15V SUP +15V GND 18 FB (IN) OUT 2 17 -V SIG GND 3 16 FB (OUT) SIG GND 4 15 SIG GND 1 OF 4 DECODER EN A0 A1 TRUTH TABLE A1 A0 EN ON CHANNEL 13 SIG GND X X L None IN3 7 12 IN1 L L H 1 (Note) SUPPLY GND 8 11 EN L H H 2 A1 9 10 A0 H L H 3 H H H 4 IN4 5 14 IN2 SIG GND 6 NOTE: Channel 1 is shown selected in the Functional Diagram. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved HI-524 Absolute Maximum Ratings Thermal Information V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33V Digital Input Voltage (VEN, VA) . . . . . . . . . . . . . . . . . . . . -6V to +6V Analog Signal (VIN, VOUT) . . . . . . . . . . . . . . . . (V-) -2V to (V+) +2V Either Supply to Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5V Thermal Resistance (Typical, Note 1) Operating Conditions θJA (oC/W) θJC (oC/W) CERDIP Package. . . . . . . . . . . . . . . . . 75 20 Maximum Junction Temperature Ceramic Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Storage Temperature . . . . . . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . 300oC Temperature Range HI-524-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications Supplies = +15V, -15V; VAH (Logic Level High) = 2.4V, VAL (Logic Level Low) = 0.5V; VEN = 2.4V, Unless Otherwise Specified PARAMETER TEST CONDITIONS -5 TEMP (oC) MIN TYP MAX UNITS DYNAMIC CHARACTERISTICS Access Time, tA Note 5 25 - 150 300 ns Break-Before-Make Delay, tOPEN Note 5 25 - 20 - ns Enable Delay (ON), tON (EN) RL = 500Ω 25 - 180 - ns Enable Delay (OFF), tOFF (EN) RL = 500Ω 25 - 180 - ns Settling Time (Note 5) To 0.1% 25 - 200 - ns To 0.01% 25 - 600 - ns Note 6 25 - -65 - dB Channel Input Capacitance, CS(OFF) 25 - 4 - pF Channel Output Capacitance, CD(OFF) 25 - 10 - pF Digital Input Capacitance, CA 25 - 5 - pF Input Low Threshold (TTL), VAL Full - - 0.8 V Input High Threshold (TTL), VAH Full 2.4 - - V Input Leakage Current (High), IAH Full - 0.05 1 µA Input Leakage Current (Low), IAL Full - - 25 µA Full -10 - +10 V 25 - 700 - Ω Full - - 1.5 kΩ 25 - 0.2 - nA Full - - 50 nA 25 - 0.2 - nA Full - - 50 nA 25 - 0.7 - nA Full - - 50 nA 25 - 8 - MHz Crosstalk DIGITAL INPUT SPECIFICATIONS ANALOG CHANNEL SPECIFICATIONS Analog Signal Range, VlN Note 2 On Resistance, rON Off Input Leakage Current, IS (OFF) Off Output Leakage Current, ID (OFF) On Channel Leakage Current, ID (ON) -3dB Bandwidth Note 3 Note 3 Note 3 Note 4 2 HI-524 Electrical Specifications Supplies = +15V, -15V; VAH (Logic Level High) = 2.4V, VAL (Logic Level Low) = 0.5V; VEN = 2.4V, Unless Otherwise Specified (Continued) TEST CONDITIONS PARAMETER -5 TEMP (oC) MIN TYP MAX UNITS Full - - 750 mW POWER SUPPLY CHARACTERISTICS Power Dissipation, PD Current, I+ Note 7 Full - - 25 mA Current, I- Note 7 Full - - 25 mA NOTES: 2. VlN = 0V; lOUT = 100µA (See Test Circuit section). 3. VO = ±10V; VIN = ±10V. (See Test Circuit section). 4. MUX output is buffered with HA-5033 amplifier. ± 5. 6V Step, ±3V to 3V, See Test Circuit section. 6. VIN = 10MHz, 3VP-P on one channel, with any other channel selected. (Worst case is channel 3 selected with input on channel 4.) MUX output is buffered with HA-2541 as shown in Applications section. Terminate all channels with 75Ω. 7. Supply currents vary less than 0.5mA for switching rates from DC to 2MHz. Test Circuits and Waveforms TA = 25oC, VSUPPLY = ±15V, VAH = 2.4V, VAL = 0.8V, Unless Otherwise Specified IOUT 100µA V2 IN OUT VIN rON = V2 100µA FIGURE 1A. TEST CIRCUIT 1,000 1,000 VIN = 0V 125oC 900 900 25oC rON (Ω) rON (Ω) 800 700 800 600 -55oC 500 400 -10 700 -8 -6 -4 -2 0 2 4 6 8 10 9 FIGURE 1B. ON RESISTANCE vs ANALOG INPUT VOLTAGE 11 12 13 14 FIGURE 1C. ON RESISTANCE vs SUPPLY VOLTAGE FIGURE 1. ON RESISTANCE 3 10 SUPPLY VOLTAGE (±V) VIN (V) 15 HI-524 TA = 25oC, VSUPPLY = ±15V, VAH = 2.4V, VAL = 0.8V, Unless Otherwise Specified ID(ON) 1.0 0.8V EN OUT IS(OFF) A ID(OFF) ±10V 0.1 0 25 50 75 100 125 ID(OFF) ± LEAKAGE CURRENT (nA) Test Circuits and Waveforms 10V 150 TEMPERATURE (oC) FIGURE 2A. LEAKAGE CURRENT vs TEMPERATURE FIGURE 2B. ID(OFF) TEST CIRCUIT (NOTE 8) OUT IS(OFF) A OUT 0.8V EN A0 ± ±10V 10V A EN A1 ID(ON) ±10V 10V ± +2.4V FIGURE 2C. IS(OFF) TEST CIRCUIT (NOTE 8) FIGURE 2D. ID(ON) TEST CIRCUIT (NOTE 8) FIGURE 2. LEAKAGE CURRENTS HA-524 ±3V IN1 VAH = 2.4V HA-2541 IN2 2 18 IN3 16 + OUTPUT 1.6V ADDRESS DRIVE (VA) 20pF (NOTE 10) VAL = 0.8V 75Ω +3V ACCESS TIME, tA SETTLING TIME, tS IN4 3V ± A0 A1 EN 5V VA HA-2541 OUTPUT 10% -3V ± 0.1% OF FULL SCALE (OR ±0.01%) 50Ω FIGURE 3A. TEST CIRCUIT FIGURE 3B. MEASUREMENT POINTS FIGURE 3. SETTLING TIME, ACCESS TIME, BREAK-BEFORE-MAKE DELAY (NOTE 9) NOTES: 8. Two measurements per channel: ±10V and 10V. (Two measurements per device for ID(OFF) ±10V and 10V.) 9. The Break-Before-Make test requires inputs 1 and 4 at the same voltage. 10. Capacitor value may be selected to optimize AC performance. 4 HI-524 Test Circuits and Waveforms TA = 25oC, VSUPPLY = ±15V, VAH = 2.4V, VAL = 0.8V, Unless Otherwise Specified 5V/DIV. VA INPUT S1 ON S4 ON 1V/DIV. OUTPUT 50ns/DIV. FIGURE 4. ACCESS TIME WAVEFORMS Application Information Often it is desirable to buffer the Hl-524 output, to avoid loading errors due to the channel “ON” resistance: HA-524 CH1 12 75Ω CH2 14 2 18 HA-2541 + - BUFFERED OUTPUT 75Ω 20pF (NOTE) CH3 7 16 75Ω CH4 5 75Ω NOTE: Capacitor value may be selected to optimize AC performance. FIGURE 5. The buffer amplifier should offer sufficient bandwidth and slew rate to avoid degradation of the anticipated signals. For video switching, the HA-5033 and HA-2542 offer good performance plus ±100mA output current for driving coaxial cables. For general wideband applications, the HA-2541 offers the convenience of unity gain stability plus 90ns settling (to ±0.1%) and ±10V output swing. Also, the Hl-524 includes a feedback resistance for use with the HA-2541. This resistance matches and tracks the channel “ON” resistance, to minimize offset voltage due to the buffer's bias currents. 5 Note that the on-chip feedback element between pins 16 and 18 includes two switches in series, to simulate a channel resistance. These switches open for VEN = Low. This allows two or more Hl-524s to operate into one HA-2541, with their feedback elements connected in parallel. Thus, only the selected multiplexer provides feedback, and the amplifier remains stable. All Hl-524 pins labeled ‘SlG GND’ (pins 3, 4, 6, 13, 15) should be externally connected to signal ground for best crosstalk performance. Bypass capacitors (0.1µF to 1µF) are recommended from each HI-524 supply pin to power ground (pins 1 and 17 to pin 8). Locate the buffer amplifier near the Hl-524 so the two capacitors may bypass both devices. If an analog input 1V or greater is present when supplies are off, a low resistance is seen from that input to a supply line. (For example, the resistance is approximately 160Ω for an input of -3V.) Current flow may be blocked by a diode in each supply line, or limited by a resistor in series with each channel. The best solution, of course, is to arrange that no digital or analog inputs are present when the power supplies are off. HI-524 Die Characteristics DIE DIMENSIONS: PASSIVATION: 2250µm x 3720µm x 485µm Type: Nitride Over Silox Nitride Thickness: 3.5kÅ ±1kÅ Silox Thickness: 12kÅ ±2kÅ METALLIZATION: Type: CuAl Thickness: 16kÅ ±2kÅ WORST CASE CURRENT DENSITY: 1.58 x 105 A/cm2 Metallization Mask Layout HI-524 EN AO SUPPLY GND A1 IN1 IN3 SIG GND SIG GND IN2 IN4 SIG GND SIG GND FB (OUT) SIG GND -V FB (IN) +V OUT All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 6