NCP3163 3.4 A, Step−Up/Down/ Inverting 50−300 kHz Switching Regulator The NCP3163 Series is a performance enhancement to the popular MC33163 and MC34163 monolithic DC−DC converters. These devices consist of an internal temperature compensated reference, comparator, controlled duty cycle oscillator with an active current limit circuit, driver and high current output switch. This controller was specifically designed to be incorporated in step−down, step−up, or voltage−inverting applications with a minimum number of external components. The NCP3163 comes in an exposed pad package which can greatly increase the power dissipation of the built in power switch. Features • • • • • • • • • • • • • Output Switch Current in Excess of 3.0 A 3.4 A Peak Switch Current Frequency is Adjustable from 50 kHz to 300 kHz Operation from 2.5 V to 40 V Input Externally Adjustable Operating Frequency Precision 2% Reference for Accurate Output Voltage Control Driver with Bootstrap Capability for Increased Efficiency Cycle−by−Cycle Current Limiting Internal Thermal Shutdown Protection Low Voltage Indicator Output for Direct Microprocessor Interface Exposed Pad Power Package Low Standby Current This is a Pb−Free Device 8 − Current Limit 9 + 10 7 6 16 1 SOIC−16W EXPOSED PAD PW SUFFIX CASE 751AG 18 1 NCP3163xPW AWLYYWWG 1 1 18−LEAD DFN MN SUFFIX CASE 505 18 NCP3163x AWLYYWW G G NCP3163x = Specific Device Code A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb−Free Package G = Pb−Free Package See detailed ordering and shipping information in the package dimensions section on page 18 of this data sheet. 11 Oscillator R 5 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 12 Q Thermal 4 16 ORDERING INFORMATION VCC Cin MARKING DIAGRAMS (Note: Microdot may be in either location) + Vin http://onsemi.com S 13 VCC 14 3 + + − 2 1 LVI 15 + + − 16 VCC (Bottom View) Figure 1. Typical Buck Application Circuit © Semiconductor Components Industries, LLC, 2006 May, 2006 − Rev. 1 CO 1 Vout + Publication Order Number: NCP3163/D NCP3163 IPKsense 0.25 V 8 − Current Limit 9 RSC 10 7 VCC VCC Timing Capacitor 6 Switch Collector Q2 R 5 RDT 12 Q Gnd Thermal 4 11 Q1 Oscillator CT Shutdown Driver Collector + 60 S Latch 13 VCC Voltage Feedback 1 14 3 Voltage Feedback 2 2 LVI Output 1 Switch Emitter 2.0 mA 45 k + + − LVI + + − 15 Feedback Comparator 1.25 V 15 k 7.0 V 1.125 V 16 Bootstrap Input VCC + (Bottom View) − = Sink Only Positive True Logic Figure 2. Representative Block Diagram PIN FUNCTION DESCRIPTION SOIC16 DFN18 PIN NAME DESCRIPTION 1 15 LVI Output 2 16 Voltage Feedback 2 Connecting this pin to a resistor divider off of the output will regulate the application according to the Vout design equation in Figure 22. 3 17 Voltage Feedback 1 Connecting this pin directly to the output will regulate the device to 5.05 V. 4 18 GND 6 1 Timing Capacitor 7 3 VCC 8 4 Ipk Sense 9 5 Drive Collector 10,11 6,7,8,9 Switch Collector 14,15 10,11,12,13 Switch Emitter Internal switch transistor emitter 16 14 Bootstrap Input Connect this pin to VCC for operation at low VCC levels. For some topologies, a series resistor and capacitor can be utilized to improve the converter efficiency. 5,12,13 2 No Connect Exposed Pad Exposed Pad Exposed Pad This pin will sink current when FB1 and FB2 are less than the LVI threshold (Vth). Ground pin for all internal circuits and power switch. Connect a capacitor to this pin to set the frequency. The addition of a parallel resistor will decrease the maximum duty cycle and increase the frequency. Power pin for the IC. When (VCC−VIPKsense) > 250 mV the circuit resets the output driver on a pulse by pulse basis. Voltage driver collector Internal switch transistor collector These pins have no connection. The exposed pad beneath the package must be connected to GND (pin 4). Additionally, using proper layout techniques, the exposed pad can greatly enhance the power dissipation capabilities of the NCP3163. http://onsemi.com 2 NCP3163 MAXIMUM RATINGS (Note 1) Rating Symbol Value Unit VCC 0 to +40 V VCSW −1.0 to +40 V Switch Emitter Voltage Range VESW −2.0 to +40 V Switch Collector to Emitter Voltage VCESW +40 V Switch Current ISW 3.4 A Driver Collector Voltage (Pin 8) VCC −1.0 to +40 V Driver Collector Current (Pin 8) ICC 150 mA Bootstrap Input Current Range IBST −100 to +100 mA VIPKSNS (VCC − 7.0) to (VCC + 1.0) V Vin −1.0 to +7.0 V Low Voltage Indicator Output Voltage Range VCLVI −1.0 to +40 V Low Voltage Indicator Output Sink Current ICLVI 10 mA RqJC RqJA 15 56 Tstg −65 to +150 °C TJmax +150 °C Power Supply Voltage Switch Collector Voltage Range Current Sense Input Voltage Range Feedback and Timing Capacitor Input Voltage Range Power Dissipation and Thermal Characteristics °C/W Thermal Characteristics Thermal Resistance, Junction−to−Case Thermal Resistance, Junction−to−Air Storage Temperature Range Maximum Junction Temperature Operating Ambient Temperature (Note 3) NCP3163PW NCP3163BPW °C TA 0 to +70 −40 to +85 Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. This device series contains ESD protection and exceeds the following tests: Human Body Model 1500 V per MIL−STD−883, Method 3015. Machine Model Method 150 V. 2. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78. 3. Maximum package power dissipation limits must be observed. Maximum Junction Temperature must not be exceeded. 4. The pins which are not defined may not be loaded by external signals. PIN CONNECTIONS LVI Output Voltage Feedback 2 1 16 2 15 3 14 4 GND N/C 5 6 Timing Capacitor 7 VCC 8 Ipk Sense 13 Voltage Feedback 1 12 Bootstrap Input Timing Capacitor N/C VCC Ipk Sense Driver Collector Switch Collector Switch Collector Switch Collector Switch Collector Switch Emitter N/C 11 10 Switch Collector 9 Driver Collector 1 2 3 4 5 6 7 8 9 18 GND EP Flag 17 16 15 14 13 12 11 10 GND Voltage Feedback 1 Voltage Feedback 2 LVI Output Bootstrap Input Switch Emitter Switch Emitter Switch Emitter Switch Emitter (Top View) Note: Pin 18 must be tied to EP Flag on PCB http://onsemi.com 3 NCP3163 ELECTRICAL CHARACTERISTICS (VCC = 15 V, Pin 16 = VCC, CT = 270 pF, RT = 15 kW, for typical values TA = 25°C, for min/max values TA is the operating ambient temperature range that applies (Note 5), unless otherwise noted.) Characteristic Symbol Frequency TA = 25°C, VCC = 15 V Total Variation over VCC = 2.5 V to 40 V and Temperature (Note 5) fOSC Min Typ Max 225 212 250 250 275 288 Unit OSCILLATOR kHz Ichg − 225 − mA Idischg − 25 − mA Ichg/Idischg 8.0 9.0 10 − Sawtooth Peak Voltage VOSC(P) − 1.25 − V Sawtooth Valley Voltage VOSC(V) − 0.55 − V 4.9 4.85 5.05 − 5.2 5.25 − 0.008 0.03 − 100 200 1.225 1.213 1.25 − 1.275 1.287 − 0.008 0.03 − 0.4 − 0.4 − 230 250 − − 270 − 1.0 20 − − 0.6 1.0 1.0 1.4 IC(off) − 0.02 100 mA Isource(DRV) 0.5 2.0 4.0 mA VZ VCC + 6.0 VCC + 7.0 VCC + 9.0 V Input Threshold (VFB2 Increasing) Vth 1.07 1.125 1.18 V Input Hysteresis (VFB2 Decreasing) VH − 15 − mV Output Sink Saturation Voltage (Isink = 2.0 mA) VOL(LVI) − 0.15 0.4 V Output Off−State Leakage Current (VOH = 15 V) IOH − 0.01 5.0 mA ICC − 6.0 10 mA Charge Current Discharge Current Charge to Discharge Current Ratio FEEDBACK COMPARATOR 1 Threshold Voltage TA = 25°C Total Variation over VCC = 2.5 V to 40 V and Temperature (Note 5) Threshold Voltage Line Regulation (VCC = 2.5 V to 40 V, TA = 25°C) Vth(FB1) V REGline(FB1) Input Bias Current (VFB1 = 5.05 V) IIB(FB1) %/V mA FEEDBACK COMPARATOR 2 Threshold Voltage TA = 25°C, VCC = 15 V Total Variation over VCC = 2.5 V to 40 V and Temperature (Note 5) Threshold Voltage Line Regulation (VCC = 2.5 V to 40 V, TA = 25°C) Vth(FB2) V REGline(FB1) Input Bias Current (VFB2 = 1.25 V) IIB(FB2) %/V mA CURRENT LIMIT COMPARATOR Threshold Voltage TA = 25°C Total Variation over VCC = 2.5 V to 40 V, and Temperature (Note 5) Vth(Sense) Input Bias Current (VIpk (Sense) = 15 V) IIB(Sense) mV mA DRIVER AND OUTPUT SWITCH (Note 6) Saturation Voltage (ISW = 2.5 A, Pins 14, 15 grounded) Non−Darlington Connection (RPin 9 = 110 W to VCC, ISW/IDRV ≈ 20) Darlington Connection (Pins 9, 10, 11 connected) (Note 7) Collector Off−State Leakage Current (VCE = 40 V) Bootstrap Input Current Source (VBS = VCC + 5.0 V) VCE(sat) Bootstrap Input Zener Clamp Voltage (IZ = 25 mA) V LOW VOLTAGE INDICATOR TOTAL DEVICE Standby Supply Current (VCC = 2.5 V to 40 V, Pin 8 = VCC, Pins 6, 14, 15 = GND, remaining pins open) 5. Maximum package power dissipation limits must be observed. 6. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. 7. Tlow = 0°C for NCP3163 Thigh = + 70°C for NCP3163 = − 40°C for NCP3163B = + 85°C for NCP3163B http://onsemi.com 4 NCP3163 300 VCC = 15 V TA = 25°C FREQUENCY (kHz) 250 200 Rt = 15 kW 150 Rt = open 100 50 0 100 200 300 400 500 CT, TIMER CAPACITANCE (pF) 600 700 Δ f OSC, OSCILLATOR FREQUENCY CHANGE (%) Δ f OSC, OSCILLATOR FREQUENCY CHANGE (%) Figure 3. Oscillator Frequency vs. Timer Capacitance (CT) 2.0 VCC = 15 V CT = 620 pF 0 −2.0 −4.0 −6.0 −55 −25 0 25 50 75 TA, AMBIENT TEMPERATURE (°C) 100 125 IIB , INPUT BIAS CURRENT (A) μ VCC = 15 V VFB1 = 5.05 V 120 100 80 −25 0 25 50 75 TA, AMBIENT TEMPERATURE (°C) 100 0 −2.0 −4.0 −6.0 −8.0 −10 −50 −25 0 25 50 TEMPERATURE (°C) 75 100 125 Figure 5. Oscillator Frequency Change vs. Temperature when CT and RT are connected to Pin 6 140 60 −55 VCC = 15 V CT = 230 pF RT = 20 kW 2.0 V th(FB2), COMPARATOR 2 THRESHOLD VOLTAGE (mV) Figure 4. Oscillator Frequency Change vs. Temperature when only CT is connected to Pin 6 4.0 125 Figure 6. Feedback Comparator 1 Input Bias Current vs. Temperature 1300 1260 Vth Max = 1275 mV Vth Typ = 1250 mV 1240 Vth Min = 1225 mV 1220 1200 −55 http://onsemi.com 5 VCC = 15 V 1280 −25 0 25 50 75 TA, AMBIENT TEMPERATURE (°C) 100 Figure 7. Feedback Comparator 2 Threshold Voltage vs. Temperature 125 V Z, BOOTSTRAP INPUT ZENER CLAMP VOLTAGE (V I source (DRV), BOOTSTRAP INPUT CURRENT SOURCE (mA NCP3163 2.8 VCC = 15 V Pin 16 = VCC + 5.0 V 2.4 2.0 1.6 1.2 −55 −25 0 25 50 75 TA, AMBIENT TEMPERATURE (°C) 100 125 IZ = 25 mA 7.4 7.2 7.0 6.8 −55 Figure 8. Bootstrap Input Current Source vs. Temperature −0.8 VCE (sat), SINK SATURATION (V) −0.4 Darlington Configuration Emitter Sourcing Current to GND Pins 7, 8, 10, 11 = VCC Pins 4, 5, 12, 13 = GND TA = 25°C, (Note 2) 100 125 Bootstrapped, Pin 16 = VCC + 5.0 V −1.2 −1.6 Non−Bootstrapped, Pin 16 = VCC 0 0.8 2.4 1.6 IE, EMITTER CURRENT (A) 0.8 Grounded Emitter Configuration Collector Sinking Current From VCC Pins 7, 8 = VCC = 15 V Pins 4, 5, 12, 13, 14, 15 = GND TA = 25°C, (Note 2) Saturated Switch, RPin9 = 110 W to VCC 0.6 0.4 0.2 0 3.2 Darlington, Pins 9, 10, 11 Connected 1.0 GND 0 Figure 10. Output Switch Source Saturation vs. Emitter Current −0.4 V OL (LVI) , OUTPUT SATURATION VOLTAGE (V) GND IC = 10 mA −0.8 IC = 10 mA −1.2 VCC = 15 V Pins 7, 8, 9, 10, 16 = VCC Pins 4, 6 = GND Pin 14 Driven Negative −1.6 −2.0 −55 −25 0 25 50 75 TA, AMBIENT TEMPERATURE (°C) 100 0.8 1.6 2.4 IC, COLLECTOR CURRENT (A) 3.2 Figure 11. Output Switch Sink Saturation vs. Collector Current 0 V E , EMITTER VOLTAGE (V) 0 25 50 75 TA, AMBIENT TEMPERATURE (°C) 1.2 VCC −2.0 −25 Figure 9. Bootstrap Input Zener Clamp Voltage vs. Temperature 0 VCE (sat), SOURCE SATURATION (V) 7.6 125 Figure 12. Output Switch Negative Emitter Voltage vs. Temperature 0.5 VCC=5 V TA=25°C 0.4 0.3 0.2 0.1 0 0 2.0 4.0 6.0 Isink, OUTPUT SINK CURRENT (mA) Figure 13. Low Voltage Indicator Output Sink Saturation Voltage vs. Sink Current http://onsemi.com 6 8.0 254 VCC = 15 V IIB (Sense), INPUT BIAS CURRENT (μ A) V th (Ipk Sense), THRESHOLD VOLTAGE (mV NCP3163 252 250 248 246 −55 −25 0 25 50 75 TA, AMBIENT TEMPERATURE (°C) 100 125 1.6 1.2 1.0 0.8 0.6 −55 Figure 14. Current Limit Comparator Threshold Voltage vs. Temperature 0 25 50 75 TA, AMBIENT TEMPERATURE (°C) 100 125 I CC, SUPPLY CURRENT (mA) 7.2 6.0 4.0 Pins 7, 8, 16 = VCC Pins 4, 6, 14 = GND Remaining Pins Open TA = 25°C 2.0 0 10 20 30 VCC, SUPPLY VOLTAGE (V) VCC = 15 V Pins 7, 8, 16 = VCC Pins 4, 6, 14 = GND Remaining Pins Open 6.4 5.6 4.8 4.0 −55 40 −25 Figure 16. Standby Supply Current vs. Supply Voltage V CC(min) , MINIMUM OPERATING SUPPLY VOLTAGE (V) I CC, SUPPLY CURRENT (mA) −25 Figure 15. Current Limit Comparator Input Bias Current vs. Temperature 8.0 0 VCC = 15 V VIpk (Sense) = 15 V 1.4 CT = 620 pF Pins 7,8 = VCC Pins 4, 14 = GND Pin 9 = 1.0 kW to 15 V Pin 10 = 100 W to 15 V 2.6 1.8 Pin 16 Open Pin 16 = VCC 1.4 1.0 −55 −25 0 100 Figure 17. Standby Supply Current vs. Temperature 3.0 2.2 0 25 50 75 TA, AMBIENT TEMPERATURE (°C) 25 50 75 100 TA, AMBIENT TEMPERATURE (°C) Figure 18. Minimum Operating Supply Voltage vs. Temperature http://onsemi.com 7 125 125 NCP3163 INTRODUCTION oscillator cycle, a partial cycle plus a complete cycle, multiple cycles, or a partial cycle plus multiple cycles. The NCP3163 is a monolithic power switching regulator optimized for DC−to−DC converter applications. The combination of its features enables the system designer to directly implement step−up, step−down, and voltage− inverting converters with a minimum number of external components. Potential applications include cost sensitive consumer products as well as equipment for the automotive, computer, and industrial markets. A representative block diagram is shown in Figure 2. Oscillator The oscillator frequency and on−time of the output switch are programmed by the value selected for timing capacitor CT. Capacitor CT is charged and discharged by a 9 to 1 ratio internal current source and sink, generating a negative going sawtooth waveform at Pin 6. As CT charges, an internal pulse is generated at the oscillator output. This pulse is connected to the NOR gate center input, preventing output switch conduction, and to the AND gate upper input, allowing the latch to be reset if the comparator output is low. Thus, the output switch is always disabled during ramp−up and can be enabled by the comparator output only at the start of ramp−down. The oscillator peak and valley thresholds are 1.25 V and 0.55 V, respectively, with a charge current of 225 mA and a discharge current of 25 mA, yielding a maximum on−time duty cycle of 90%. A reduction of the maximum duty cycle may be required for specific converter configurations. This can be accomplished with the addition of an external deadtime resistor (RDT) placed across CT. The resistor increases the discharge current which reduces the on−time of the output switch. The converter output can be inhibited by clamping CT to ground with an external NPN small−signal transistor. To calculate the frequency when only CT is connected to Pin 6, use the equations found in Figure 22. When RT is also used, the frequency and maximum duty cycle can be calculated with the NCP3163 design tool found at www.onsemi.com. OPERATING DESCRIPTION The NCP3163 operates as a fixed on−time, variable off−time voltage mode ripple regulator. In general, this mode of operation is somewhat analogous to a capacitor charge pump and does not require dominant pole loop compensation for converter stability. The Typical Operating Waveforms are shown in Figure 19. The output voltage waveform shown is for a step−down converter with the ripple and phasing exaggerated for clarity. During initial converter startup, the feedback comparator senses that the output voltage level is below nominal. This causes the output switch to turn on and off at a frequency and duty cycle controlled by the oscillator, thus pumping up the output filter capacitor. When the output voltage level reaches nominal, the feedback comparator sets the latch, immediately terminating switch conduction. The feedback comparator will inhibit the switch until the load current causes the output voltage to fall below nominal. Under these conditions, output switch conduction can be inhibited for a partial 1 Comparator Output 0 1.25 V Timing Capacitor CT 0.55 V t 9t 1 Oscillator Output 0 On Output Switch Off Nominal Output Voltage Level Output Voltage Startup Quiescent Operation Figure 19. Typical Operating Waveforms http://onsemi.com 8 NCP3163 Feedback and Low Voltage Indicator Comparators output state is controlled by the highest voltage applied to either of the two noninverting inputs. The Low Voltage Indicator (LVI) comparator is designed for use as a reset controller in microprocessor−based systems. The inverting input is internally biased at 1.125 V, which sets the noninverting input thresholds to 90% of nominal. The LVI comparator has 15 mV of hysteresis to prevent erratic reset operation. The Open Collector output is capable of sinking in excess of 6.0 mA (see Figure 13). An external resistor (RLVI) and capacitor (CDLY) can be used to program a reset delay time (tDLY) by the formula shown below, where Vth(MPU) is the microprocessor reset input threshold. Refer to Figure 20. Output voltage control is established by the Feedback comparator. The inverting input is internally biased at 1.25 V and is not pinned out. The converter output voltage is typically divided down with two external resistors and monitored by the high impedance noninverting input at Pin 2. The maximum input bias current is ±0.4 mA, which can cause an output voltage error that is equal to the product of the input bias current and the upper divider resistance value. For applications that require 5.0 V, the converter output can be directly connected to the noninverting input at Pin 3. The high impedance input, Pin 2, must be grounded to prevent noise pickup. The internal resistor divider is set for a nominal voltage of 5.05 V. The additional 50 mV compensates for a 1.0% voltage drop in the cable and connector from the converter output to the load. The Feedback comparator’s tDLY = RLVI ⋅ CDLY ⋅ In 3 Feedback Comparator + + − RLVI 1 CDLY Ǔ 14 2 Low Voltage Indicator Output ǒ 1 Vth(MPU) 1− Vout LVI + + − 1.25 V 15 16 1.125 V L CO (Bottom View) Vout Figure 20. Partial Application Schematic Showing Implementation of LVI Delay with RLVI and CDLY Current Limit Comparator, Latch and Thermal Shutdown 200 ns. The parasitic inductance associated with RSC and the circuit layout should be minimized. This will prevent unwanted voltage spikes that may falsely trip the Current Limit comparator. Internal thermal shutdown circuitry is provided to protect the IC in the event that the maximum junction temperature is exceeded. When activated, typically at 170°C, the Latch is forced into the “Set” state, disabling the Output Switch. This feature is provided to prevent catastrophic failures from accidental device overheating. It is not intended to be used as a replacement for proper heatsinking. With a voltage mode ripple converter operating under normal conditions, output switch conduction is initiated by the oscillator and terminated by the Voltage Feedback comparator. Abnormal operating conditions occur when the converter output is overloaded or when feedback voltage sensing is lost. Under these conditions, the Current Limit comparator will protect the Output Switch. The switch current is converted to a voltage by inserting a fractional ohm resistor, RSC, in series with VCC and output switch transistor Q2. The voltage drop across RSC is monitored by the Current Sense comparator. If the voltage drop exceeds 250 mV with respect to VCC, the comparator will set the latch and terminate output switch conduction on a cycle−by−cycle basis. This Comparator/Latch configuration ensures that the Output Switch has only a single on−time during a given oscillator cycle. The calculation for a value of RSC is: Driver and Output Switch To aid in system design flexibility and conversion efficiency, the driver current source and collector, and output switch collector and emitter are pinned out separately. This allows the designer the option of driving the output switch into saturation with a selected force gain or driving it near saturation when connected as a Darlington. The output switch has a typical current gain of 70 at 2.5 A and is designed to switch a maximum of 40 V collector to emitter, with up to 3.4 A peak collector current. The minimum value for RSC is: RSC + 0.25 V Ipk (Switch) Figures 14 and 15 show that the Current Sense comparator threshold is tightly controlled over temperature and has a typical input bias current of 1.0 mA. The propagation delay from the comparator input to the Output Switch is typically RSC(min) + 0.25 V + 0.0735 W 3.4 A http://onsemi.com 9 NCP3163 low ESR capacitors. The equation below is used to calculate a minimum value bootstrap capacitor based on a minimum zener voltage and an upper limit current source. When configured for step−down or voltage−inverting applications (see application notes at the end of this document) the inductor will forward bias the output rectifier when the switch turns off. Rectifiers with a high forward voltage drop or long turn−on delay time should not be used. If the emitter is allowed to go sufficiently negative, collector current will flow, causing additional device heating and reduced conversion efficiency. Figure 12 shows that by clamping the emitter to 0.5 V, the collector current will be in the range 10 mA over temperature. A 1N5822 or equivalent Schottky barrier rectifier is recommended to fulfill these requirements. A bootstrap input is provided to reduce the output switch saturation voltage in step−down and voltage−inverting converter applications. This input is connected through a series resistor and capacitor to the switch emitter and is used to raise the internal 2.0 mA bias current source above VCC. An internal zener limits the bootstrap input voltage to VCC +7.0 V. The capacitor’s equivalent series resistance must limit the zener current to less than 100 mA. An additional series resistor may be required when using tantalum or other t CB(min) + I Dt + 4.0 mA on + 0.001 ton DV 4.0 V Parametric operation of the NCP3163 is guaranteed over a supply voltage range of 2.5 V to 40 V. When operating below 3.0 V, the Bootstrap Input should be connected to VCC. Figure 18 shows that functional operation down to 1.7 V at room temperature is possible. Package The NCP3163 is contained in a heatsinkable 16−lead plastic package in which the die is mounted on a special heat tab copper alloy pad. This pad is designed to be soldered directly to a GND connection on the printed circuit board to improve thermal conduction. Since this pad directly contacts the substrate of the die, it is important that this pad be always soldered to GND, even if surface mount heat sinking is not being used. Figure 21 shows recommended layout techniques for this package. Vias to 2nd Layer Metal for Maximum Heat Sinking Exposed Pad 0.175 0.188 Minimum Recommended Exposed Copper 0.145 Flare Metal for Maximum Heat Sinking Figure 21. Layout Guidelines to Obtain Maximum Package Power Dissipation APPLICATIONS Figures 23 through 30 show the simplicity and flexibility of the NCP3163. Three main converter topologies are demonstrated with actual test data shown below each of the circuit diagrams. Figure 22 gives the relevant design equations for the key parameters. Additionally, a complete application design aid for the NCP3163 can be found at www.onsemi.com. http://onsemi.com 10 NCP3163 Calculation Step−Down (See Notes 1,2,3) ton toff V V out ) V F * V sat * V out in ǒ ton t on t off Voltage−Inverting V out ) V F – V in V – V sat in |V out| ) V F V * V sat in Ǔ t on ) 1 t off ƒ ƒ IL(avg) IL(avg) ) DI L ǒ V L Vripple(pp) DIL in V Vout ref ǒ ǒ Ǔ ǒ V t on R1 ) (ESR)2 [ Ǔ ) 1 V ref ǒ R2 R1 ǒ Ǔ t on ) 1 t off I out ǒ Ǔ t on ) 1 t off IL(avg) ) 2 DI L 2 0.25 Ipk (Switch) Ǔ ǒ V t on t on I out C t on t off 32.143 · 10*6 * 20 @ 10 *12 f DI L * V sat DI L in 2 R2 Ǔ t on ) 1 t off ƒ 0.25 Ipk (Switch) * V sat * V out DI L ǒ8 ƒ1COǓ Ǔ t on ) 1 t off IL(avg) ) 2 0.25 Ipk (Switch) RSC ǒ I out Iout Ipk (Switch) t on t off 32.143 · 10*6 * 20 @ 10 *12 f 32.143 · 10*6 * 20 @ 10 *12 f CT Step−Up in * V sat DI L [ O Ǔ ) 1 V ref ǒ Ǔ t on t on I out C R2 R1 O Ǔ ) 1 The following Converter Characteristics must be chosen: Nominal operating input voltage. Desired output voltage. Desired output current. Desired peak−to−peak inductor ripple current. For maximum output current it is suggested that DIL be chosen to be less than 10% of the average inductor current IL(avg). This will help prevent Ipk (Switch) from reaching the current limit threshold set by RSC. If the design goal is to use a minimum inductance value, let DIL = 2(IL(avg)). This will proportionally reduce converter output current capability. p − Maximum output switch frequency. Vripple(pp) − Desired peak−to−peak output ripple voltage. For best performance the ripple voltage should be kept to a low value since it will directly affect line and load regulation. Capacitor CO should be a low equivalent series resistance (ESR) electrolytic designed for switching regulator applications. Vin − Vout − Iout − DI L − NOTES: NOTES: NOTES: NOTES: 1. 2. 3. 3. Vsat − Saturation voltage of the output switch, refer to Figures 10 and 11. VF − Output rectifier forward voltage drop. Typical value for 1N5822 Schottky barrier rectifier is 0.5 V. The calculated ton/toff must not exceed the minimum guaranteed oscillator charge to discharge ratio of 8, at the minimum operating input voltage. Figure 22. Design Equations http://onsemi.com 11 NCP3163 − + RSC Vin Current Limit 0.25 V 8 9 7 Cin 10 VCC 6 Oscillator 11 Q1 CT RT R Q S Latch 5 Thermal 4 Q2 12 60 13 VCC 3 14 45 k R1 1 R2 Feedback Comparator + + − 2 LVI + + − D 2.0 mA 1.25 V 15 k 1.125 V 15 16 VCC 7.0 V CB RB L Vout CO (Bottom View) Figure 23. Typical Buck Application Schematic Value of Components Name Value Name L 47 mH R1 D Value 15 kW 2 A, 40 V Schottky Rectifier R2 24.9 kW Cin 47 mF, 35 V Rsc 80 mW, 1 W Cout 100 mF, 10 V Cb 4.7 nF Ct 270 pF ±10% Rb 200 W Rt 15 kW Test Results for Vout = 3.3 V Test Condition Results Line Regulation Vin = 8.0 V to 24 V, Iout = 2.5 A 13 mV Load Regulation Vin = 12 V, Iout = 0 to 2.5 A 25 mV Output Ripple Vin = 12 V, Iout = 0 to 2.5 A 100 mVpp Efficiency Vin = 12 V, Iout = 2.5 A 70.3% Short Circuit Current Vin = 12 V, RL = 0.1 W 3.1 A Condition Results Test Results for Vout = 5.05 V Test Line Regulation Vin = 10.2 V to 24 V, Iout = 2.5 A 54 mV Load Regulation Vin = 12 V, Iout = 0 to 2.5 A 28 mV Output Ripple Vin = 12 V, Iout = 0 to 2.5 A 150 mVpp Efficiency Vin = 12 V, Iout = 2.5 A 75.5% Short Circuit Current Vin = 12 V, RL = 0.1 W 3.1 A http://onsemi.com 12 NCP3163 Figure 24. Buck Layout APPLICATION SPECIFIC CHARACTERISTICS 85 3.3 V Eff EFFICIENCY (%) 80 75 5.0 V Eff 70 65 60 55 50 0 0.5 1.0 1.5 2.0 2.5 Iout (A) Figure 25. Efficiency vs. Output Current for the Buck Demo Board at Vin = 12 V, TA = 255C http://onsemi.com 13 NCP3163 8 − + RSC Vin + 7 Cin 6 RT Current Limit 0.25 V L 9 10 VCC Oscillator 11 Q1 CT Q2 R Q S Latch 5 Thermal 4 12 60 13 VCC D 3 14 45 k + + − 2 1 LVI 15 2.0 mA 1.25 V 15 k + + − 1.125 V R1 R2 Feedback Comparator 16 VCC 7.0 V CO (Bottom View) + Vout Figure 26. Typical Boost Application Schematic Value of Components for Vout = 24 V Name Value Name Value L 33 mH R1 42.2 kW D 2 A, 40 V Schottky Rectifier R2 2.32 kW Cin 330 mF, 35 V Cout 330 mF, 25 V Ct 270 pF ±10% Rsc 80 mW, 1 W Rt 15 kW Test Results for Vout = 24 V Test Condition Results Line Regulation Vin = 10 V to 20 V, Iout = 700 mA 90 mV Load Regulation Vin = 12 V, Iout = 0 to 700 mA 80 mV Output Ripple Vin = 12 V, Iout = 0 to 700 mA 300 mVpp Efficiency Vin = 12 V, Iout = 700 mA 83% Short Circuit Current Vin = 12 V, RL = 0.1 W 3.1 A http://onsemi.com 14 NCP3163 Figure 27. Boost Demo Board Layout 86 EFFICIENCY (%) 84 82 80 78 76 74 0.1 0.2 0.3 0.4 0.5 0.6 0.7 Iout (A) Figure 28. Efficiency vs. Output Current for the Boost Demo Board at Vin = 12 V, TA = 255C http://onsemi.com 15 NCP3163 − + RSC Vin Cin Current Limit 0.25 V 8 10 7 + VCC 6 Oscillator 11 Q1 CT RT 9 Q2 R Q S Latch 5 Thermal 4 12 60 13 VCC 14 3 45 k + + − 2 1 LVI R2 R1 + + − Feedback Comparator 15 2.0 mA 1.25 V 15 k 1.125 V VCC 7.0 V 16 L RB CB D Vout + CO (Bottom View) Figure 29. Typical Voltage Inverting Application Schematic Value of Components for Vout = −15 V Name Value Name Value L 47 mH R1 1.07 kW D 2 A, 40 V Schottky Rectifier R2 11.8 kW Cin 270 mF, 16 V Rsc 80 mW, 1 W Cout 2 X 270 mF, 16 V Cb 4.7 nF 150 pF ±10% Rb 200 mW Ct Test Results for Vout = −15 V Test Condition Results Line Regulation Vin = 7.0 V to 16 V, Iout = 500 mA 35 mV Load Regulation Vin = 12 V, Iout = 0 to 500 mA 20 mV Output Ripple Vin = 12 V, Iout = 0 to 500 mA 100 mVpp Efficiency Vin = 12 V, Iout = 500 mA 68% Short Circuit Current Vin = 12 V, RL = 0.1 W 3.1 A http://onsemi.com 16 NCP3163 Figure 30. Voltage Inverting Demo Board Layout 70 EFFICIENCY (%) 66 62 58 54 50 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 Iout (A) Figure 31. Efficiency vs. Output Current for the Voltage Inverting Demo Board at Vin = 12 V, TA = 255C http://onsemi.com 17 NCP3163 ORDERING INFORMATION Package Shipping † NCP3163PWG SOIC−16 W Exposed Pad (Pb−Free) 47 Units / Rail NCP3163PWR2G SOIC−16 W Exposed Pad (Pb−Free) 1000 / Tape & Reel NCP3163BPWG SOIC−16 W Exposed Pad (Pb−Free) 47 Units / Rail NCP3163BPWR2G SOIC−16 W Exposed Pad (Pb−Free) 1000 / Tape & Reel NCP3163MNR2G DFN18 (Pb−Free) 2500 / Tape & Reel NCP3163BMNR2G DFN18 (Pb−Free) 2500 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 18 NCP3163 PACKAGE DIMENSIONS SOIC 16 LEAD WIDE BODY, EXPOSED PAD PW SUFFIX CASE 751AG−01 ISSUE O −U− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751R−01 OBSOLETE, NEW STANDARD 751R−02. A M 16 9 P 0.25 (0.010) M W M B 1 R x 45_ 8 −W− G PIN 1 I.D. 14 PL DIM A B C D F G H J K L M P R DETAIL E TOP SIDE C F −T− 0.10 (0.004) T K D 16 PL 0.25 (0.010) M T U SEATING PLANE W S S J DETAIL E H EXPOSED PAD 1 8 16 9 MILLIMETERS MIN MAX 10.15 10.45 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 3.31 3.51 0.25 0.32 0.00 0.10 4.58 4.78 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.400 0.411 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.130 0.138 0.010 0.012 0.000 0.004 0.180 0.188 0_ 7_ 0.395 0.415 0.010 0.029 SOLDERING FOOTPRINT* L 0.350 Exposed Pad 0.175 0.050 BACK SIDE CL 0.200 0.188 CL 0.376 0.074 0.024 0.145 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 19 NCP3163 PACKAGE DIMENSIONS 18−LEAD DFN, 5 x 6 mm MN SUFFIX CASE 505−01 ISSUE B A D B PIN 1 LOCATION E NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS IN MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 2X DIM A A1 A3 b D D2 E E2 e K L 0.15 C 2X 0.15 C TOP VIEW (A3) 0.10 C A 18X 0.08 C A1 MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 6.00 BSC 3.98 4.28 5.00 BSC 2.98 3.28 0.50 BSC 0.20 −−− 0.45 0.65 C SIDE VIEW SEATING PLANE D2 18X 18X L e 1 9 E2 K 18 10 18X b 0.10 C A B 0.05 C NOTE 3 BOTTOM VIEW ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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