MC74HC4316A Quad Analog Switch/ Multiplexer/Demultiplexer with Separate Analog and Digital Power Supplies http://onsemi.com High−Performance Silicon−Gate CMOS The MC74HC4316A utilizes silicon−gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF−channel leakage current. This bilateral switch/multiplexer/ demultiplexer controls analog and digital voltages that may vary across the full analog power−supply range (from VCC to VEE). The HC4316A is similar in function to the metal−gate CMOS MC14016 and MC14066, and to the High−Speed CMOS HC4066A. Each device has four independent switches. The device control and Enable inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The device has been designed so that the ON resistances (RON) are much more linear over input voltage than RON of metal−gate CMOS analog switches. Logic−level translators are provided so that the On/Off Control and Enable logic−level voltages need only be VCC and GND, while the switch is passing signals ranging between VCC and VEE. When the Enable pin (active−low) is high, all four analog switches are turned off. • • • *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. June, 2005 − Rev. 4 PDIP−16 N SUFFIX CASE 648 16 1 MC74HC139AN AWLYYWWG 1 16 SOIC−16 D SUFFIX CASE 751B 16 1 HC139AG AWLYWW 1 16 SOEIAJ−16 F SUFFIX CASE 966 16 74HC139A ALYWG 1 Logic−Level Translator for On/Off Control and Enable Inputs Fast Switching and Propagation Speeds High ON/OFF Output Voltage Ratio Diode Protection on All Inputs/Outputs Analog Power−Supply Voltage Range (VCC − VEE) = 2.0 to 12.0 V Digital (Control) Power−Supply Voltage Range (VCC − GND) = 2.0 V to 6.0 V, Independent of VEE Improved Linearity of ON Resistance Chip Complexity: 66 FETs or 16.5 Equivalent Gates Pb−Free Packages are Available* © Semiconductor Components Industries, LLC, 2005 16 1 Features • • • • • • MARKING DIAGRAMS 1 A L, WL Y, YY W, WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package ORDERING INFORMATION Package Shipping † MC74HC4316AN PDIP−16 500 Units / Box MC74HC4316ANG PDIP−16 (Pb−Free) 500 Units / Box MC74HC4316ADR2 SOIC−16 2500/Tape&Reel MC74HC4316ADR2G SOIC−16 2500/Tape&Reel (Pb−Free) MC74HC4316AFEL SOEIAJ−16 50/Tape&Reel MC74HC4316AFELG SOEIAJ−16 (Pb−Free) 50/Tape&Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Publication Order Number: MC74HC4316A/D MC74HC4316A XA 1 16 YA 2 15 YB 3 14 XB B ON/OFF CONTROL C ON/OFF CONTROL ENABLE 4 13 VCC A ON/OFF CONTROL D ON/OFF CONTROL XD 5 12 YD 6 11 YC 7 10 XC GND 8 9 VEE FUNCTION TABLE Inputs Enable On/Off Control State of Analog Switch L L H H L X On Off Off X = Don’t Care. Figure 1. Pin Assignment XA A ON/OFF CONTROL XB B ON/OFF CONTROL XC C ON/OFF CONTROL XD D ON/OFF CONTROL ENABLE 1 15 7 3 YB ANALOG OUTPUTS/INPUTS ANALOG SWITCH 11 ANALOG SWITCH 12 YC LEVEL TRANSLATOR 13 14 ANALOG SWITCH YA LEVEL TRANSLATOR 10 6 2 LEVEL TRANSLATOR 4 5 ANALOG SWITCH YD LEVEL TRANSLATOR ANALOG INPUTS/OUTPUTS = XA, XB, XC, XD Figure 2. Logic Diagram http://onsemi.com 2 PIN 16 = VCC PIN 8 = GND PIN 9 = VEE GND ≥ VEE MC74HC4316A ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ MAXIMUM RATINGS Symbol Parameter Value Unit – 0.5 to + 7.0 – 0.5 to + 14.0 V Negative DC Supply Voltage (Ref. to GND) – 7.0 to + 0.5 V Analog Input Voltage VEE – 0.5 to VCC + 0.5 V VCC Positive DC Supply Voltage (Ref. to GND) (Ref. to VEE) VEE VIS Vin DC Input Voltage (Ref. to GND) – 0.5 to VCC + 0.5 V DC Current Into or Out of Any Pin ± 25 mA PD Power Dissipation in Still Air 750 500 450 mW Tstg Storage Temperature – 65 to + 150 °C TL Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP, SOIC or TSSOP Package) I Plastic DIP* EIAJ/SOIC Package* TSSOP Package* °C 260 Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. *Derating − Plastic DIP: – 10 mW/°C from 65° to 125°C EIAJ/SOIC Package: – 7 mW/°C from 65° to 125°C TSSOP Package: − 6.1 mW/°C from 65° to 125°C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit VCC Positive DC Supply Voltage (Ref. to GND) 2.0 6.0 V VEE Negative DC Supply Voltage (Ref. to GND) – 6.0 GND V VIS Analog Input Voltage VEE VCC V Vin Digital Input Voltage (Ref. to GND) GND VCC V VIO* Static or Dynamic Voltage Across Switch TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Control or Enable Inputs) (Figure 10) − 1.2 V – 55 + 125 °C 0 0 0 0 1000 600 500 400 ns VCC = 2.0 V VCC = 3.0 V VCC = 4.5 V VCC = 6.0 V *For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current may be drawn; i.e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. http://onsemi.com 3 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. I/O pins must be connected to a properly terminated line or bus. MC74HC4316A ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ DC ELECTRICAL CHARACTERISTICS Digital Section (Voltages Referenced to GND) VEE = GND Except Where Noted Guaranteed Limit Symbol Parameter Test Conditions VCC V – 55 to 25°C v 85°C v 125°C Unit VIH Minimum High−Level Voltage, Control or Enable Inputs Ron = Per Spec 2.0 3.0 4.5 6.0 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 V VIL Maximum Low−Level Voltage, Control or Enable Inputs Ron = Per Spec 2.0 3.0 4.5 6.0 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 V Iin Maximum Input Leakage Current, Control or Enable Inputs Vin = VCC or GND VEE = – 6.0 V 6.0 ± 0.1 ± 1.0 ± 1.0 mA ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND VEE = GND VIO = 0 V VEE = – 6.0 6.0 6.0 2 4 20 40 40 160 NOTE: mA Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ DC ELECTRICAL CHARACTERISTICS Analog Section (Voltages Referenced to VEE) Guaranteed Limit VCC V VEE V – 55 to 25°C v 85°C v 125°C Unit Vin = VIH VIS = VCC to VEE IS v 2.0 mA (Figures 1, 2) 2.0* 45 4.5 6.0 0.0 0.0 − 4.5 − 6.0 − 160 90 90 − 200 110 110 − 240 130 130 W Vin = VIH VIS = VCC or VEE (Endpoints) IS v 2.0 mA (Figures 1, 2) 2.0 4.5 4.5 6.0 0.0 0.0 − 4.5 − 6.0 − 90 70 70 − 115 90 90 − 140 105 105 Maximum Difference in “ON” Resistance Between Any Two Channels in the Same Package Vin = VIH VIS = 1/2 (VCC − VEE) IS v 2.0 mA 2.0 4.5 4.5 6.0 0.0 0.0 – 4.5 – 6.0 − 20 15 15 − 25 20 20 − 30 25 25 W Ioff Maximum Off−Channel Leakage Current, Any One Channel Vin = VIL VIO = VCC or VEE Switch Off (Figure 3) 6.0 – 6.0 0.1 0.5 1.0 mA Ion Maximum On−Channel Leakage Current, Any One Channel Vin = VIH VIS = VCC or VEE (Figure 4) 6.0 – 6.0 0.1 0.5 1.0 mA Symbol Ron DRon Parameter Maximum “ON” Resistance Test Conditions NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). *At supply voltage (VCC − VEE) approaching 2.0 V the analog switch−on resistance becomes extremely non−linear. Therefore, for low−voltage operation, it is recommended that these devices only be used to control digital signals. http://onsemi.com 4 MC74HC4316A ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Control or Enable tr = tf = 6 ns, VEE = GND) Guaranteed Limit Symbol tPLH, tPHL Parameter Maximum Propagation Delay, Analog Input to Analog Output (Figures 8 and 9) VCC V – 55 to 25°C v 85°C v 125°C 2.0 4.5 6.0 40 6 5 50 8 7 60 9 8 Unit ns tPLZ, tPHZ Maximum Propagation Delay, Control or Enable to Analog Output (Figures 10 and 11) 2.0 4.5 6.0 130 40 30 160 50 40 200 60 50 ns tPZL, tPZH Maximum Propagation Delay, Control or Enable to Analog Output (Figures 10 and 11) 2.0 4.5 6.0 140 40 30 175 50 40 250 60 50 ns − 10 10 10 pF C Maximum Capacitance ON/OFF Control and Enable Inputs Control Input = GND Analog I/O − 35 35 35 Feedthrough − 1.0 1.0 1.0 1. For propagation delays with loads other than 50 pF, see Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). Typical @ 25°C, VCC = 5.0 V 15 Power Dissipation Capacitance (Per Switch) (Figure 13)* pF CPD *Used to determine the no−load dynamic power consumption: P D = CPD V CC2 f + ICC VCC . For load considerations, see Chapter 2of the ON Semiconductor High−Speed CMOS Data Book (DL129/D). ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎ ÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎ ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0 V) VCC V VEE V Limit* 25°C fin = 1 MHz Sine Wave Adjust fin Voltage to Obtain 0 dBm at VOS Increase fin Frequency Until dB Meter Reads – 3 dB RL = 50 W, CL = 10 pF 2.25 4.50 6.00 – 2.25 – 4.50 – 6.00 150 160 160 MHz fin Sine Wave Adjust fin Voltage to Obtain 0 dBm at VIS fin = 10 kHz, RL = 600 W, CL = 50 pF 2.25 4.50 6.00 – 2.25 – 4.50 – 6.00 – 50 – 50 – 50 dB fin = 1.0 MHz, RL = 50 W, CL = 10 pF 2.25 4.50 6.00 – 2.25 – 4.50 – 6.00 – 40 – 40 – 40 Vin v 1 MHz Square Wave (tr = tf = 6 ns) Adjust RL at Setup so that IS = 0 A RL = 600 W, CL = 50 pF 2.25 4.50 6.00 – 2.25 – 4.50 – 6.00 60 130 200 RL = 10 kW, CL = 10 pF 2.25 4.50 6.00 – 2.25 – 4.50 – 6.00 30 65 100 fin Sine Wave Adjust fin Voltage to Obtain 0 dBm at VIS fin = 10 kHz, RL = 600 W, CL = 50 pF 2.25 4.50 6.00 – 2.25 – 4.50 – 6.00 – 70 – 70 – 70 fin = 1.0 MHz, RL = 50 W, CL = 10 pF 2.25 4.50 6.00 – 2.25 – 4.50 – 6.00 – 80 – 80 – 80 Symbol Parameter Test Conditions BW Maximum On–Channel Bandwidth or Minimum Frequency Response (Figure 5) Off–Channel Feedthrough Isolation (Figure 6) − − − THD Feedthrough Noise, Control to Switch (Figure 7) Crosstalk Between Any Two Switches (Figure 12) Total Harmonic Distortion (Figure 14) fin = 1 kHz, RL = 10 kW, CL = 50 pF THD = THDMeasured − THDSource VIS = 4.0 VPP sine wave VIS = 8.0 VPP sine wave VIS = 11.0 VPP sine wave *Limits not tested. Determined by design and verified by qualification. http://onsemi.com 5 Unit mVPP dB % 2.25 4.50 6.00 – 2.25 – 4.50 – 6.00 0.10 0.06 0.04 MC74HC4316A TBD TBD Figure 1a. Typical On Resistance, VCC − VEE = 2.0 V Figure 1b. Typical On Resistance, VCC − VEE = 4.5 V TBD TBD Figure 1d. Typical On Resistance, VCC − VEE = 9.0 V Figure 1c. Typical On Resistance, VCC − VEE = 6.0 V PLOTTER PROGRAMMABLE POWER SUPPLY TBD − MINI COMPUTER DC ANALYZER + VCC DEVICE UNDER TEST ANALOG IN COMMON OUT GND Figure 1e. Typical On Resistance, VCC − VEE = 12.0 V VEE Figure 2. On Resistance Test Set−Up http://onsemi.com 6 MC74HC4316A VCC 16 VEE A VCC VCC VCC 16 A OFF O/I N/C ON VEE VIL 7 8 9 VCC VIH 7 8 9 SELECTED CONTROL INPUT SELECTED CONTROL INPUT VEE VEE Figure 3. Maximum Off Channel Leakage Current, Any One Channel, Test Set−Up Figure 4. Maximum On Channel Leakage Current, Test Set−Up VIS VCC VCC 16 fin VCC RL ON 0.1 mF C L* RL 7 8 9 VEE 16 TO dB METER fin OFF 0.1 mF VCC RL RL 7 8 9 SELECTED CONTROL INPUT VEE *Includes all probe and jig capacitance. C L* TO dB METER SELECTED CONTROL INPUT *Includes all probe and jig capacitance. Figure 5. Maximum On−Channel Bandwidth Test Set−Up Figure 6. Off−Channel Feedthrough Isolation, Test Set−Up VCC 16 ON/OFF RL 7 8 9 VEE RL C L* TEST POINT VCC ANALOG IN SELECTED CONTROL INPUT 50% GND tPLH CONTROL ANALOG OUT tPHL 50% *Includes all probe and jig capacitance. Figure 7. Feedthrough Noise, Control to Analog Out, Test Set−Up Figure 8. Propagation Delays, Analog In to Analog Out http://onsemi.com 7 MC74HC4316A VCC 16 ANALOG I/O tr ANALOG O/I ON tf ENABLE TEST POINT VCC 50% CONTROL 50 pF* GND tPZL 7 8 9 SELECTED CONTROL INPUT VCC tPLZ HIGH IMPEDANCE 50% ANALOG OUT tPZH tPHZ 10% VOL 90% VOH 50% HIGH IMPEDANCE *Includes all probe and jig capacitance. Figure 9. Propagation Delay Test Set−Up Figure 10. Propagation Delay, ON/OFF Control to Analog Out VIS 1 POSITIONWHEN TESTING tPHZ AND tPZH 2 POSITIONWHEN TESTING tPLZ AND tPZL 1 2 fin VCC VCC 1 RL ON TEST POINT ON/OFF 2 16 0.1 mF 1 kW 16 VCC RL ANALOG I/O 50 pF* C L* TEST POINT OFF CONTROL OR ENABLE 7 8 9 8 9 VEE *Includes all probe and jig capacitance. RL C L* VCC SELECTED CONTROL INPUT *Includes all probe and jig capacitance. Figure 11. Propagation Delay Test Set−Up Figure 12. Crosstalk Between Any Two Switches, Test Set−Up (Adjacent Channels Used) VCC A VIS 16 N/C ON/OFF VCC 10 mF N/C VOS 16 fin ON RL 7 8 9 VEE SELECTED CONTROL INPUT 7 8 9 VEE CONTROL SELECTED CONTROL INPUT C L* TO DISTORTION METER VCC *Includes all probe and jig capacitance. Figure 13. Power Dissipation Capacitance Test Set−Up Figure 14. Total Harmonic Distortion, Test Set−Up http://onsemi.com 8 MC74HC4316A APPLICATIONS INFORMATION 0 −10 FUNDAMENTAL FREQUENCY −20 −30 dBm −40 −50 DEVICE −60 SOURCE −70 −80 −90 − 100 1.0 3.0 2.0 FREQUENCY (kHz) Figure 15. Plot, Harmonic Distortion The Enable and Control pins should be at VCC or GND logic levels, VCC being recognized as logic high and GND being recognized as a logic low. Unused analog inputs/outputs may be left floating (not connected). However, it is advisable to tie unused analog inputs and outputs to VCC or VEE through a low value resistor. This minimizes crosstalk and feedthrough noise that may be picked up by the unused I/O pins. The maximum analog voltage swings are determined by the supply voltages VCC and VEE. The positive peak analog voltage should not exceed VCC. Similarly, the negative peak analog voltage should not go below VEE. In the example below, the difference between VCC and VEE is 12 V. Therefore, using the configuration in Figure 16, a maximum analog signal of twelve volts peak−to−peak can be controlled. When voltage transients above VCC and/or below VEE are anticipated on the analog channels, external diodes (Dx) are recommended as shown in Figure 17. These diodes should be small signal, fast turn−on types able to absorb the maximum anticipated current surges during clipping. An alternate method would be to replace the Dx diodes with MOSORBs (MOSORBt is an acronym for high current surge protectors). MOSORBs are fast turn−on devices ideally suited for precise dc protection with no inherent wear out mechanism. VCC VCC = 6 V +6V 16 ANALOG I/O ON ANALOG O/I +6V SELECTED CONTROL INPUT VEE 8 16 Dx SELECTED CONTROL INPUT Dx Dx +6V ON −6 V −6 V VCC VCC Dx VEE ENABLE CONTROL INPUTS (VCC OR GND) VEE VEE ENABLE CONTROL INPUTS (VCC OR GND) −6 V Figure 16. Figure 17. Transient Suppressor Application http://onsemi.com 9 MC74HC4316A VCC = 5 V +5 V 16 ANALOG SIGNALS R* R* R* R* R* HC4316A 7 5 6 14 15 TTL 16 ANALOG SIGNALS ANALOG SIGNALS HCT BUFFER VEE = 0 TO −6 V ENABLE AND CONTROL 9 INPUTS 8 HC4016A 5 LSTTL/ NMOS 6 14 ANALOG SIGNALS VEE = 0 TO −6 V CONTROL INPUTS 9 15 7 R* = 2 TO 10 kW a. Using Pull−Up Resistors b. Using HCT Buffer Figure 18. LSTTL/NMOS to HCMOS Interface VCC = 12 V R1 12 V POWER SUPPLY GND = 6 V R2 VEE = 0 V R1 = R2 VCC 12 VPP ANALOG INPUT SIGNAL R3 C R4 1 OF 4 SWITCHES ANALOG OUTPUT SIGNAL 12 V 0 R1 = R2 R3 = R4 VEE Figure 19. Switching a 0−to−12 V Signal Using a Single Power Supply (GND ≠ 0 V) CHANNEL 4 1 OF 4 SWITCHES CHANNEL 3 1 OF 4 SWITCHES CHANNEL 2 1 OF 4 SWITCHES CHANNEL 1 1 OF 4 SWITCHES COMMON I/O − INPUT 1 OF 4 SWITCHES + OUTPUT LF356 OR EQUIVALENT 0.01 mF 1 2 3 4 CONTROL INPUTS Figure 20. 4−Input Multiplexer Figure 21. Sample/Hold Amplifier http://onsemi.com 10 MC74HC4316A PACKAGE DIMENSIONS PDIP−16 N SUFFIX CASE 648−08 ISSUE T NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. −A− 16 9 1 8 B F C L DIM A B C D F G H J K L M S S −T− SEATING PLANE K H D M J G 16 PL 0.25 (0.010) T A M M INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 SOIC−16 D SUFFIX CASE 751B−05 ISSUE J NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. −A− 16 9 −B− 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C −T− SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A S http://onsemi.com 11 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 MC74HC4316A PACKAGE DIMENSIONS SOEIAJ−16 F SUFFIX CASE 966−01 ISSUE O 16 LE 9 Q1 M_ E HE 1 8 L DETAIL P Z D e VIEW P A DIM A A1 b c D E e HE L LE M Q1 Z A1 b 0.13 (0.005) c NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). M 0.10 (0.004) MILLIMETERS MIN MAX −−− 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 −−− 0.78 INCHES MIN MAX −−− 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 −−− 0.031 MOSORB is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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