MC10EP56, MC100EP56 3.3V / 5VECL Dual Differential 2:1 Multiplexer The MC10/100EP56 is a dual, fully differential 2:1 multiplexer. The differential data path makes the device ideal for multiplexing low skew clock or other skew sensitive signals. Multiple VBB pins are provided. The VBB pin, an internally generated voltage supply, is available to this device only. For single−ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The device features both individual and common select inputs to address both data path and random logic applications. The 100 Series contains temperature compensation. • 360 ps Typical Propagation Delays • Maximum Frequency > 3 GHz Typical • PECL Mode Operating Range: VCC = 3.0 V to 5.5 V • • • • • • http://onsemi.com MARKING DIAGRAMS* 20 20 xxxx EP56 ALYW 1 TSSOP−20 DT SUFFIX CASE 948E 1 20 20 with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −5.5 V Open Input Default State MC100EP56 AWLYYWW 1 SO−20 DW SUFFIX CASE 751D Safety Clamp on Inputs xxx A L, WL Y, YY W, WW Separate and Common Select Q Output Will Default LOW with Inputs Open or at VEE VBB Outputs 1 = = = = = MC10 or 100 Assembly Location Wafer Lot Year Work Week *For additional information, see Application Note AND8002/D ORDERING INFORMATION Package Shipping† MC10EP56DT TSSOP−20 75 Units/Rail MC10EP56DTR2 TSSOP−20 2500 Tape & Reel MC100EP56DT TSSOP−20 MC100EP56DTR2 TSSOP−20 2500 Tape & Reel Device 75 Units/Rail MC100EP56DW SO−20 38 Units/Rail MC100EP56DWR2 SO−20 1000 Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2004 January, 2004 − Rev. 12 1 Publication Order Number: MC10EP56/D MC10EP56, MC100EP56 Q0 Q0 SEL0 20 19 18 17 1 COM_SEL VCC PIN DESCRIPTION SEL1 VCC Q1 Q1 VEE D0a* − D1a* 16 15 14 13 12 11 D0a* − D1a* ECL Input Data a Invert D0b* − D1b* ECL Input Data b D0b* − D1b* ECL Input Data b Invert 0 1 2 D0a D0a 3 1 4 VBBO D0b 5 D0b 6 0 7 D1a D1a 8 9 VBB1 D1b 10 D1b PIN FUNCTION ECL Input Data a SEL0* − SEL1* ECL Indiv. Select Input COM_SEL* ECL Common Select Input VBB0, VBB1 Output Reference Voltage Q0 − Q1 ECL True Outputs Q0 − Q1 ECL Inverted Outputs VCC Positive Supply VEE Negative Supply * Pins will default LOW when left open. TRUTH TABLE Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. SEL0 SEL1 COM_SEL Q0, Q0 Q1, Q1 X L L H H X L H H L H L L L L a b b a a a b a a b Figure 1. 20−Lead Package (Top View) and Logic Diagram ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 k Internal Input Pullup Resistor ESD Protection N/A Human Body Model Machine Model Charged Device Model Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Oxygen Index: 28 to 34 Transistor Count > 2 kV > 150 V > 2 kV Level 1 UL 94 V−0 @ 0.125 in 140 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. http://onsemi.com 2 MC10EP56, MC100EP56 MAXIMUM RATINGS (Note 2) Rating Units VCC PECL Mode Power Supply Parameter VEE = 0 V 6 V VEE NECL Mode Power Supply VCC = 0 V −6 V VI PECL Mode In Input ut Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 −6 V V Iout Output Current Continuous Surge 50 100 mA mA IBB VBB Sink/Source ± 0.5 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C JA Thermal Resistance (Junction−to−Ambient) 0 LFPM 500 LFPM 20 TSSOP 20 TSSOP 140 100 °C/W °C/W JC Thermal Resistance (Junction−to−Case) std bd 20 TSSOP 23 to 41 °C/W JA Thermal Resistance (Junction−to−Ambient) 0 LFPM 500 LFPM 20 SOIC 20 SOIC 90 60 °C/W °C/W JC Thermal Resistance (Junction−to−Case) std bd 20 SOIC 33 to 35 °C/W Tsol Wave Solder <2 to 3 sec @ 248°C 265 °C Symbol Condition 1 Condition 2 VI VCC VI VEE 2. Maximum Ratings are those values beyond which device damage may occur. 10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 50 61 75 50 63 75 55 65 78 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 4) 2165 2290 2415 2230 2355 2480 2290 2415 2540 mV VOL Output LOW Voltage (Note 4) 1365 1490 1615 1430 1555 1680 1490 1615 1740 mV VIH Input HIGH Voltage (Single−Ended) 2090 2415 2155 2480 2215 2540 mV VIL Input LOW Voltage (Single−Ended) 1365 1690 1460 1755 1490 1815 mV VBB Output Voltage Reference 1790 1990 1855 2055 1915 2115 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 5) 3.3 2.0 3.3 2.0 3.3 V IIH Input HIGH Current 150 A IIL Input LOW Current 1890 2.0 150 0.5 1955 150 0.5 0.5 2015 A NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V. 4. All loading with 50 to VCC−2.0 volts. 5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 3 MC10EP56, MC100EP56 10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 50 61 75 50 63 75 55 65 78 mA Output HIGH Voltage (Note 7) 3865 3990 4115 3930 4055 4180 3990 4115 4240 mV VOL Output LOW Voltage (Note 7) 3065 3190 3315 3130 3255 3380 3190 3315 3440 mV VIH Input HIGH Voltage (Single−Ended) 3790 4115 3855 4180 3915 4240 mV VIL Input LOW Voltage (Single−Ended) 3065 3390 3130 3455 3190 3515 mV VBB Output Voltage Reference 3490 3690 3555 3755 3615 3815 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 8) 5.0 2.0 5.0 2.0 5.0 V IIH Input HIGH Current 150 A IIL Input LOW Current IEE Power Supply Current VOH 3590 2.0 3655 150 3715 150 0.5 0.5 A 0.5 NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to −0.5 V. 7. All loading with 50 to VCC−2.0 volts. 8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 10EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = −5.5 V to −3.0 V (Note 9) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 50 61 75 50 63 75 55 65 78 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 10) −1135 −1010 −885 −1070 −945 −820 −1010 −885 −760 mV VOL Output LOW Voltage (Note 10) −1935 −1810 −1685 −1870 −1745 −1620 −1810 −1685 −1560 mV VIH Input HIGH Voltage (Single−Ended) −1210 −885 −1145 −820 −1085 −760 mV VIL Input LOW Voltage (Single−Ended) −1935 −1610 −1870 −1545 −1810 −1485 mV VBB Output Voltage Reference −1510 −1310 −1445 −1245 −1385 −1185 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 11) 0.0 V IIH Input HIGH Current 150 A IIL Input LOW Current −1410 VEE+2.0 0.0 VEE+2.0 150 0.5 −1345 0.0 VEE+2.0 150 0.5 −1285 0.5 A NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 9. Input and output parameters vary 1:1 with VCC. 10. All loading with 50 to VCC−2.0 volts. 11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 4 MC10EP56, MC100EP56 100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 12) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 50 61 75 50 63 77 55 66 80 mA Output HIGH Voltage (Note 13) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mV VOL Output LOW Voltage (Note 13) 1355 1480 1605 1355 1480 1605 1355 1480 1605 mV VIH Input HIGH Voltage (Single−Ended) 2075 2420 2075 2420 2075 2420 mV VIL Input LOW Voltage (Single−Ended) 1355 1675 1355 1675 1355 1675 mV VBB Output Voltage Reference 1775 1975 1775 1975 1775 1975 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 14) 3.3 2.0 3.3 2.0 3.3 V IIH Input HIGH Current 150 A IIL Input LOW Current IEE Power Supply Current VOH 1875 2.0 1875 150 0.5 1875 150 0.5 A 0.5 NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 12. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V. 13. All loading with 50 to VCC−2.0 volts. 14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 15) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 50 61 75 50 63 77 55 66 80 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 16) 3855 3980 4105 3855 3980 4105 3855 3980 4105 mV VOL Output LOW Voltage (Note 16) 3055 3180 3305 3055 3180 3305 3055 3180 3305 mV VIH Input HIGH Voltage (Single−Ended) 3775 4120 3775 4120 3775 4120 mV VIL Input LOW Voltage (Single−Ended) 3055 3375 3055 3375 3055 3375 mV VBB Output Voltage Reference 3475 3675 3475 3675 3475 3675 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 17) 5.0 2.0 5.0 2.0 5.0 V IIH Input HIGH Current 150 A IIL Input LOW Current 3575 2.0 150 0.5 3575 150 0.5 0.50 3575 A NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 15. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to −0.5 V. 16. All loading with 50 to VCC−2.0 volts. 17. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 5 MC10EP56, MC100EP56 100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = −5.5 V to −3.0 V (Note 18) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 50 61 75 50 63 77 55 66 80 mA Output HIGH Voltage (Note 19) −1145 −1020 −895 −1145 −1020 −895 −1145 −1020 −895 mV VOL Output LOW Voltage (Note 19) −1945 −1820 −1695 −1945 −1820 −1695 −1945 −1820 −1695 mV VIH Input HIGH Voltage (Single−Ended) −1225 −880 −1225 −880 −1225 −880 mV VIL Input LOW Voltage (Single−Ended) −1945 −1625 −1945 −1625 −1945 −1625 mV VBB Output Voltage Reference −1525 −1325 −1525 −1325 −1525 −1325 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 20) 0.0 V IIH Input HIGH Current 150 A IIL Input LOW Current IEE Power Supply Current VOH −1425 VEE+2.0 0.0 −1425 VEE+2.0 150 0.5 0.0 −1425 VEE+2.0 150 0.5 A 0.5 NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained. 18. Input and output parameters vary 1:1 with VCC. 19. All loading with 50 to VCC−2.0 volts. 20. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. AC CHARACTERISTICS VCC = 0 V; VEE = −3.0 V to −5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 21) −40°C Symbol Characteristic fmax Maximum Frequency (See Figure 2 Fmax/JITTER) tPLH, tPHL Propagation Delay to Output Differential Min Typ 25°C Max Min >3 Typ 85°C Max Min >3 Typ Max >3 Unit GHz ps D to Q, Q SEL to Q, Q COM_SEL to Q, Q 250 250 250 340 340 350 450 450 450 270 270 270 360 340 360 470 470 470 300 300 300 400 400 400 500 500 500 tSKEW Within−Device Skew (Note 22) Device to Device Skew 50 100 200 50 100 200 50 100 200 ps tJITTER Random Clock Jitter (See Figure 2 Fmax/JITTER) 0.2 <1 0.2 <1 0.2 <1 ps VPP Input Voltage Swing (Differential) 150 800 1200 150 800 1200 150 800 1200 mV tr tf Output Rise/Fall Times (20% − 80%) 70 120 170 80 130 180 100 150 230 ps Q, Q 21. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 to VCC−2.0 V. 22. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays are measured from the cross point of the inputs to the cross point of the outputs. http://onsemi.com 6 MC10EP56, MC100EP56 10 9 5V 8 800 7 3.3 V 6 600 5 JITTEROUT ps (RMS) VOUTamplitude (mVpp) 1000 ÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ 4 3 400 2 1 (JITTER) 0 200 1.0 1.5 2.0 2.5 FREQUENCY (GHz) 3.0 Figure 2. Fmax/Jitter @ 25C Q D Receiver Device Driver Device Q D 50 50 V TT V TT = V CC − 2.0 V Figure 3. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020 − Termination of ECL Logic Devices.) Resource Reference of Application Notes AN1404 − ECLinPS Circuit Performance at Non−Standard VIH Levels AN1405 − ECL Clock Distribution Techniques AN1406 − Designing with PECL (ECL at +5.0 V) AN1504 − Metastability and the ECLinPS Family AN1568 − Interfacing Between LVDS and ECL AN1650 − Using Wire−OR Ties in ECLinPS Designs AN1672 − The ECL Translator Guide AND8001 − Odd Number Counters Design AND8002 − Marking and Date Codes AND8009 − ECLinPS Plus Spice I/O Model Kit AND8020 − Termination of ECL Logic Devices For an updated list of Application Notes, please see our website at http://onsemi.com. http://onsemi.com 7 MC10EP56, MC100EP56 PACKAGE DIMENSIONS TSSOP−20 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948E−02 ISSUE B 20X 0.15 (0.006) T U 2X K REF 0.10 (0.004) S L/2 20 M T U S V S K K1 ÍÍÍÍ ÍÍÍÍ ÍÍÍÍ 11 J J1 B L −U− PIN 1 IDENT SECTION N−N 1 10 0.25 (0.010) N 0.15 (0.006) T U S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. M A −V− N F DETAIL E −W− C D G H DETAIL E 0.100 (0.004) −T− SEATING PLANE http://onsemi.com 8 DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 −−− 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0 8 INCHES MIN MAX 0.252 0.260 0.169 0.177 −−− 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0 8 MC10EP56, MC100EP56 PACKAGE DIMENSIONS SO−20 DW SUFFIX PLASTIC SOIC PACKAGE CASE 751D−05 ISSUE F A 20 X 45 h 1 10 20X B B 0.25 M T A S B S A L H M E 0.25 10X NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. 11 B M D 18X e A1 SEATING PLANE C T http://onsemi.com 9 DIM A A1 B C D E e H h L MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0 7 MC10EP56, MC100EP56 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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