MC10EP131, MC100EP131 3.3V / 5VECL Quad D Flip−Flop with Set, Reset, and Differential Clock The MC10/100EP131 is a Quad Master−slaved D flip−flop with common set and separate resets. The device is an expansion of the E131 with differential common clock and individual clock enables. With AC performance faster than the E131 device, the EP131 is ideal for applications requiring the fastest AC performance available. Each flip−flop may be clocked separately by holding Common Clock (CC) LOW and CC HIGH, then using the differential Clock Enable inputs for clocking (C0−3, C0−3). Common clocking is achieved by holding the differential inputs C0−3 LOW and C0−3 HIGH while using the differential Common Clock (CC) to clock all four flip−flops. When left floating open, any differential input will disable operation due to input pulldown resistors forcing an output default state. Individual asynchronous resets (R0−3) and an asynchronous set (SET) are provided. Data enters the master when both CC and C0−3 are LOW, and transfers to the slave when either CC or C0−3 (or both) go HIGH. The 100 Series contains temperature compensation. • • • • • • • 460 ps Typical Propagation Delay http://onsemi.com MARKING DIAGRAM* MCXXX EP131 LQFP−32 FA SUFFIX CASE 873A AWLYYWW 32 1 XXX = 10 or 100 A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week *For additional information, see Application Note AND8002/D Maximum Frequency > 3 GHz Typical Differential Individual and Common Clocks Individual Asynchronous Resets ORDERING INFORMATION Asynchronous Set • • Safety Clamp on Inputs • Q Output Will Default LOW with Inputs Open or at VEE Semiconductor Components Industries, LLC, 2004 January, 2004 − Rev. 7 Package Shipping† MC10EP131FA LQFP−32 250 Units/Tray MC10EP131FAR2 LQFP−32 2000 Tape & Reel MC100EP131FA LQFP−32 Device PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −5.5 V Open Input Default State 250 Units/Tray MC100EP131FAR2 LQFP−32 2000 Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. 1 Publication Order Number: MC10EP131/D MC10EP131, MC100EP131 Q3 Q3 Q2 Q2 Q1 Q1 Q0 Q0 S D3 24 VCC 23 22 21 20 19 18 17 VCC C3 C3 26 15 R0 C3 27 14 D0 VEE 28 13 VCC D2 D3 29 12 C0 C2 R3 30 11 C0 SET 31 10 R1 D2 32 9 VEE 32−Lead LQFP Pinout (Top View) 1 2 3 4 5 6 7 Q Q3 Q Q3 Q Q2 Q Q2 Q Q1 Q Q1 Q Q0 Q Q0 C3 16 25 D 8 R R3 S D C2 R R2 SET CC R2 C2 C2 CC CC C1 C1 CC D1 Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. R1 R C1 Figure 1. 32−Lead LQFP Pinout (Top View) C1 D1 PIN DESCRIPTION PIN FUNCTION D0−3* ECL Data Inputs C0−3*, C0−3* ECL Separate Clock Inputs CC*, CC* ECL Common Clock Inputs D S R0 R0−3* ECL Asynchronous Reset SET* ECL Asynchronous Set Q0−3, Q0−3 ECL Data Outputs VCC Positive Supply VEE Negative Supply R C0 C0 D0 D S VEE * Pins will default LOW when left open. Figure 2. Logic Diagram TRUTH TABLE D S* R* CLK Q L H X X X L L H L H L L L H H Z Z X X X L H H L Undef Z = LOW to HIGH Transition * Pins will default low when left open. http://onsemi.com 2 MC10EP131, MC100EP131 ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 k Internal Input Pullup Resistor ESD Protection N/A > 2 kV > 100 V > 2 kV Human Body Model Machine Model Charged Device Model Moisture Sensitivity (Note 1) Flammability Rating Level 2 Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 935 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. MAXIMUM RATINGS (Note 2) Symbol Rating Units VCC PECL Mode Power Supply Parameter VEE = 0 V Condition 1 Condition 2 6 V VEE NECL Mode Power Supply VCC = 0 V −6 V VI PECL Mode In Input ut Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 −6 V V Iout Output Current Continuous Surge 50 100 mA mA IBB VBB Sink/Source ± 0.5 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range θJA Thermal Resistance (Junction−to−Ambient) VI ≤ VCC VI ≥ VEE −65 to +150 °C 0 LFPM 500 LFPM 32 LQFP 32 LQFP 80 55 °C/W °C/W 32 LQFP 12 to 17 °C/W 265 °C θJC Thermal Resistance (Junction−to−Case) std bd Tsol Wave Solder > 2 to 3 sec @ 248°C 2. Maximum Ratings are those values beyond which device damage may occur. http://onsemi.com 3 MC10EP131, MC100EP131 10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3) −40°C Symbol Characteristic Min Typ 25°C Max Min Typ 85°C Max Min Typ Max Unit IEE Power Supply Current 70 95 120 70 95 120 70 95 120 mA VOH Output HIGH Voltage (Note 4) 2165 2290 2415 2230 2355 2480 2290 2415 2540 mV VOL Output LOW Voltage (Note 4) 1365 1490 1615 1430 1555 1680 1490 1615 1740 mV VIH Input HIGH Voltage (Single−Ended) 2090 2415 2155 2480 2215 2540 mV VIL Input LOW Voltage (Single−Ended) 1365 1690 1460 1755 1490 1815 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 5) 2.0 3.3 2.0 3.3 2.0 3.3 V IIH Input HIGH Current 150 µA IIL Input LOW Current 150 150 0.5 0.5 µA 0.5 NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V. 4. All loading with 50 Ω to VCC−2.0 volts. 5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 70 95 120 70 95 120 70 95 120 mA Output HIGH Voltage (Note 7) 3865 3990 4115 3930 4055 4180 3990 4115 4240 mV Output LOW Voltage (Note 7) 3065 3190 3315 3130 3255 3380 3190 3315 3440 mV VIH Input HIGH Voltage (Single−Ended) 3790 4115 3855 4180 3915 4240 mV VIL Input LOW Voltage (Single−Ended) 3065 3390 3130 3455 3190 3515 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 8) 2.0 5.0 2.0 5.0 2.0 5.0 V IIH Input HIGH Current 150 µA IIL Input LOW Current IEE Power Supply Current VOH VOL 150 150 0.5 0.5 µA 0.5 NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to −0.5 V. 7. All loading with 50 Ω to VCC−2.0 volts. 8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 10EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = −5.5 V to −3.0 V (Note 9) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 70 95 120 70 95 120 70 95 120 mA Output HIGH Voltage (Note 10) −1135 −1010 −885 −1070 −945 −820 −1010 −885 −760 mV Output LOW Voltage (Note 10) −1935 −1810 −1685 −1870 −1745 −1620 −1810 −1685 −1560 mV VIH Input HIGH Voltage (Single−Ended) −1210 −885 −1145 −820 −1085 −760 mV VIL Input LOW Voltage (Single−Ended) −1935 −1610 −1870 −1545 −1810 −1485 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 11) 0.0 V IIH Input HIGH Current 150 µA IIL Input LOW Current IEE Power Supply Current VOH VOL VEE+2.0 0.0 VEE+2.0 150 0.5 0.0 VEE+2.0 150 0.5 0.5 µA NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 9. Input and output parameters vary 1:1 with VCC. 10. All loading with 50 Ω to VCC−2.0 volts. 11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 4 MC10EP131, MC100EP131 100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 12) −40°C Symbol Characteristic 25°C 85°C Min Typ Max Min Typ Max Min Typ Max Unit 70 95 120 75 97 120 80 105 130 mA Output HIGH Voltage (Note 13) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mV Output LOW Voltage (Note 13) 1355 1480 1605 1355 1480 1605 1355 1480 1605 mV VIH Input HIGH Voltage (Single−Ended) 2075 2420 2075 2420 2075 2420 mV VIL Input LOW Voltage (Single−Ended) 1355 1675 1355 1675 1355 1675 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 14) 2.0 3.3 2.0 3.3 2.0 3.3 V IIH Input HIGH Current 150 µA IIL Input LOW Current IEE Power Supply Current VOH VOL 150 150 0.5 0.5 µA 0.5 NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 12. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V. 13. All loading with 50 Ω to VCC−2.0 volts. 14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 15) −40°C Symbol Characteristic Min Typ 25°C Max Min Typ 85°C Max Min Typ Max Unit IEE Power Supply Current 70 95 120 75 97 120 80 105 130 mA VOH Output HIGH Voltage (Note 16) 3855 3980 4105 3855 3980 4105 3855 3980 4105 mV VOL Output LOW Voltage (Note 16) 3055 3180 3305 3055 3180 3305 3055 3180 3305 mV VIH Input HIGH Voltage (Single−Ended) 3775 4120 3775 4120 3775 4120 mV VIL Input LOW Voltage (Single−Ended) 3055 3375 3055 3375 3055 3375 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 17) 2.0 5.0 2.0 5.0 2.0 5.0 V IIH Input HIGH Current 150 µA IIL Input LOW Current 150 150 0.5 0.5 µA 0.5 NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 15. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to −0.5 V. 16. All loading with 50 Ω to VCC−2.0 volts. 17. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = −5.5 V to −3.0 V (Note 18) −40°C Symbol Characteristic Min 25°C Typ Max Min Typ 85°C Max Min Typ Max Unit IEE Power Supply Current 70 95 120 75 97 120 80 105 130 mA VOH Output HIGH Voltage (Note 19) −1145 −1020 −895 −1145 −1020 −895 −1145 −1020 −895 mV VOL Output LOW Voltage (Note 19) −1945 −1820 −1695 −1945 −1820 −1695 −1945 −1820 −1695 mV VIH Input HIGH Voltage (Single−Ended) −1225 −880 −1225 −880 −1225 −880 mV VIL Input LOW Voltage (Single−Ended) −1945 −1625 −1945 −1625 −1945 −1625 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 20) 0.0 V IIH Input HIGH Current 150 µA IIL Input LOW Current VEE+2.0 0.0 VEE+2.0 150 0.5 0.0 VEE+2.0 150 0.5 0.5 µA NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 18. Input and output parameters vary 1:1 with VCC. 19. All loading with 50 Ω to VCC−2.0 volts. 20. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 5 MC10EP131, MC100EP131 AC CHARACTERISTICS VCC = 0 V; VEE = −3.0 V to −5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 21) −40°C Symbol Characteristic Min fmax Maximum Frequency (See Figure 3. Frequency vs. VOUTpp and JITTER) tPLH, tPHL Propagation Delay to Output Differential tRR tS tH tPW Minimum Pulse Rate tJITTER Cycle−to−Cycle Jitter (See Figure 3. Frequency vs. VOUTpp and JITTER) tr tf Output Rise/Fall Times (20% − 80%) C0−3 CC R0−3 SET Typ Min Set/R0−3 Recovery 290 Setup Time Hold Time 120 550 400 110 Typ 85°C Max Min >3 450 450 430 430 Q, Q Max >3 320 320 320 300 SET, R0−3 25°C 520 520 520 550 380 400 380 380 460 500 480 460 210 290 80 120 550 400 0.2 <1 180 250 125 6 Max >3 580 600 580 580 Unit GHz 450 450 450 400 560 560 560 530 210 350 280 ps 80 120 80 ps 550 400 0.2 <1 200 275 21. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 Ω to VCC−2.0 V. http://onsemi.com Typ 150 650 650 700 650 ps 0.2 <1 ps 230 300 ps 800 8 700 7 600 6 500 5 400 4 300 3 200 2 ÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉ ÉÉ ÉÉ 100 1 (JITTER) 0 0 1000 2000 JITTEROUT ps (RMS) VOUTpp (mV) MC10EP131, MC100EP131 3000 4000 5000 6000 FREQUENCY (MHz) Figure 3. Frequency vs. VOUTpp and JITTER Q D Driver Device Receiver Device D Q 50 Ω 50 Ω VTT VTT = VCC − 2.0 V Figure 4. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020 − Termination of ECL Logic Devices.) Resource Reference of Application Notes AN1404 − ECLinPS Circuit Performance at Non−Standard VIH Levels AN1405 − ECL Clock Distribution Techniques AN1406 − Designing with PECL (ECL at +5.0 V) AN1504 − Metastability and the ECLinPS Family AN1568 − Interfacing Between LVDS and ECL AN1650 − Using Wire−OR Ties in ECLinPS Designs AN1672 − The ECL Translator Guide AND8001 − Odd Number Counters Design AND8002 − Marking and Date Codes AND8009 − ECLinPS Plus Spice I/O Model Kit AND8020 − Termination of ECL Logic Devices For an updated list of Application Notes, please see our website at http://onsemi.com. http://onsemi.com 7 MC10EP131, MC100EP131 PACKAGE DIMENSIONS A 32 −T−, −U−, −Z− LQFP FA SUFFIX 32−LEAD PLASTIC PACKAGE CASE 873A−02 ISSUE A 4X A1 0.20 (0.008) AB T−U Z 25 1 −U− −T− B V AE P B1 DETAIL Y 17 8 AE DETAIL Y 9 4X −Z− 9 V1 0.20 (0.008) AC T−U Z S1 S DETAIL AD G −AB− 0.10 (0.004) AC AC T−U Z −AC− BASE METAL ÉÉ ÉÉ ÉÉ F 8X M R M N D J 0.20 (0.008) SEATING PLANE SECTION AE−AE W K X DETAIL AD Q GAUGE PLANE H 0.250 (0.010) C E http://onsemi.com 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE −AB− IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS −T−, −U−, AND −Z− TO BE DETERMINED AT DATUM PLANE −AB−. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE −AC−. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE −AB−. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12 REF 0.090 0.160 0.400 BSC 1 5 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12 REF 0.004 0.006 0.016 BSC 1 5 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF MC10EP131, MC100EP131 Notes http://onsemi.com 9 MC10EP131, MC100EP131 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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