AMD AM29DL642G90MDI

AM29DL642G
Data Sheet
RETIRED
PRODUCT
This product has been retired and is not recommended for designs. For new and current designs,
S29PL127J supersedes AM29DL642G as the factory-recommended migration path. Please refer to
the S29PL127J datasheet for specifications and ordering information. Availability of this document
is retained for reference and historical purposes only.
April 2005
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that
originally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number 26503
Revision B
Amendment 2
Issue Date June 10, 2005
THIS PAGE LEFT INTENTIONALLY BLANK.
Am29DL642G
128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only
Simultaneous Read/Write Flash Memory
This product has been retired and is not recommended for designs. For new and current designs, S29PL127J supersedes AM29DL642G as the factory-recommended migration path.
Please refer to the S29PL127J datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only.
DISTINCTIVE CHARACTERISTICS
■ Two 64 Megabit (Am29DL640G) in a single 63-ball 12
x 11 mm Fine-pitch BGA package (features are
described herein for each internal Am29DL640G)
■ Two Chip Enable inputs
— Two CE# inputs to control selection of each internal
Am29DL640G devices
■ Single power supply operation
— 2.7 to 3.6 volt read, erase, and program operations
■ Simultaneous Read/Write operations
— Data can be continuously read from one bank while
executing erase/program functions in another bank.
— Zero latency between read and write operations
■ Flexible BankTM architecture
— Read may occur in any of the three banks not being
written or erased.
— Four banks may be grouped by customer to achieve
desired bank divisions.
■ Boot Sectors
— Top and bottom boot sectors in the same device
— Any combination of sectors can be erased
■ SecSi™ (Secured Silicon) SectorSecSiTM (Secured
Silicon) Sector: Extra 256 Byte sector
— Factory locked and identifiable: 16 bytes available for
secure, random factory Electronic Serial Number;
verifiable as factory locked through autoselect
function. ExpressFlash option allows entire sector to
be available for factory-secured data
— Customer lockable: One-time programmable only.
Once locked, data cannot be changed
■ High performance
— 70 or 90 ns access time
■ Manufactured on 0.17 µm process technology
■ CFI (Common Flash Interface) compliant
— Provides device-specific information to the system,
allowing host software to easily reconfigure for
different Flash devices
■ Ultra low power consumption (typical values at 3.0 V,
5 MHz) for the part
— 10 mA typical active read current
— 15 mA typical erase/program current
— 400 nA typical standby mode current
■ Flexible sector architecture
— Two hundred fifty-six 32 Kword sectors
■ Compatibility with JEDEC standards
— Except for the added CE2#, the Fine-pitch BGA is
pinout and software compatible with single-power
supply Flash
— Superior inadvertent write protection
■ Minimum 1 million erase cycle guarantee per sector
■ 63-ball Fine-pitch BGA Package
SOFTWARE FEATURES
■ Data Management Software (DMS)
— AMD-supplied software manages data programming,
enabling EEPROM emulation
— Eases historical sector erase flash limitations
■ Supports Common Flash Memory Interface (CFI)
■ Erase Suspend/Erase Resume
— Suspends erase operations to allow reading from
other sectors in same bank
■ Data# Polling and Toggle Bits
— Provides a software method of detecting the status of
program or erase cycles
■ Unlock Bypass Program command
— Reduces overall programming time when issuing
multiple program command sequences
HARDWARE FEATURES
■ Ready/Busy# output (RY/BY#)
— Hardware method for detecting program or erase
cycle completion
■ Hardware reset pin (RESET#)
— Hardware method of resetting the internal state
machine to the read mode
■ WP#/ACC input pin
— Write protect (WP#) function protects sectors 0, 1,
140, and 141, regardless of sector protect status
— Acceleration (ACC) function accelerates program
timing
■ Sector protection
— Hardware method of locking a sector, either
in-system or using programming equipment, to
prevent any program or erase operation within that
sector
— Temporary Sector Unprotect allows changing data in
protected sectors in-system
This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication# 26503
Rev: B Amendment/+2
Issue Date: June 10, 2005
Refer to AMD’s Website (www.amd.com) for the latest information.
P R E L I M I N A R Y
GENERAL DESCRIPTION
The Am29DL642G is a 128 Mbit, 3.0 Volt (2.7 V to 3.6 V)
that combines two Am29DL640G single power supply
flash memory devices in a single 63-ball Fortified BGA
package. Each Am29DL640G is a 64 Mbit, 3.0 Volt (2.7 V
to 3.6 V) device organized as 4,194,304 words. Data appears on DQ15-DQ0. The device is designed to be programmed in-system with the standard system 3.0 volt
VCC supply. A 12.0 volt VPP is not required for program or
erase operations. The Am29DL642G is equipped with
two CE# inputs for flexible selection between the two internal 64 Mb devices. The device can also be programmed in standard EPROM programmers.
The Am29DL642G offers an access time of 70 or 90 ns.
To eliminate bus contention the Am29DL642G device has
two separate chip enables (CE# and CE2#). Each chip
enable (CE# or CE2#) is connected to only one of the two
dice in the Am29DL642G package. To the system, this
d ev i c e w i l l b e t h e s a m e a s t wo i n d e p e n d e n t
Am29DL640G on the same board. The only difference
is that they are now packaged together to reduce
board space.
Each device requires only a single 3.0 Volt power supply (2.7 V to 3.6 V) for both read and write functions. Internally generated and regulated voltages are provided
for the program and erase operations.
Simultaneous Read/Write Operations with
Zero Latency
The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space of
each Am29DL640G device into four banks, two 8 Mb
banks with small and large sectors, and two 24 Mb banks
of large sectors. Sector addresses are fixed, system software can be used to form user-defined bank groups.
During an Erase/Program operation, any of the three
non-busy banks may be read from. Note that only two
banks can operate simultaneously. The device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately
and simultaneously read from the other bank, with zero
latency. This releases the system from waiting for the
completion of program or erase operations.
Each Am29DL640G can be organized as both a top and
bottom boot sector configuration.
Bank
Megabits
Bank 1
8 Mb
Bank 2
Bank 3
24 Mb
24 Mb
Bank 4
8 Mb
Sector Sizes
Eight 4 Kword,
Fifteen 32 Kword
Forty-eight 32 Kword
Forty-eight 32 Kword
Eight 4 Kword,
Fifteen 32 Kword
Factory locked parts provide several options. The SecSi
Sector may store a secure, random 16 byte ESN (Electronic Serial Number), customer code (programmed
through AMD’s ExpressFlash service), or both. Customer
Lockable parts may utilize the SecSi Sector as bonus
space, reading and writing like any other flash sector, or
may permanently lock their own code there.
DMS (Data Management Software) allows systems to
easily take advantage of the advanced architecture of the
simultaneous read/write product line by allowing removal
of EEPROM devices. DMS will also allow the system software to be simplified, as it will perform all functions necessary to modify data in file structures, as opposed to
single-byte modifications. To write or update a particular
piece of data (a phone number or configuration data, for
example), the user only needs to state which piece of
data is to be updated, and where the updated data is located in the system. This is an advantage compared to
systems where user-written software must keep track of
the old data location, status, logical to physical translation
of the data onto the Flash memory device (or memory
devices), and more. Using DMS, user-written software
does not need to interface with the Flash memory directly. Instead, the user's software accesses the Flash
memory by calling one of only six functions. AMD provides this software to simplify system design and software integration efforts.
The device offers complete compatibility with the JEDEC
single-power-supply Flash command set standard.
Commands are written to the command register using
standard microprocessor write timings. Reading data out
of the device is similar to reading from other Flash or
EPROM devices.
The host system can detect whether a program or erase
operation is complete by using the device status bits:
RY/BY# pin, DQ7 (Data# Polling) and DQ6/DQ2 (toggle
bits). After a program or erase cycle has been completed,
the device automatically returns to the read mode.
The sector erase architecture allows memory sectors to
be erased and reprogrammed without affecting the data
contents of other sectors. The device is fully erased when
shipped from the factory.
Hardware data protection measures include a low VCC
detector that automatically inhibits write operations during power transitions. The hardware sector protection
feature disables both program and erase operations in
any combination of the sectors of memory. This can be
achieved in-system or via programming equipment.
Am29DL642G Features
The SecSi™ (Secured Silicon) Sector is an extra 256
byte sector capable of being permanently locked by AMD
or customers. The SecSi Indicator Bit (DQ7) is perma-
2
nently set to a 1 if the part is factory locked, and set to a
0 if customer lockable. This way, customer lockable
parts can never be used to replace a factory locked part.
The device offers two power-saving features. When addresses have been stable for a specified amount of time,
the device enters the automatic sleep mode. The system can also place the device into the standby mode.
Power consumption is greatly reduced in both modes.
Am29DL642G
June 10, 2005
P R E L I M I N A R Y
TABLE OF CONTENTS
Distinctive Characteristics . . . . . . . . . . . . . . . . . . 1
General Description . . . . . . . . . . . . . . . . . . . . . . . . 2
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9
Table 1. Am29DL642G Device Bus Operations ................................9
Requirements for Reading Array Data ..................................... 9
Writing Commands/Command Sequences .............................. 9
Accelerated Program Operation ............................................. 10
Autoselect Functions .............................................................. 10
Simultaneous Read/Write Operations with Zero Latency ....... 10
Standby Mode ........................................................................ 10
Automatic Sleep Mode ........................................................... 10
RESET#: Hardware Reset Pin ............................................... 10
Output Disable Mode .............................................................. 11
Table 2. Am29DL642G Sector Architecture ....................................11
Table 4. Bank Address ....................................................................17
SecSiTM Sector Addresses............................................................. 17
Autoselect Mode ..................................................................... 17
Table 6. Am29DL642G Autoselect Codes, (High Voltage Method) 18
Sector/Sector Block Protection and Unprotection .................. 19
Table 7. Am29DL642G Boot Sector/Sector Block
Addresses for Protection/Unprotection ...........................................19
Write Protect (WP#) ................................................................ 20
Table 8. WP#/ACC Modes ..............................................................20
Temporary Sector Unprotect .................................................. 20
Figure 1. Temporary Sector Unprotect Operation........................... 20
Figure 2. In-System Sector Protect/Unprotect Algorithms .............. 21
SecSi™ (Secured Silicon) Sector
Flash Memory Region ............................................................ 22
Hardware Data Protection ...................................................... 22
Low VCC Write Inhibit ............................................................ 22
Write Pulse “Glitch” Protection ............................................... 23
Logical Inhibit .......................................................................... 23
Power-Up Write Inhibit ............................................................ 23
Common Flash Memory Interface (CFI) . . . . . . . 23
Table 9. CFI Query Identification String .......................................... 23
System Interface String................................................................... 24
Table 11. Device Geometry Definition ............................................ 24
Table 12. Primary Vendor-Specific Extended Query ...................... 25
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 26
Reading Array Data ................................................................ 26
Reset Command ..................................................................... 26
Autoselect Command Sequence ............................................ 26
Enter SecSi™ Sector/Exit SecSi Sector
Command Sequence .............................................................. 26
Word Program Command Sequence ..................................... 27
Unlock Bypass Command Sequence ..................................... 27
Chip Erase Command Sequence ........................................... 28
Sector Erase Command Sequence ........................................ 28
Erase Suspend/Erase Resume Commands ........................... 29
Figure 4. Erase Operation.............................................................. 29
Table 13. Am29DL642G Command Definitions .............................. 30
Write Operation Status . . . . . . . . . . . . . . . . . . . . 31
DQ7: Data# Polling ................................................................. 31
Figure 5. Data# Polling Algorithm .................................................. 31
RY/BY#: Ready/Busy# ............................................................ 32
DQ6: Toggle Bit I .................................................................... 32
Figure 6. Toggle Bit Algorithm........................................................ 32
DQ2: Toggle Bit II ................................................................... 33
Reading Toggle Bits DQ6/DQ2 ............................................... 33
DQ5: Exceeded Timing Limits ................................................ 33
DQ3: Sector Erase Timer ....................................................... 33
Table 14. Write Operation Status ................................................... 34
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 35
Figure 7. Maximum Negative Overshoot Waveform ...................... 35
Figure 8. Maximum Positive Overshoot Waveform........................ 35
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 9. ICC1 Current vs. Time (Showing Active and
Automatic Sleep Currents) ............................................................. 37
Figure 10. Typical ICC1 vs. Frequency ............................................ 37
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 11. Test Setup.................................................................... 38
Figure 12. Input Waveforms and Measurement Levels ................. 38
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 39
Read-Only Operations ........................................................... 39
Figure 13. Read Operation Timings ............................................... 39
Hardware Reset (RESET#) .................................................... 40
Figure 14. Reset Timings ............................................................... 40
Erase and Program Operations .............................................. 41
Figure 15. Program Operation Timings..........................................
Figure 16. Accelerated Program Timing Diagram..........................
Figure 17. Chip/Sector Erase Operation Timings ..........................
Figure 18. Back-to-back Read/Write Cycle Timings ......................
Figure 19. Data# Polling Timings (During Embedded Algorithms).
Figure 20. Toggle Bit Timings (During Embedded Algorithms)......
Figure 21. DQ2 vs. DQ6.................................................................
42
42
43
44
44
45
45
Temporary Sector Unprotect .................................................. 46
Figure 22. Temporary Sector Unprotect Timing Diagram .............. 46
Figure 23. Sector/Sector Block Protect and
Unprotect Timing Diagram ............................................................. 47
Alternate CE# Controlled Erase and Program Operations ..... 48
Figure 24. Alternate CE# Controlled Write (Erase/Program)
Operation Timings.......................................................................... 49
Erase And Programming Performance . . . . . . . 50
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 50
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 51
FSD063—63-Ball Fine-Pitch Ball Grid Array (FBGA)
10.95 x 11.95 mm package .................................................... 51
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 3. Program Operation .......................................................... 28
June 10, 2005
Am29DL642G
3
P R E L I M I N A R Y
PRODUCT SELECTOR GUIDE
Part Number
Speed Rating
Am29DL642G
Regulated Voltage Range: VCC = 2.7–3.6 V
70
90
Max Access Time (ns)
70
90
CE# Access Time (ns)
70
90
OE# Access Time (ns)
30
30
Note: See “AC Characteristics” for full specifications.
4
Am29DL642G
June 10, 2005
P R E L I M I N A R Y
BLOCK DIAGRAM
VCC
Sector Switches
VSS
DQ15–DQ0
RY/BY#
Erase Voltage
Generator
RESET#
WE#
Input/Output
Buffers
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
CE#
OE#
VCC Detector
Address Latch
STB
Timer
A21–A0
STB
Data
Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
DQ15–DQ0
ACC
Sector Switches
RY/BY#
Erase Voltage
Generator
A21–A0
Input/Output
Buffers
State
Control
Command
Register
PGM Voltage
Generator
STB
VCC Detector
A21–A0
June 10, 2005
Timer
Address Latch
Chip Enable
Output Enable
Logic
CE#2
Am29DL642G
STB
Data
Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
5
P R E L I M I N A R Y
CONNECTION DIAGRAM
63-Ball Fine-pitch BGA
Top View, Balls Facing
Down
A8
B8
L8
M8
NC
NC
NC*
NC*
A7
B7
C7
D7
E7
F7
G7
H7
J7
K7
L7
M7
NC
NC
A13
A12
A14
A15
A16
CE2#
DQ15
VSS
NC*
NC*
C6
D6
E6
F6
G6
H6
J6
K6
A9
A8
A10
A11
DQ7
DQ14
DQ13
DQ6
C5
D5
E5
F5
G5
H5
J5
K5
WE#
RESET#
A21
A19
DQ5
DQ12
VCC
DQ4
C4
D4
E4
F4
G4
H4
J4
K4
A18
A20
DQ2
DQ10
DQ11
DQ3
RY/BY# WP#/ACC
A2
D3
E3
F3
G3
H3
J3
K3
A7
A17
A6
A5
DQ0
DQ8
DQ9
DQ1
C2
D2
E2
F2
G2
H2
J2
K2
L2
M2
OE#
VSS
NC*
NC*
L1
M1
NC*
NC*
A3
NC*
A1
C3
A4
A2
A1
A0
CE#
B1
* Balls are shorted together via the substrate but not connected to the die.
NC*
NC*
Special Handling Instructions for BGA
Package
Special handling is required for Flash Memory products
in BGA packages.
6
Flash memory devices in BGA packages may be
damaged if exposed to ultrasonic cleaning methods.
The package and/or data integrity may be compromised
if the package body is exposed to temperatures above
150°C for prolonged periods of time.
Am29DL642G
June 10, 2005
P R E L I M I N A R Y
PIN DESCRIPTION
A21–A0
LOGIC SYMBOL
= 22 Addresses inputs
22
DQ15–DQ0 = 16 Data inputs/outputs
A21–A0
CE#
= Chip Enable input
CE2#
= Chip Enable input for second die
OE#
= Output Enable input
WE#
= Write Enable input
WP#/ACC
= Hardware Write Protect/Acceleration
Pin
WP#/ACC
RESET#
= Hardware Reset Pin input
RESET#
RY/BY#
= Ready/Busy output
VCC
= 3.0 volt-only single power supply
(see Product Selector Guide for
speed options and voltage
supply tolerances)
VSS
= Device Ground
NC
= Pin Not Connected Internally
CE#
16
DQ15–DQ0
CE2#
OE#
June 10, 2005
Am29DL642G
WE#
RY/BY#
7
P R E L I M I N A R Y
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the following:
Am29DL642G
70
MD
I
TEMPERATURE RANGE
I
= Industrial (–40°C to +85°C)
PACKAGE TYPE
MD
= 63-Ball Fine-pitch Ball Grid Array (FBGA)
0.8 mm pitch, 10.95 x 11.95 mm package (FSD063)
SPEED OPTION
See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION
Am29DL642G
128 Megabit (2 x 8 M x 16-Bit) CMOS Simultaneous Operation Flash Memory
3.0 Volt-only Read, Program, and Erase
Valid Combinations
Valid Combinations for
Fine-pitch BGA Packages
Package
Marking
Order Number
Am29DL642G70
Am29DL642G90
8
MDI
Speed
D642G70V
I
70 ns
D642G90V
I
90 ns
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales
office to confirm availability of specific valid combinations and
to check on newly released combinations.
Am29DL642G
June 10, 2005
P R E L I M I N A R Y
DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the inputs and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Table 1.
Am29DL642G Device Bus Operations
CE#
(Note 3)
OE#
WE#
RESET#
WP#/ACC
Addresses
(Note 1)
DQ15–
DQ0
Read
L
L
H
H
L/H
AIN
DOUT
Write
L
H
L
H
(Note 4)
AIN
DIN
VCC ±
0.3 V
X
X
VCC ±
0.3 V
L/H
X
High-Z
Output Disable
L
H
H
H
L/H
X
High-Z
Reset
X
X
X
L
L/H
X
High-Z
Sector Protect (Note 2)
L
H
L
VID
L/H
SA, A6 = L,
A1 = H, A0 = L
DIN
Sector Unprotect (Note 2)
L
H
L
VID
(Note 4)
SA, A6 = H,
A1 = H, A0 = L
DIN
Temporary Sector Unprotect
X
X
X
VID
(Note 4)
AIN
DIN
Operation
Standby
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address,
AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are A21:A0.
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector
Block Protection and Unprotection” section.
3. CE# can be replaced with CE2# when referring to the second die in the package. CE# and CE2# must not both be driven at the
same time.
4. If WP#/ACC = VIL, sectors 0, 1, 140, and 141 remain protected. If WP#/ACC = VIH, protection on sectors 0, 1, 140, and 141
depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block Protection
and Unprotection”. If WP#/ACC = VHH, all sectors will be unprotected.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output control and gates array data to the output pins. WE#
should remain at VIH.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No command is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
June 10, 2005
data on the device data outputs. Each bank remains
enabled for read access until the command register
contents are altered.
Refer to the AC Read-Only Operations table for timing
specifications and to Figure 13 for the timing diagram.
ICC1 in the DC Characteristics table represents the active current specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# (or CE2#) to VIL, and OE# to VIH.
Am29DL642G
9
P R E L I M I N A R Y
The device features an Unlock Bypass mode to facilitate faster programming. Once a bank enters the Unlock Bypass mode, only two write cycles are required
to program a word, instead of four. The “Word Program Command Sequence” section has details on
programming data to the device using both standard
and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device. Table 2 indicates the address
space that each sector occupies. Similarly, a “sector
address” is the address bits required to uniquely select
a sector. The “Command Definitions” section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation.
The device address space is divided into four banks. A
“bank address” is the address bits required to uniquely
select a bank.
ICC2 in the DC Characteristics table represents the active current specification for the write mode. The AC
Characteristics section contains timing specification
tables and timing diagrams for write operations.
Accelerated Program Operation
The device offers accelerated program operations
through the ACC function. This is one of two functions
provided by the WP#/ACC pin. This function is primarily intended to allow faster manufacturing throughput
at the factory.
If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass
mode, temporarily unprotects any protected sectors,
and uses the higher voltage on the pin to reduce the
time required for program operations. The system
would use a two-cycle program command sequence
as required by the Unlock Bypass mode. Removing
VHH from the WP#/ACC pin returns the device to normal operation. Note that VHH must not be asserted on
WP#/ACC for operations other than accelerated programming, or device damage may result. In addition,
the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result.
See “Write Protect (WP#)” on page 20. for related information.
Autoselect Functions
If the system writes the autoselect command sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the internal register (which is separate from the memory array)
on DQ15–DQ0. Standard read cycle timings apply in
this mode. Refer to the Autoselect Mode and Autoselect Command Sequence sections for more information.
10
Simultaneous Read/Write Operations with
Zero Latency
This device is capable of reading data from one bank
of memory while programming or erasing in the other
bank of memory. An erase operation may also be suspended to read from or program to another location
within the same bank (except the sector being
erased). Figure 18 shows how read and write cycles
may be initiated for simultaneous operation with zero
latency. ICC6 and ICC7 in the DC Characteristics table
represent the current specifications for read-while-program and read-while-erase, respectively.
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
The device enters the CMOS standby mode when the
CE# or CE2# and RESET# pins are both held at VCC ±
0.3 V. (Note that this is a more restricted voltage range
than VIH.) If CE# and RESET# are held at VIH, but not
within VCC ± 0.3 V, the device will be in the standby
mode, but the standby current will be greater. The device requires standard access time (tCE) for read access when the device is in either of these standby
modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws active current until the
operation is completed.
I CC3 in the DC Characteristics table represents the
standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables
this mode when addresses remain stable for tACC +
30 ns. The automatic sleep mode is independent of
the CE#, CE2#, WE#, and OE# control signals. Standard address access timings provide new data when
addresses are changed. While in sleep mode, output
data is latched and always available to the system.
I CC5 in the DC Characteristics table represents the
automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state machine to reading array data. The operation that was in-
Am29DL642G
June 10, 2005
P R E L I M I N A R Y
terrupted should be reinitiated once the device is
ready to accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VSS±0.3 V, the device
draws CMOS standby current (ICC4). If RESET# is held
at VIL but not within VSS±0.3 V, the standby current will
be greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firmware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
Table 2.
Bank
Bank 1
June 10, 2005
time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of t READY (not during Embedded Algorithms). The system can read data tRH after the RESET# pin returns to VIH.
Refer to the AC Characteristics tables for RESET# parameters and to Figure 14 for the timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high
impedance state.
Am29DL642G Sector Architecture
Sector
Sector Address
A21–A12
Sector Size
(Kwords)
(x16)
Address Range
SA0
0000000000
4
00000h–00FFFh
SA1
0000000001
4
01000h–01FFFh
SA2
0000000010
4
02000h–02FFFh
SA3
0000000011
4
03000h–03FFFh
SA4
0000000100
4
04000h–04FFFh
SA5
0000000101
4
05000h–05FFFh
SA6
0000000110
4
06000h–06FFFh
SA7
0000000111
4
07000h–07FFFh
SA8
0000001xxx
32
08000h–0FFFFh
SA9
0000010xxx
32
10000h–17FFFh
SA10
0000011xxx
32
18000h–1FFFFh
SA11
0000100xxx
32
20000h–27FFFh
SA12
0000101xxx
32
28000h–2FFFFh
SA13
0000110xxx
32
30000h–37FFFh
SA14
0000111xxx
32
38000h–3FFFFh
SA15
0001000xxx
32
40000h–47FFFh
SA16
0001001xxx
32
48000h–4FFFFh
SA17
0001010xxx
32
50000h–57FFFh
SA18
0001011xxx
32
58000h–5FFFFh
SA19
0001100xxx
32
60000h–67FFFh
SA20
0001101xxx
32
68000h–6FFFFh
SA21
0001101xxx
32
70000h–77FFFh
SA22
0001111xxx
32
78000h–7FFFFh
Am29DL642G
11
P R E L I M I N A R Y
Table 2.
Bank
Bank 2
12
Am29DL642G Sector Architecture (Continued)
Sector
Sector Address
A21–A12
Sector Size
(Kwords)
(x16)
Address Range
SA23
0010000xxx
32
80000h–87FFFh
SA24
0010001xxx
32
88000h–8FFFFh
SA25
0010010xxx
32
90000h–97FFFh
SA26
0010011xxx
32
98000h–9FFFFh
SA27
0010100xxx
32
A0000h–A7FFFh
SA28
0010101xxx
32
A8000h–AFFFFh
SA29
0010110xxx
32
B0000h–B7FFFh
SA30
0010111xxx
32
B8000h–BFFFFh
SA31
0011000xxx
32
C0000h–C7FFFh
SA32
0011001xxx
32
C8000h–CFFFFh
SA33
0011010xxx
32
D0000h–D7FFFh
SA34
0011011xxx
32
D8000h–DFFFFh
SA35
0011000xxx
32
E0000h–E7FFFh
SA36
0011101xxx
32
E8000h–EFFFFh
SA37
0011110xxx
32
F0000h–F7FFFh
SA38
0011111xxx
32
F8000h–FFFFFh
SA39
0100000xxx
32
F9000h–107FFFh
SA40
0100001xxx
32
108000h–10FFFFh
SA41
0100010xxx
32
110000h–117FFFh
SA42
0101011xxx
32
118000h–11FFFFh
SA43
0100100xxx
32
120000h–127FFFh
SA44
0100101xxx
32
128000h–12FFFFh
SA45
0100110xxx
32
130000h–137FFFh
SA46
0100111xxx
32
138000h–13FFFFh
SA47
0101000xxx
32
140000h–147FFFh
SA48
0101001xxx
32
148000h–14FFFFh
SA49
0101010xxx
32
150000h–157FFFh
SA50
0101011xxx
32
158000h–15FFFFh
SA51
0101100xxx
32
160000h–167FFFh
SA52
0101101xxx
32
168000h–16FFFFh
SA53
0101110xxx
32
170000h–177FFFh
SA54
0101111xxx
32
178000h–17FFFFh
SA55
0110000xxx
32
180000h–187FFFh
SA56
0110001xxx
32
188000h–18FFFFh
SA57
0110010xxx
32
190000h–197FFFh
SA58
0110011xxx
32
198000h–19FFFFh
SA59
0100100xxx
32
1A0000h–1A7FFFh
SA60
0110101xxx
32
1A8000h–1AFFFFh
SA61
0110110xxx
32
1B0000h–1B7FFFh
SA62
0110111xxx
32
1B8000h–1BFFFFh
SA63
0111000xxx
32
1C0000h–1C7FFFh
SA64
0111001xxx
32
1C8000h–1CFFFFh
SA65
0111010xxx
32
1D0000h–1D7FFFh
SA66
0111011xxx
32
1D8000h–1DFFFFh
SA67
0111100xxx
32
1E0000h–1E7FFFh
SA68
0111101xxx
32
1E8000h–1EFFFFh
SA69
0111110xxx
32
1F0000h–1F7FFFh
SA70
0111111xxx
32
1F8000h–1FFFFFh
Am29DL642G
June 10, 2005
P R E L I M I N A R Y
Table 2.
Bank
Bank 3
June 10, 2005
Am29DL642G Sector Architecture (Continued)
Sector
Sector Address
A21–A12
Sector Size
(Kwords)
(x16)
Address Range
SA71
1000000xxx
32
200000h–207FFFh
SA72
1000001xxx
32
208000h–20FFFFh
SA73
1000010xxx
32
210000h–217FFFh
SA74
1000011xxx
32
218000h–21FFFFh
SA75
1000100xxx
32
220000h–227FFFh
SA76
1000101xxx
32
228000h–22FFFFh
SA77
1000110xxx
32
230000h–237FFFh
SA78
1000111xxx
32
238000h–23FFFFh
SA79
1001000xxx
32
240000h–247FFFh
SA80
1001001xxx
32
248000h–24FFFFh
SA81
1001010xxx
32
250000h–257FFFh
SA82
1001011xxx
32
258000h–25FFFFh
SA83
1001100xxx
32
260000h–267FFFh
SA84
1001101xxx
32
268000h–26FFFFh
SA85
1001110xxx
32
270000h–277FFFh
SA86
1001111xxx
32
278000h–27FFFFh
SA87
1010000xxx
32
280000h–28FFFFh
SA88
1010001xxx
32
288000h–28FFFFh
SA89
1010010xxx
32
290000h–297FFFh
SA90
1010011xxx
32
298000h–29FFFFh
SA91
1010100xxx
32
2A0000h–2A7FFFh
SA92
1010101xxx
32
2A8000h–2AFFFFh
SA93
1010110xxx
32
2B0000h–2B7FFFh
SA94
1010111xxx
32
2B8000h–2BFFFFh
SA95
1011000xxx
32
2C0000h–2C7FFFh
SA96
1011001xxx
32
2C8000h–2CFFFFh
SA97
1011010xxx
32
2D0000h–2D7FFFh
SA98
1011011xxx
32
2D8000h–2DFFFFh
SA99
1011100xxx
32
2E0000h–2E7FFFh
SA100
1011101xxx
32
2E8000h–2EFFFFh
SA101
1011110xxx
32
2F0000h–2FFFFFh
SA102
1011111xxx
32
2F8000h–2FFFFFh
SA103
1100000xxx
32
300000h–307FFFh
SA104
1100001xxx
32
308000h–30FFFFh
SA105
1100010xxx
32
310000h–317FFFh
SA106
1100011xxx
32
318000h–31FFFFh
SA107
1100100xxx
32
320000h–327FFFh
SA108
1100101xxx
32
328000h–32FFFFh
SA109
1100110xxx
32
330000h–337FFFh
SA110
1100111xxx
32
338000h–33FFFFh
SA111
1101000xxx
32
340000h–347FFFh
SA112
1101001xxx
32
348000h–34FFFFh
SA113
1101010xxx
32
350000h–357FFFh
SA114
1101011xxx
32
358000h–35FFFFh
SA115
1101100xxx
32
360000h–367FFFh
SA116
1101101xxx
32
368000h–36FFFFh
SA117
1101110xxx
32
370000h–377FFFh
SA118
1101111xxx
32
378000h–37FFFFh
Am29DL642G
13
P R E L I M I N A R Y
Table 2.
Bank
Bank 4
Sector
Sector Address
A21–A12
Sector Size
(Kwords)
SA119
1110000xxx
32
380000h–387FFFh
SA120
1110001xxx
32
388000h–38FFFFh
SA121
1110010xxx
32
390000h–397FFFh
SA122
1110011xxx
32
398000h–39FFFFh
SA123
1110100xxx
32
3A0000h–3A7FFFh
SA124
1110101xxx
32
3A8000h–3AFFFFh
SA125
1110110xxx
32
3B0000h–3B7FFFh
SA126
1110111xxx
32
3B8000h–3BFFFFh
SA127
1111000xxx
32
3C0000h–3C7FFFh
SA128
1111001xxx
32
3C8000h–3CFFFFh
SA129
1111010xxx
32
3D0000h–3D7FFFh
SA130
1111011xxx
32
3D8000h–3DFFFFh
SA131
1111100xxx
32
3E0000h–3E7FFFh
SA132
1111101xxx
32
3E8000h–3EFFFFh
SA133
1111110xxx
32
3F0000h–3F7FFFh
SA134
1111111000
4
3F8000h–3F8FFFh
SA135
1111111001
4
3F9000h–3F9FFFh
SA136
1111111010
4
3FA000h–3FAFFFh
SA137
1111111011
4
3FB000h–3FBFFFh
SA138
1111111100
4
3FC000h–3FCFFFh
Bank 1
14
(x16)
Address Range
SA139
1111111101
4
3FD000h–3FDFFFh
SA140
1111111110
4
3FE000h–3FEFFFh
SA141
1111111111
4
3FF000h–3FFFFFh
Table 3.
Bank
Am29DL642G Sector Architecture (Continued)
Am29DL642G Sector Architecture for CE2#
Sector
Sector Address
A21–A12
Sector Size
(Kwords)
(x16)
Address Range
SA0
0000000000
4
00000h–00FFFh
SA1
0000000001
4
01000h–01FFFh
SA2
0000000010
4
02000h–02FFFh
SA3
0000000011
4
03000h–03FFFh
SA4
0000000100
4
04000h–04FFFh
SA5
0000000101
4
05000h–05FFFh
SA6
0000000110
4
06000h–06FFFh
SA7
0000000111
4
07000h–07FFFh
SA8
0000001xxx
32
08000h–0FFFFh
SA9
0000010xxx
32
10000h–17FFFh
SA10
0000011xxx
32
18000h–1FFFFh
SA11
0000100xxx
32
20000h–27FFFh
SA12
0000101xxx
32
28000h–2FFFFh
SA13
0000110xxx
32
30000h–37FFFh
SA14
0000111xxx
32
38000h–3FFFFh
SA15
0001000xxx
32
40000h–47FFFh
SA16
0001001xxx
32
48000h–4FFFFh
SA17
0001010xxx
32
50000h–57FFFh
SA18
0001011xxx
32
58000h–5FFFFh
SA19
0001100xxx
32
60000h–67FFFh
SA20
0001101xxx
32
68000h–6FFFFh
SA21
0001101xxx
32
70000h–77FFFh
SA22
0001111xxx
32
78000h–7FFFFh
Am29DL642G
June 10, 2005
P R E L I M I N A R Y
Table 3.
Bank
Bank 2
June 10, 2005
Am29DL642G Sector Architecture for CE2# (Continued)
Sector
Sector Address
A21–A12
Sector Size
(Kwords)
(x16)
Address Range
SA23
0010000xxx
32
80000h–87FFFh
SA24
0010001xxx
32
88000h–8FFFFh
SA25
0010010xxx
32
90000h–97FFFh
SA26
0010011xxx
32
98000h–9FFFFh
SA27
0010100xxx
32
A0000h–A7FFFh
SA28
0010101xxx
32
A8000h–AFFFFh
SA29
0010110xxx
32
B0000h–B7FFFh
SA30
0010111xxx
32
B8000h–BFFFFh
SA31
0011000xxx
32
C0000h–C7FFFh
SA32
0011001xxx
32
C8000h–CFFFFh
SA33
0011010xxx
32
D0000h–D7FFFh
SA34
0011011xxx
32
D8000h–DFFFFh
SA35
0011000xxx
32
E0000h–E7FFFh
SA36
0011101xxx
32
E8000h–EFFFFh
SA37
0011110xxx
32
F0000h–F7FFFh
SA38
0011111xxx
32
F8000h–FFFFFh
SA39
0100000xxx
32
F9000h–107FFFh
SA40
0100001xxx
32
108000h–10FFFFh
SA41
0100010xxx
32
110000h–117FFFh
SA42
0101011xxx
32
118000h–11FFFFh
SA43
0100100xxx
32
120000h–127FFFh
SA44
0100101xxx
32
128000h–12FFFFh
SA45
0100110xxx
32
130000h–137FFFh
SA46
0100111xxx
32
138000h–13FFFFh
SA47
0101000xxx
32
140000h–147FFFh
SA48
0101001xxx
32
148000h–14FFFFh
SA49
0101010xxx
32
150000h–157FFFh
SA50
0101011xxx
32
158000h–15FFFFh
SA51
0101100xxx
32
160000h–167FFFh
SA52
0101101xxx
32
168000h–16FFFFh
SA53
0101110xxx
32
170000h–177FFFh
SA54
0101111xxx
32
178000h–17FFFFh
SA55
0110000xxx
32
180000h–187FFFh
SA56
0110001xxx
32
188000h–18FFFFh
SA57
0110010xxx
32
190000h–197FFFh
SA58
0110011xxx
32
198000h–19FFFFh
SA59
0100100xxx
32
1A0000h–1A7FFFh
SA60
0110101xxx
32
1A8000h–1AFFFFh
SA61
0110110xxx
32
1B0000h–1B7FFFh
SA62
0110111xxx
32
1B8000h–1BFFFFh
SA63
0111000xxx
32
1C0000h–1C7FFFh
SA64
0111001xxx
32
1C8000h–1CFFFFh
SA65
0111010xxx
32
1D0000h–1D7FFFh
SA66
0111011xxx
32
1D8000h–1DFFFFh
SA67
0111100xxx
32
1E0000h–1E7FFFh
SA68
0111101xxx
32
1E8000h–1EFFFFh
SA69
0111110xxx
32
1F0000h–1F7FFFh
SA70
0111111xxx
32
1F8000h–1FFFFFh
Am29DL642G
15
P R E L I M I N A R Y
Table 3.
Bank
Bank 3
16
Am29DL642G Sector Architecture for CE2# (Continued)
Sector
Sector Address
A21–A12
Sector Size
(Kwords)
(x16)
Address Range
SA71
1000000xxx
32
200000h–207FFFh
SA72
1000001xxx
32
208000h–20FFFFh
SA73
1000010xxx
32
210000h–217FFFh
SA74
1000011xxx
32
218000h–21FFFFh
SA75
1000100xxx
32
220000h–227FFFh
SA76
1000101xxx
32
228000h–22FFFFh
SA77
1000110xxx
32
230000h–237FFFh
SA78
1000111xxx
32
238000h–23FFFFh
SA79
1001000xxx
32
240000h–247FFFh
SA80
1001001xxx
32
248000h–24FFFFh
SA81
1001010xxx
32
250000h–257FFFh
SA82
1001011xxx
32
258000h–25FFFFh
SA83
1001100xxx
32
260000h–267FFFh
SA84
1001101xxx
32
268000h–26FFFFh
SA85
1001110xxx
32
270000h–277FFFh
SA86
1001111xxx
32
278000h–27FFFFh
SA87
1010000xxx
32
280000h–28FFFFh
SA88
1010001xxx
32
288000h–28FFFFh
SA89
1010010xxx
32
290000h–297FFFh
SA90
1010011xxx
32
298000h–29FFFFh
SA91
1010100xxx
32
2A0000h–2A7FFFh
SA92
1010101xxx
32
2A8000h–2AFFFFh
SA93
1010110xxx
32
2B0000h–2B7FFFh
SA94
1010111xxx
32
2B8000h–2BFFFFh
SA95
1011000xxx
32
2C0000h–2C7FFFh
SA96
1011001xxx
32
2C8000h–2CFFFFh
SA97
1011010xxx
32
2D0000h–2D7FFFh
SA98
1011011xxx
32
2D8000h–2DFFFFh
SA99
1011100xxx
32
2E0000h–2E7FFFh
SA100
1011101xxx
32
2E8000h–2EFFFFh
SA101
1011110xxx
32
2F0000h–2FFFFFh
SA102
1011111xxx
32
2F8000h–2FFFFFh
SA103
1100000xxx
32
300000h–307FFFh
SA104
1100001xxx
32
308000h–30FFFFh
SA105
1100010xxx
32
310000h–317FFFh
SA106
1100011xxx
32
318000h–31FFFFh
SA107
1100100xxx
32
320000h–327FFFh
SA108
1100101xxx
32
328000h–32FFFFh
SA109
1100110xxx
32
330000h–337FFFh
SA110
1100111xxx
32
338000h–33FFFFh
SA111
1101000xxx
32
340000h–347FFFh
SA112
1101001xxx
32
348000h–34FFFFh
SA113
1101010xxx
32
350000h–357FFFh
SA114
1101011xxx
32
358000h–35FFFFh
SA115
1101100xxx
32
360000h–367FFFh
SA116
1101101xxx
32
368000h–36FFFFh
SA117
1101110xxx
32
370000h–377FFFh
SA118
1101111xxx
32
378000h–37FFFFh
Am29DL642G
June 10, 2005
P R E L I M I N A R Y
Table 3.
Bank
Bank 4
Am29DL642G Sector Architecture for CE2# (Continued)
Sector
Sector Address
A21–A12
Sector Size
(Kwords)
SA119
1110000xxx
32
380000h–387FFFh
SA120
1110001xxx
32
388000h–38FFFFh
SA121
1110010xxx
32
390000h–397FFFh
SA122
1110011xxx
32
398000h–39FFFFh
SA123
1110100xxx
32
3A0000h–3A7FFFh
SA124
1110101xxx
32
3A8000h–3AFFFFh
SA125
1110110xxx
32
3B0000h–3B7FFFh
SA126
1110111xxx
32
3B8000h–3BFFFFh
SA127
1111000xxx
32
3C0000h–3C7FFFh
SA128
1111001xxx
32
3C8000h–3CFFFFh
SA129
1111010xxx
32
3D0000h–3D7FFFh
SA130
1111011xxx
32
3D8000h–3DFFFFh
SA131
1111100xxx
32
3E0000h–3E7FFFh
SA132
1111101xxx
32
3E8000h–3EFFFFh
SA133
1111110xxx
32
3F0000h–3F7FFFh
SA134
1111111000
4
3F8000h–3F8FFFh
SA135
1111111001
4
3F9000h–3F9FFFh
SA136
1111111010
4
3FA000h–3FAFFFh
SA137
1111111011
4
3FB000h–3FBFFFh
SA138
1111111100
4
3FC000h–3FCFFFh
SA139
1111111101
4
3FD000h–3FDFFFh
SA140
1111111110
4
3FE000h–3FEFFFh
SA141
1111111111
4
3FF000h–3FFFFFh
Table 4.
Bank Address
Bank
1
2
3
4
A21–A19
000
001, 010, 011
100, 101, 110
111
Table 5.
SecSiTM Sector Addresses
Device
Sector Size
(x16)
Address Range
Am29DL642G
128 words
00000h–0007Fh
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming
algorithm. However, the autoselect codes can also be
accessed in-system through the command register.
When using programming equipment, the autoselect
mode requires VID on address pin A9. Address pins
must be as shown in Table 6. In addition, when verifying sector protection, the sector address must appear
on the appropriate highest order address bits (see
June 10, 2005
(x16)
Address Range
Table 2). Table 6 shows the remaining address bits
that are don’t care. When all necessary bits have been
set as required, the programming equipment may then
read the corresponding identifier code on DQ7–DQ0.
However, the autoselect codes can also be accessed
in-system through the command register, for instances
when the Am29DL642G is erased or programmed in a
system without access to high voltage on the A9 pin.
The command sequence is illustrated in Table 13.
Note that if a Bank Address (BA) on address bits A21,
A20, and A19 is asserted during the third write cycle of
the autoselect command, the host system can read
autoselect data from that bank and then immediately
read array data from the other bank, without exiting the
autoselect mode.
Am29DL642G
17
P R E L I M I N A R Y
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 13. This method
Table 6.
Description
Device ID
Manufacturer ID:
AMD
does not require VID. Refer to the Autoselect Command Sequence section for more information.
Am29DL642G Autoselect Codes, (High Voltage Method)
CE#
OE#
WE#
A21
to
A12
L
L
H
BA
A11
to
A10
A9
A8
to
A7
X
VID
X
X
VID
A3
A2
A1
L
X
L
L
L
L
Read Cycle 1
Read Cycle 2
A6
A5
to
A4
L
L
H
BA
X
Read Cycle 3
L
X
L
Sector Protection
Verification
L
L
H
SA
X
VID
X
L
X
SecSi Indicator Bit
(DQ7)
L
L
H
BA
X
VID
X
L
X
A0
DQ15
to DQ0
DQ7
to
DQ0
L
L
X
01h
L
L
H
22h
7Eh
H
H
H
L
22h
02h
H
H
H
H
22h
01h
H
L
X
01h (protected),
00h (unprotected)
H
H
X
80h (factory locked),
00h (not factory
locked)
L
L
Legend: L = Logic Low = VIL, H = Logic High = VIH, BA = Bank Address, SA = Sector Address, X = Don’t care.
18
Am29DL642G
June 10, 2005
P R E L I M I N A R Y
Sector/Sector Block Protection and
Unprotection
Sector
A21–A12
Sector/
Sector Block Size
(Note: For the following discussion, the term “sector”
applies to both sectors and sector blocks. A sector
block consists of two or more adjacent sectors that are
protected or unprotected at the same time (see Table
7).
SA63–SA66
01110XXXXX
128 (4x32) Kwords
SA67–SA70
01111XXXXX
128 (4x32) Kwords
SA71–SA74
10000XXXXX
128 (4x32) Kwords
SA75–SA78
10001XXXXX
128 (4x32) Kwords
SA79–SA82
10010XXXXX
128 (4x32) Kwords
The hardware sector protection feature disables both
program and erase operations in any sector. The hardware sector unprotection feature re-enables both program and erase operations in previously protected
sectors. Sector protection/unprotection can be implemented via two methods.
SA83–SA86
10011XXXXX
128 (4x32) Kwords
SA87–SA90
10100XXXXX
128 (4x32) Kwords
SA91–SA94
10101XXXXX
128 (4x32) Kwords
SA95–SA98
10110XXXXX
128 (4x32) Kwords
SA99–SA102
10111XXXXX
128 (4x32) Kwords
SA103–SA106
11000XXXXX
128 (4x32) Kwords
SA107–SA110
11001XXXXX
128 (4x32) Kwords
SA111–SA114
11010XXXXX
128 (4x32) Kwords
SA115–SA118
11011XXXXX
128 (4x32) Kwords
SA119–SA122
11100XXXXX
128 (4x32) Kwords
SA123–SA126
11101XXXXX
128 (4x32) Kwords
SA127–SA130
11110XXXXX
128 (4x32) Kwords
SA131–SA133
1111100XXX,
1111101XXX,
1111110XXX
96 (3x32) Kwords
Table 7. Am29DL642G Boot Sector/Sector Block
Addresses for Protection/Unprotection
Sector
A21–A12
Sector/
Sector Block Size
SA0
0000000000
4 Kwords
SA1
0000000001
4 Kwords
SA2
0000000010
4 Kwords
SA3
0000000011
4 Kwords
SA4
0000000100
4 Kwords
SA134
1111111000
4 Kwords
SA5
0000000101
4 Kwords
SA135
1111111001
4 Kwords
SA6
0000000110
4 Kwords
SA136
1111111010
4 Kwords
SA7
0000000111
4 Kwords
SA137
1111111011
4 Kwords
SA138
1111111100
4 Kwords
SA8–SA10
0000001XXX,
0000010XXX,
0000011XXX,
SA139
1111111101
4 Kwords
SA140
1111111101
4 Kwords
SA141
1111111111
4 Kwords
96 (3x32) Kwords
SA11–SA14
00001XXXXX
128 (4x32) Kwords
SA15–SA18
00010XXXXX
128 (4x32) Kwords
SA19–SA22
00011XXXXX
128 (4x32) Kwords
SA23–SA26
00100XXXXX
128 (4x32) Kwords
SA27-SA30
00101XXXXX
128 (4x32) Kwords
SA31-SA34
00110XXXXX
128 (4x32) Kwords
SA35-SA38
00111XXXXX
128 (4x32) Kwords
SA39-SA42
01000XXXXX
128 (4x32) Kwords
SA43-SA46
01001XXXXX
128 (4x32) Kwords
SA47-SA50
01010XXXXX
128 (4x32) Kwords
SA51-SA54
01011XXXXX
128 (4x32) Kwords
SA55–SA58
01100XXXXX
128 (4x32) Kwords
SA59–SA62
01101XXXXX
128 (4x32) Kwords
June 10, 2005
The primary method requires VID on the RESET# pin
only, and can be implemented either in-system or via
programming equipment. Figure 2 shows the algorithms and Figure 23 shows the timing diagram. This
method uses standard microprocessor bus cycle timing. For sector unprotect, all unprotected sectors must
first be protected prior to the first sector unprotect
write cycle. Note that the sector unprotect algorithm
unprotects all sectors in parallel. All previously protected sectors must be individually re-protected. To
change data in protected sectors efficiently, the temporary sector unprotect function is available. See
“Temporary Sector Unprotect”.
Am29DL642G
19
P R E L I M I N A R Y
The alternate method intended only for programming
equipment requires VID on address pin A9 and OE#.
This method is compatible with programmer routines
written for earlier 3.0 volt-only AMD flash devices.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
It is possible to determine whether a sector is protected or unprotected. See the Autoselect Mode section for details.
Write Protect (WP#)
The Write Protect function provides a hardware
method of protecting without using VID. This function is
one of two provided by the WP#/ACC pin.
Temporary Sector Unprotect
(Note: For the following discussion, the term “sector”
applies to both sectors and sector blocks. A sector
block consists of two or more adjacent sectors that are
protected or unprotected at the same time (see Table
7).
This feature allows temporary unprotection of previously protected sectors to change data in-system. The
Sector Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected
sectors can be programmed or erased by selecting the
sector addresses. Once VID is removed from the RESET# pin, all the previously protected sectors are
protected again. Figure 1 shows the algorithm, and
Figure 22 shows the timing diagrams, for this feature.
If the WP#/ACC pin is at VIL, sectors 0, 1, 140, and
141 will remain protected during the Temporary sector
Unprotect mode.
If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in sectors
0, 1, 140, and 141, independently of whether those
sectors were protected or unprotected using the
method described in “Sector/Sector Block Protection
and Unprotection”.
START
If the system asserts VIH on the WP#/ACC pin, the device reverts to whether sectors 0, 1, 140, and 141
were last set to be protected or unprotected. That is,
sector protection or unprotection for these sectors depends on whether they were last protected or unprotected using the method described in “Sector/Sector
Block Protection and Unprotection”.
RESET# = VID
(Note 1)
Perform Erase or
Program Operations
Note that the WP#/ACC pin must not be left floating or
unconnected; inconsistent behavior of the device may
result.
Table 8.
WP# Input
Voltage
RESET# = VIH
WP#/ACC Modes
Temporary Sector
Unprotect Completed
(Note 2)
Device
Mode
VIL
Disables programming and erasing in
SA0, SA1, SA140, and SA141
VIH
Enables programming and erasing in
SA0, SA1, SA140, and SA141
VHH
Enables accelerated progamming (ACC).
See “Accelerated Program Operation” on
page 10..
Notes:
1. All protected sectors unprotected (If WP#/ACC = VIL,
sectors 0, 1, 140, and 141 will remain protected).
2. All previously protected sectors are protected once
again.
Figure 1.
20
Am29DL642G
Temporary Sector Unprotect Operation
June 10, 2005
P R E L I M I N A R Y
START
START
PLSCNT = 1
RESET# = VID
Wait 1 μs
Temporary Sector
Group Unprotect
Mode
No
PLSCNT = 1
Protect all sector
groups: The indicated
portion of the sector
group protect algorithm
must be performed for all
unprotected sector
groups prior to issuing
the first sector group
unprotect address
RESET# = VID
Wait 1 μs
First Write
Cycle = 60h?
First Write
Cycle = 60h?
Temporary Sector
Group Unprotect
Mode
Yes
Yes
Set up sector
group address
No
Sector Group Protect:
Write 60h to sector
group address with
A6 = 0, A1 = 1,
A0 = 0
All sector
groups
protected?
Yes
Set up first sector
group address
Sector Group
Unprotect:
Write 60h to sector
group address with
A6 = 1, A1 = 1,
A0 = 0
Wait 150 µs
Increment
PLSCNT
No
Verify Sector Group
Protect: Write 40h
to sector group
address twith A6 = 0,
A1 = 1, A0 = 0
Reset
PLSCNT = 1
Wait 15 ms
Read from
sector group address
with A6 = 0,
A1 = 1, A0 = 0
Verify Sector Group
Unprotect: Write
40h to sector group
address with
A6 = 1, A1 = 1,
A0 = 0
Increment
PLSCNT
No
No
PLSCNT
= 25?
Read from
sector group
address with A6 = 1,
A1 = 1, A0 = 0
Data = 01h?
Yes
No
Yes
Device failed
Protect
another
sector group?
Yes
Set up
next sector group
address
No
PLSCNT
= 1000?
No
Data = 00h?
Yes
Yes
Remove VID
from RESET#
Device failed
Last sector
group
verified?
Write reset
command
Sector Group
Protect
Algorithm
Sector Group
Protect complete
No
Yes
Sector Group
Unprotect
Algorithm
Remove VID
from RESET#
Write reset
command
Sector Group
Unprotect complete
Figure 2.
June 10, 2005
In-System Sector Protect/Unprotect Algorithms
Am29DL642G
21
P R E L I M I N A R Y
SecSi™ (Secured Silicon) Sector
Flash Memory Region
The SecSi (Secured Silicon) Sector feature provides a
Flash memory region that enables permanent part
identification through an Electronic Serial Number
(ESN). The SecSi Sector is 256 bytes in length, and
uses a SecSi Sector Indicator Bit (DQ7) to indicate
whether or not the SecSi Sector is locked when
shipped from the factory. This bit is permanently set at
the factory and cannot be changed, which prevents
cloning of a factory locked part. This ensures the security of the ESN once the product is shipped to the field.
AMD offers the device with the SecSi Sector either
facto r y locked or c ustomer lock able. The factory-locked version is always protected when shipped
from the factory, and has the SecSi (Secured Silicon)
Sector Indicator Bit permanently set to a “1.” The customer-lockable version is shipped with the SecSi Sector unprotected, allowing customers to utilize the that
sector in any manner they choose. The customer-lockable version has the SecSi (Secured Silicon) Sector
Indicator Bit permanently set to a “0.” Thus, the SecSi
Sector Indicator Bit prevents customer-lockable devices from being used to replace devices that are factory locked.
The system accesses the SecSi Sector Secure
through a command sequence (see “Enter SecSi™
Sector/Exit SecSi Sector Command Sequence”). After
the system has written the Enter SecSi Sector command sequence, it may read the SecSi Sector by
using the addresses normally occupied by the boot
sectors. This mode of operation continues until the
system issues the Exit SecSi Sector command sequence, or until power is removed from the device. On
power-up, or following a hardware reset, the device reverts to sending commands to the first 256 bytes of
Sector 0.
Factory Locked: SecSi Sector Programmed and
Protected At the Factory
In a factory locked device, the SecSi Sector is protected when the device is shipped from the factory.
The SecSi Sector cannot be modified in any way. The
device is preprogrammed with both a random number
and a secure ESN. The 8-word random number is at
addresses 000000h–000007h. The secure ESN is prog r a m m e d i n t h e n ex t 8 w o r d s a t a d d r e s s e s
000008h–00000Fh. The device is available preprogrammed with one of the following:
Customers may opt to have their code programmed by
AMD through the AMD ExpressFlash service. AMD
programs the customer’s code, with or without the random ESN. The devices are then shipped from AMD’s
factory with the SecSi Sector permanently locked.
Contact an AMD representative for details on using
AMD’s ExpressFlash service.
Customer Lockable: SecSi Sector NOT
Programmed or Protected At the Factory
If the security feature is not required, the SecSi Sector
can be treated as an additional Flash memory space.
The SecSi Sector can be read any number of times,
but can be programmed and locked only once. Note
that the accelerated programming (ACC) and unlock
bypass functions are not available when programming
the SecSi Sector.
The SecSi Sector area can be protected using one of
the following procedures:
■ Write the three-cycle Enter SecSi Sector Region
command sequence, and then follow the in-system
sector protect algorithm as shown in Figure 2, except that RESET# may be at either VIH or VID. This
allows in-system protection of the SecSi Sector Region without raising any device pin to a high voltage.
Note that this method is only applicable to the SecSi
Sector.
■ Write the three-cycle Enter SecSi Sector Secure
Region command sequence, and then use the alternate method of sector protection described in the
“Sector/Sector Block Protection and Unprotection”
section.
Once the SecSi Sector is locked and verified, the system must write the Exit SecSi Sector Region command sequence to return to reading and writing the
remainder of the array.
The SecSi Sector lock must be used with caution
since, once locked, there is no procedure available for
unlocking the SecSi Sector area and none of the bits
in the SecSi Sector memory space can be modified in
any way.
Hardware Data Protection
■ Customer code through the ExpressFlash service
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 13 for command definitions). In addition, the following hardware
data protection measures prevent accidental erasure
or programming, which might otherwise be caused by
spurious system level signals during V CC power-up
and power-down transitions, or from system noise.
■ Both a random, secure ESN and customer code
through the ExpressFlash service.
Low VCC Write Inhibit
■ A random, secure ESN only
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC
22
Am29DL642G
June 10, 2005
P R E L I M I N A R Y
power-up and power-down. The command register
and all internal program/erase circuits are disabled,
and the device resets to the read mode. Subsequent
writes are ignored until VCC is greater than VLKO. The
system must provide the proper signals to the control
pins to prevent unintentional writes when V CC is
greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE#
or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up,
the device does not accept commands on the rising
edge of WE#. The internal state machine is automatically reset to the read mode on power-up.
COMMON FLASH MEMORY INTERFACE
(CFI)
The Common Flash Interface (CFI) specification outlines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of
Table 9.
devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and
backward-compatible for the specified flash device
families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address
55h, any time the device is ready to read array data.
The system can read CFI information at the addresses
given in Tables 9–12. To terminate reading CFI data,
the system must write the reset command.The CFI
Query mode is not accessible when the device is executing an Embedded Program or embedded Erase algorithm.
The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
CFI data at the addresses given in Tables 9–12. The
system must write the reset command to return the
device to reading array data.
For further information, please refer to the CFI Specification and CFI Publication 100, available via the World
W i d e We b a t h t t p : / / w w w. a m d . c o m / u s - e n / a s sets/content_type/DownloadableAssets/cfi100.pdf and
http://www.amd.com/us-en/assets/content_type/Down
loadableAssets/cfiamd1.pdf. Alternatively, contact an
AMD representative for copies of these documents.
CFI Query Identification String
Addresses
Data
10h
11h
12h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
13h
14h
0002h
0000h
Primary OEM Command Set
15h
16h
0040h
0000h
Address for Primary Extended Table
17h
18h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
19h
1Ah
0000h
0000h
Address for Alternate OEM Extended Table (00h = none exists)
June 10, 2005
Description
Am29DL642G
23
P R E L I M I N A R Y
Table 10.
Addresses
Data
Description
1Bh
0027h
VCC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Ch
0036h
VCC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Dh
0000h
VPP Min. voltage (00h = no VPP pin present)
1Eh
0000h
VPP Max. voltage (00h = no VPP pin present)
1Fh
0004h
Typical timeout per single byte/word write 2N µs
20h
0000h
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
21h
000Ah
Typical timeout per individual block erase 2N ms
22h
0000h
Typical timeout for full chip erase 2N ms (00h = not supported)
23h
0005h
Max. timeout for byte/word write 2N times typical
24h
0000h
Max. timeout for buffer write 2N times typical
25h
0004h
Max. timeout per individual block erase 2N times typical
26h
0000h
Max. timeout for full chip erase 2N times typical (00h = not supported)
Table 11.
Addresses
24
System Interface String
Device Geometry Definition
Data
Description
N
27h
0017h
Device Size = 2 byte
28h
29h
0002h
0000h
Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh
0000h
0000h
Max. number of byte in multi-byte write = 2N
(00h = not supported)
2Ch
0003h
Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
0007h
0000h
0020h
0000h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
31h
32h
33h
34h
007Dh
0000h
0000h
0001h
Erase Block Region 2 Information
(refer to the CFI specification or CFI publication 100)
35h
36h
37h
38h
0007h
0000h
0020h
0000h
Erase Block Region 3 Information
(refer to the CFI specification or CFI publication 100)
39h
3Ah
3Bh
3Ch
0000h
0000h
0000h
0000h
Erase Block Region 4 Information
(refer to the CFI specification or CFI publication 100)
Am29DL642G
June 10, 2005
P R E L I M I N A R Y
Table 12.
Primary Vendor-Specific Extended Query
Addresses
Data
Description
40h
41h
42h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h
0031h
Major version number, ASCII (reflects modifications to the silicon)
44h
0033h
Minor version number, ASCII (reflects modifications to the CFI table)
45h
0004h
Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
Silicon Revision Number (Bits 7-2)
46h
0002h
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
47h
0001h
Sector Protect
0 = Not Supported, X = Number of sectors in per group
48h
0001h
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
49h
0004h
Sector Protect/Unprotect scheme
01 =29F040 mode, 02 = 29F016 mode, 03 = 29F400, 04 = 29LV800 mode
4Ah
0077h
Simultaneous Operation
00 = Not Supported, X = Number of Sectors (excluding Bank 1)
4Bh
0000h
Burst Mode Type
00 = Not Supported, 01 = Supported
4Ch
0000h
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
4Dh
0085h
4Eh
0095h
ACC (Acceleration) Supply Minimum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
Top/Bottom Boot Sector Flag
4Fh
0004h
50h
0001h
57h
0004h
58h
0017h
59h
0030h
5Ah
0030h
5Bh
0017h
June 10, 2005
00h = Uniform device, 01h = 8 x 8 Kbyte Sectors, Top And Bottom Boot with Write
Protect, 02h = Bottom Boot Device, 03h = Top Boot Device, 04h = Both Top and
Bottom
Program Suspend
0 = Not supported, 1 = Supported
Bank Organization
00 = Data at 4Ah is zero, X = Number of Banks
Bank 1 Region Information
X = Number of Sectors in Bank 1
Bank 2 Region Information
X = Number of Sectors in Bank 2
Bank 3 Region Information
X = Number of Sectors in Bank 3
Bank 4 Region Information
X = Number of Sectors in Bank 4
Am29DL642G
25
P R E L I M I N A R Y
COMMAND DEFINITIONS
Writing specific address and data commands or sequences into the command register initiates device operations. Table 13 defines the valid register command
sequences. Writing incorrect address and data values or writing them in the improper sequence resets
the device to reading array data.
All addresses are latched on the falling edge of WE#
or CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the AC Characteristics section for timing
diagrams.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. Each bank is ready to read array data
after completing an Embedded Program or Embedded
Erase algorithm.
After the device accepts an Erase Suspend command,
the corresponding bank enters the erase-suspend-read mode, after which the system can read
data from any non-erase-suspended sector within the
same bank. The system can read array data using the
standard read timing, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming
operation in the Erase Suspend mode, the system
may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands section for more information.
The system must issue the reset command to return a
bank to the read (or erase-suspend-read) mode if DQ5
goes high during an active program or erase operation, or if the bank is in the autoselect mode. See the
next section, Reset Command, for more information.
See also Requirements for Reading Array Data in the
Device Bus Operations section for more information.
The Read-Only Operations table provides the read parameters, and Figure 13 shows the timing diagram.
Reset Command
Writing the reset command resets the banks to the
read or erase-suspend-read mode. Address bits are
don’t cares for this command.
The reset command may be written between the sequence cycles in an erase command sequence before
erasing begins. This resets the bank to which the system was writing to the read mode. Once erasure begins, however, the device ignores reset commands
until the operation is complete.
The reset command may be written between the
sequence cycles in a program command sequence
before programming begins. This resets the bank to
26
which the system was writing to the read mode. If the
program command sequence is written to a bank that
is in the Erase Suspend mode, writing the reset
command retur ns that bank to the erase-suspend-read mode. Once programming begins, however,
the device ignores reset commands until the operation
is complete.
The reset command may be written between the sequence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command
must be written to return to the read mode. If a bank
entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns that
bank to the erase-suspend-read mode.
If DQ5 goes high during a program or erase operation,
writing the reset command returns the banks to the
read mode (or erase-suspend-read mode if that bank
was in Erase Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and device codes,
and determine whether or not a sector is protected.
The autoselect command sequence may be written to
an address within a bank that is either in the read or
erase-suspend-read mode. The autoselect command
may not be written while the device is actively programming or erasing in the other bank.
The autoselect command sequence is initiated by first
writing two unlock cycles. This is followed by a third
write cycle that contains the bank address and the autoselect command. The bank then enters the autoselect mode. The system may read any number of
autoselect codes without reinitiating the command sequence.
Table 13 shows the address and data requirements.
To determine sector protection information, the system
must write to the appropriate bank address (BA) and
sector address (SA). Table 2 shows the address range
and bank number associated with each sector.
The system must write the reset command to return to
the read mode (or erase-suspend-read mode if the
bank was previously in Erase Suspend).
Enter SecSi™ Sector/Exit SecSi Sector
Command Sequence
The SecSi Sector region provides a secured data area
containing a random, sixteen-byte electronic serial
number (ESN). The system can access the SecSi
Sector region by issuing the three-cycle Enter SecSi
Sector command sequence. The device continues to
access the SecSi Sector region until the system issues the four-cycle Exit SecSi Sector command se-
Am29DL642G
June 10, 2005
P R E L I M I N A R Y
quence. The Exit SecSi Sector command sequence
returns the device to normal operation. The SecSi
Sector is not accessible when the device is executing
an Embedded Program or embedded Erase algorithm.
Table 13 shows the address and data requirements for
both command sequences. See also “SecSi™ (Secured Silicon) Sector Flash Memory Region” for further
information.
Word Program Command Sequence
Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two
unlock write cycles, followed by the program set-up
command. The program address and data are written
next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further
controls or timings. The device automatically provides
internally generated program pulses and verifies the
programmed cell margin. Table 13 shows the address
and data requirements for the word program command
sequence.
When the Embedded Program algorithm is complete,
that bank then returns to the read mode and addresses are no longer latched. The system can determine the status of the program operation by using
DQ7, DQ6, or RY/BY#. Refer to the Write Operation
Status section for information on these status bits.
Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program
operation. The program command sequence should
be reinitiated once that bank has returned to the read
mode, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from “0” back to a “1.” Attempting to do so may
cause that bank to set DQ5 = 1, or cause the DQ7 and
DQ6 status bits to indicate the operation was successful. However, a succeeding read will show that the
data is still “0.” Only erase operations can convert a “0”
to a “1.”
June 10, 2005
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program words to a bank faster than using the standard
program command sequence. The unlock bypass
command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. That bank
then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is
required to program in this mode. The first cycle in this
sequence contains the unlock bypass program command, A0h; the second cycle contains the program
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in faster total programming time. Table 13 shows the requirements for the
command sequence.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the bank
address and the data 90h. The second cycle need
only contain the data 00h. The bank then returns to
the read mode.
The device offers accelerated program operations
through the WP#/ACC pin. When the system asserts
VHH on the WP#/ACC pin, the device automatically enters the Unlock Bypass mode. The system may then
write the two-cycle Unlock Bypass program command
sequence. The device uses the higher voltage on the
WP#/ACC pin to accelerate the operation. Note that
the WP#/ACC pin must not be at VHH any operation
other than accelerated programming, or device damage may result. In addition, the WP#/ACC pin must not
be left floating or unconnected; inconsistent behavior
of the device may result.
Figure 3 illustrates the algorithm for the program operation. Refer to the Erase and Program Operations
table in the AC Characteristics section for parameters,
and Figure 15 for timing diagrams.
Am29DL642G
27
P R E L I M I N A R Y
Any commands written during the chip erase operation
are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be
reinitiated once that bank has returned to reading
array data, to ensure data integrity.
START
Figure 4 illustrates the algorithm for the erase operation. Refer to the Erase and Program Operations tables in the AC Characteristics section for parameters,
and Figure 17 section for timing diagrams.
Write Program
Command Sequence
Embedded
Program
algorithm
in progress
Data Poll
from System
Sector Erase Command Sequence
Verify Data?
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then followed by the address of the sector to be erased, and
the sector erase command. Table 13 shows the address and data requirements for the sector erase command sequence.
No
Yes
Increment Address
No
The device does not require the system to preprogram
prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or timings during these operations.
Last Address?
Yes
Programming
Completed
Note: See Table 13 for program command sequence.
Figure 3.
Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any controls or timings during these operations. Table 13
shows the address and data requirements for the chip
erase command sequence.
When the Embedded Erase algorithm is complete,
that bank returns to the read mode and addresses are
no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2,
or RY/BY#. Refer to the Write Operation Status section for information on these status bits.
28
After the command sequence is written, a sector erase
time-out of 80 µs occurs. During the time-out period,
additional sector addresses and sector erase commands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sectors may be from one sector to all sectors. The time
between these additional cycles must be less than 80
µs, otherwise erasure may begin. Any sector erase address and command following the exceeded time-out
may or may not be accepted. It is recommended that
processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase command is
written. Any command other than Sector Erase or
Erase Suspend during the time-out period resets
that bank to the read mode. The system must rewrite
the command sequence and any additional addresses
and commands.
The system can monitor DQ3 to determine if the sector erase timer has timed out (See the section on DQ3:
Sector Erase Timer.). The time-out begins from the rising edge of the final WE# pulse in the command
sequence.
When the Embedded Erase algorithm is complete, the
bank returns to reading array data and addresses are
no longer latched. Note that while the Embedded
Erase operation is in progress, the system can read
data from the non-erasing bank. The system can determine the status of the erase operation by reading
Am29DL642G
June 10, 2005
P R E L I M I N A R Y
DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. Refer
to the Write Operation Status section for information
on these status bits.
just as in the standard Word Program operation.
Refer to the Write Operation Status section for more
information.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands are ignored. However, note that a hardware
reset immediately terminates the erase operation. If
that occurs, the sector erase command sequence
should be reinitiated once that bank has returned to
reading array data, to ensure data integrity.
In the erase-suspend-read mode, the system can also
issue the autoselect command sequence. The device
allows reading autoselect codes even at addresses
within erasing sectors, since the codes are not stored
in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation.
Refer to the Autoselect Mode and Autoselect Command Sequence sections for details.
Figure 4 illustrates the algorithm for the erase operation. Refer to the Erase and Program Operations tables in the AC Characteristics section for parameters,
and Figure 17 section for timing diagrams.
Erase Suspend/Erase Resume
Commands
The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read
data from, or program data to, any sector not selected
for erasure. The bank address is required when writing
this command. This command is valid only during the
sector erase operation, including the 80 µs time-out
period during the sector erase command sequence.
The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program
algorithm.
To resume the sector erase operation, the system
must write the Erase Resume command (address bits
are don’t care). The bank address of the erase-suspended bank is required when writing this command.
Further writes of the Resume command are ignored.
Another Erase Suspend command can be written after
the chip has resumed erasing.
START
Write Erase
Command Sequence
(Notes 1, 2)
When the Erase Suspend command is written during
the sector erase operation, the device requires a maximum of 20 µs to suspend the erase operation. However, when the Erase Suspend command is written
during the sector erase time-out, the device immediately terminates the time-out period and suspends the
erase operation. Addresses are “don’t-cares” when
writing the Erase suspend command.
After the erase operation has been suspended, the
bank enters the erase-suspend-read mode. The system can read data from or program data to any sector
not selected for erasure. (The device “erase suspends” all sectors selected for erasure.) Reading at
any address within erase-suspended sectors produces status information on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
Refer to the Write Operation Status section for information on these status bits.
After an erase-suspended program operation is complete, the bank returns to the erase-suspend-read
mode. The system can determine the status of the
program operation using the DQ7 or DQ6 status bits,
June 10, 2005
Data Poll to Erasing
Bank from System
No
Embedded
Erase
algorithm
in progress
Data = FFh?
Yes
Erasure Completed
Notes:
1. See Table 13 for erase command sequence.
2. See the section on DQ3 for information on the sector
erase timer.
Am29DL642G
Figure 4.
Erase Operation
29
P R E L I M I N A R Y
Autoselect (Note 8)
Command
Sequence
(Note 1)
Read (Note 6)
Reset (Note 7)
Manufacturer ID
Device ID (Note 9)
SecSi Sector Factory Protect
(Note 10)
Sector/Sector Block Protect
Verify (Note 11)
Enter SecSi Sector Region
Exit SecSi Sector Region
Program
Unlock Bypass
Unlock Bypass Program (Note 12)
Unlock Bypass Reset (Note 13)
Chip Erase
Sector Erase
Erase Suspend (Note 14)
Erase Resume (Note 15)
CFI Query (Note 16)
Cycles
Table 13.
1
1
4
6
Am29DL642G Command Definitions
First
Addr Data
RA
RD
XXX
F0
555
AA
555
AA
Second
Addr Data
2AA
2AA
55
55
(BA)555
(BA)555
90
90
(BA)X00
(BA)X01
01
7E
4
555
AA
2AA
55
(BA)555
90
(BA)X03 80/00
4
555
AA
2AA
55
(BA)555
90
(SA)X02 00/01
3
4
4
3
2
2
6
6
1
1
1
555
555
555
555
XXX
BA
555
555
BA
BA
55
AA
AA
AA
AA
A0
90
AA
AA
B0
30
98
2AA
2AA
2AA
2AA
PA
XXX
2AA
2AA
55
55
55
55
PD
00
55
55
555
555
555
555
88
90
A0
20
XXX
PA
00
PD
555
555
80
80
555
555
AA
AA
Legend:
X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses
latch on the falling edge of the WE# or CE# pulse, whichever happens
later.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect
command sequence, all bus cycles are write cycles.
4. Data bits DQ15–DQ8 are don’t care in command sequences,
except for RD and PD.
5. Unless otherwise noted, address bits A21–A11 are don’t cares for
unlock and command cycles, unless SA or PA is required.
6. No unlock or command cycles required when bank is reading
array data.
7. The Reset command is required to return to the read mode (or to
the erase-suspend-read mode if previously in Erase Suspend)
when a bank is in the autoselect mode, or if DQ5 goes high (while
the bank is providing status information).
8. The fourth cycle of the autoselect command sequence is a read
cycle. The system must provide the bank address to obtain the
manufacturer ID, device ID, or SecSi Sector factory protect
information. Data bits DQ15–DQ8 are don’t care. See the
Autoselect Command Sequence section for more information.
30
Bus Cycles (Notes 2–5)
Third
Fourth
Addr
Data
Addr
Data
Fifth
Addr
Data
Sixth
Addr
Data
(BA)X0E
02
(BA)X0F
01
2AA
2AA
55
55
555
SA
10
30
PD = Data to be programmed at location PA. Data latches on the rising
edge of WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A21–A12 uniquely select any sector. Refer to
Table 2 for information on sector addresses.
BA = Address of the bank that is being switched to autoselect mode, is
in bypass mode, or is being erased. A21–A19 uniquely select a bank.
9.
10.
11.
12.
13.
14.
15.
16.
The device ID must be read across the fourth, fifth, and sixth
cycles.
The data is 80h for factory locked and 00h for not factory locked.
The data is 00h for an unprotected sector/sector block and 01h for
a protected sector/sector block.
The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
The Unlock Bypass Reset command is required to return to the
read mode when the bank is in the unlock bypass mode.
The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation, and requires the bank address.
The Erase Resume command is valid only during the Erase
Suspend mode, and requires the bank address.
Command is valid when device is ready to read array data or when
device is in autoselect mode.
Am29DL642G
June 10, 2005
P R E L I M I N A R Y
WRITE OPERATION STATUS
The device provides several bits to determine the status of a
program or erase operation: DQ2, DQ3, DQ5, DQ6, and
DQ7. Table 14 and the following subsections describe the
function of these bits. DQ7 and DQ6 each offer a method for
determining whether a program or erase operation is complete or in progress. The device also provides a hardware-based output signal, RY/BY#, to determine whether
an Embedded Program or Erase operation is in progress or
has been completed.
pleted the program or erase operation and DQ7 has
valid data, the data outputs on DQ15–DQ0 may be still
invalid. Valid data on DQ15–DQ0 will appear on successive read cycles.
Table 14 shows the outputs for Data# Polling on DQ7.
Figure 5 shows the Data# Polling algorithm. Figure 19
in the AC Characteristics section shows the Data#
Polling timing diagram.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system
whether an Embedded Program or Erase algorithm is in
progress or completed, or whether a bank is in Erase Suspend. Data# Polling is valid after the rising edge of the final
WE# pulse in the command sequence.
START
Read DQ7–DQ0
Addr = VA
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to
DQ7. This DQ7 status also applies to programming during
Erase Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to
DQ7. The system must provide the program address to
read valid status information on DQ7. If a program address
falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 µs, then that bank returns to the
read mode.
DQ7 = Data?
No
No
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the bank enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
The system must provide an address within any of the
sectors selected for erasure to read valid status information on DQ7.
June 10, 2005
DQ5 = 1?
Yes
Read DQ7–DQ0
Addr = VA
After an erase command sequence is written, if all
sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 µs, then the
bank returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected
sector, the status may not be valid.
When the system detects DQ7 has changed from the
complement to true data, it can read valid data at
DQ15–DQ0 on the following read cycles. Just prior to
the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with
DQ15–DQ8 while Output Enable (OE#) is asserted
low. That is, the device may change from providing
status information to valid data on DQ7. Depending on
when the system samples the DQ7 output, it may read
the status or valid data. Even if the device has com-
Yes
DQ7 = Data?
Yes
No
FAIL
PASS
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector address
within the sector being erased. During chip erase, a
valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
Am29DL642G
Figure 5.
Data# Polling Algorithm
31
P R E L I M I N A R Y
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin
which indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a
pull-up resistor to VCC.
If the output is low (Busy), the device is actively erasing or programming. (This includes programming in
the Erase Suspend mode.) If the output is high
(Ready), the device is in the read mode, the standby
mode, or one of the banks is in the erase-suspend-read mode.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Program algorithm is complete.
Table 14 shows the outputs for Toggle Bit I on DQ6.
Figure 6 shows the toggle bit algorithm. Figure 20 in
the “AC Characteristics” section shows the toggle bit
timing diagrams. Figure 21 shows the differences between DQ2 and DQ6 in graphical form. See also the
subsection on DQ2: Toggle Bit II.
START
Table 14 shows the outputs for RY/BY#.
Read DQ7–DQ0
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase
Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final
WE# pulse in the command sequence (prior to the
program or erase operation), and during the sector
erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause
DQ6 to toggle. The system may use either OE# or
CE# to control the read cycles. When the operation is
complete, DQ6 stops toggling.
Read DQ7–DQ0
Toggle Bit
= Toggle?
Yes
No
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 toggles for approximately 100 µs, then returns to reading
array data. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are protected.
DQ5 = 1?
Yes
Read DQ7–DQ0
Twice
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is
erase-suspended. When the device is actively erasing
(that is, the Embedded Erase algorithm is in progress),
DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system
must also use DQ2 to determine which sectors are
erasing or erase-suspended. Alternatively, the system
can use DQ7 (see the subsection on DQ7: Data# Polling).
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 µs after the program
command sequence is written, then returns to reading
array data.
Toggle Bit
= Toggle?
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Note: The system should recheck the toggle bit even if DQ5
= “1” because the toggle bit may stop toggling as DQ5
changes to “1.” See the subsections on DQ6 and DQ2 for
more information.
Figure 6.
32
No
Am29DL642G
Toggle Bit Algorithm
June 10, 2005
P R E L I M I N A R Y
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform
other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to determine the status of the operation (top of Figure 6).
DQ5: Exceeded Timing Limits
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and
mode information. Refer to Table 14 to compare outputs for DQ2 and DQ6.
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under these
conditions DQ5 produces a “1,” indicating that the program
or erase cycle was not successfully completed.
Figure 6 shows the toggle bit algorithm in flowchart
form, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the DQ6: Toggle Bit I subsection.
Figure 20 shows the toggle bit timing diagram. Figure
21 shows the differences between DQ2 and DQ6 in
graphical form.
Under both these conditions, the system must write
the reset command to return to the read mode (or to
the erase-suspend-read mode if a bank was previously in the erase-suspend-program mode).
Reading Toggle Bits DQ6/DQ2
Refer to Figure 6 for the following discussion. Whenever the system initially begins reading toggle bit status, it must read DQ15–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically,
the system would note and store the value of the toggle bit after the first read. After the second read, the
system would compare the new value of the toggle bit
with the first. If the toggle bit is not toggling, the device
has completed the program or erase operation. The
system can read array data on DQ15–DQ0 on the following read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the device did not completed the operation successfully, and
the system must write the reset command to return to
reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor
June 10, 2005
The device may output a “1” on DQ5 if the system tries
to program a “1” to a location that was previously programmed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the timing limit
has been exceeded, DQ5 produces a “1.”
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not
erasure has begun. (The sector erase timer does not
apply to the chip erase command.) If additional
sectors are selected for erasure, the entire time-out
also applies after each additional sector erase command. When the time-out period is complete, DQ3
switches from a “0” to a “1.” If the time between additional sector erase commands from the system can be
assumed to be less than 50 µs, the system need not
monitor DQ3. See also the Sector Erase Command
Sequence section.
After the sector erase command is written, the system
should read the status of DQ7 (Data# Polling) or DQ6
(Toggle Bit I) to ensure that the device has accepted
the command sequence, and then read DQ3. If DQ3 is
“1,” the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored
until the erase operation is complete. If DQ3 is “0,” the
device will accept additional sector erase commands.
To ensure the command has been accepted, the system software should check the status of DQ3 prior to
and following each subsequent sector erase command. If DQ3 is high on the second status check, the
last command might not have been accepted.
Table 14 shows the status of DQ3 relative to the other
status bits.
Am29DL642G
33
P R E L I M I N A R Y
Table 14.
Standard
Mode
Erase
Suspend
Mode
Status
Embedded Program Algorithm
Embedded Erase Algorithm
Erase
Erase-Suspend- Suspended Sector
Read
Non-Erase
Suspended Sector
Erase-Suspend-Program
Write Operation Status
DQ7
(Note 2)
DQ7#
0
DQ6
Toggle
Toggle
DQ5
(Note 1)
0
0
DQ3
N/A
1
DQ2
(Note 2)
No toggle
Toggle
RY/BY#
0
0
1
No toggle
0
N/A
Toggle
1
Data
Data
Data
Data
Data
1
DQ7#
Toggle
0
N/A
N/A
0
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
Refer to the section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further
details.
3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm
is in progress. The device outputs array data if the system addresses a non-busy bank.
34
Am29DL642G
June 10, 2005
P R E L I M I N A R Y
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C
20 ns
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –65°C to +125°C
+0.8 V
Voltage with Respect to Ground
–0.5 V
VCC (Note 1) . . . . . . . . . . . . . . . . . –0.5 V to +4.0 V
A9, OE#, and RESET#
(Note 2) . . . . . . . . . . . . . . . . . . . . –0.5 V to +12.5 V
20 ns
–2.0 V
20 ns
WP#/ACC . . . . . . . . . . . . . . . . . . –0.5 V to +10.5 V
All other pins (Note 1) . . . . . . –0.5 V to VCC +0.5 V
Figure 7. Maximum Negative
Overshoot Waveform
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V.
During voltage transitions, input or I/O pins may
overshoot V SS to –2.0 V for periods of up to 20 ns.
Maximum DC voltage on input or I/O pins is VCC +0.5 V.
See Figure 7. During voltage transitions, input or I/O pins
may overshoot to VCC +2.0 V for periods up to 20 ns. See
Figure 8.
2. Minimum DC input voltage on pins A9, OE#, RESET#,
and WP#/ACC is –0.5 V. During voltage transitions, A9,
OE#, WP#/ACC, and RESET# may overshoot V SS to
–2.0 V for periods of up to 20 ns. See Figure 7. Maximum
DC input voltage on pin A9 is +12.5 V which may
overshoot to +14.0 V for periods up to 20 ns. Maximum
DC input voltage on WP#/ACC is +9.5 V which may
overshoot to +12.0 V for periods up to 20 ns.
20 ns
VCC
+2.0 V
VCC
+0.5 V
2.0 V
20 ns
20 ns
Figure 8. Maximum Positive
Overshoot Waveform
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This
is a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.
OPERATING RANGES
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C
Extended (E) Devices
Ambient Temperature (TA) . . . . . . . . –55°C to +125°C
VCC Supply Voltages
VCC for standard voltage range . . . . . . . 2.7 V to 3.6 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
June 10, 2005
Am29DL642G
35
P R E L I M I N A R Y
DC CHARACTERISTICS
CMOS Compatible
Parameter
Symbol
Parameter Description
Test Conditions
Min
ILI
Input Load Current
VIN = VSS to VCC,
VCC = VCC max
ILIT
A9 Input Load Current
VCC = VCC max; A9 = 12.5 V
ILO
Output Leakage Current
VOUT = VSS to VCC,
VCC = VCC max
ICC1
VCC Active Read Current
(Notes 1, 2)
CE# = VIL, OE# = VIH
ICC2
Typ
Max
Unit
±1.0
µA
35
µA
±1.0
µA
mA
5 MHz
10
16
1 MHz
2
4
VCC Active Write Current
(Notes 1, 2, 3)
CE# = VIL, OE# = VIH, WE# = VIL
15
30
mA
ICC3
VCC Standby Current (Note 2)
CE#, RESET# = VCC ± 0.3 V
0.2
10
µA
ICC4
VCC Reset Current (Note 2)
RESET# = VSS ± 0.3 V
0.2
10
µA
ICC5
Automatic Sleep Mode (Notes 2, 4)
VIH = VCC ± 0.3 V;
VIL = VSS ± 0.3 V
0.2
10
µA
ICC6
VCC Active Read-While-Program
Current (Notes 1, 2)
CE# = VIL, OE# = VIH
21
45
mA
ICC7
VCC Active Read-While-Erase
Current (Notes 1, 2)
CE# = VIL, OE# = VIH
21
45
mA
ICC8
VCC Active
Program-While-Erase-Suspended
Current (Notes 2, 5)
CE# = VIL, OE# = VIH
17
35
mA
VIL
Input Low Voltage
–0.5
0.8
V
VIH
Input High Voltage
0.7 x VCC
VCC + 0.3
V
VHH
Voltage for WP#/ACC Sector
Protect/Unprotect and Program
Acceleration
VCC = 3.0 V ± 10%
8.5
9.5
V
VID
Voltage for Autoselect and
Temporary Sector Unprotect
VCC = 3.0 V ± 10%
11.5
12.5
V
VOL
Output Low Voltage
IOL = 4.0 mA, VCC = VCC min
0.45
V
VOH1
VOH2
VLKO
Output High Voltage
IOH = –2.0 mA, VCC = VCC min
0.85 VCC
IOH = –100 µA, VCC = VCC min
VCC–0.4
Low VCC Lock-Out Voltage (Note 5)
2.3
V
2.5
V
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH, one die active at a time.
2. Maximum ICC specifications are tested with VCC = VCCmax.
3. ICC active while Embedded Erase or Embedded Program is in progress.
4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is
200 nA.
5. Not 100% tested.
36
Am29DL642G
June 10, 2005
P R E L I M I N A R Y
DC CHARACTERISTICS
Zero-Power Flash
Supply Current in mA
25
20
15
10
5
0
0
500
1000
1500
2000
2500
3000
3500
4000
Time in ns
Note: Addresses are switching at 1 MHz
Figure 9.
ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
12
3.6 V
10
2.7 V
Supply Current in mA
8
6
4
2
0
1
2
3
Note: T = 25 °C
Figure 10.
June 10, 2005
4
5
Frequency in MHz
Typical ICC1 vs. Frequency
Am29DL642G
37
P R E L I M I N A R Y
TEST CONDITIONS
Table 15.
3.3 V
Test Condition
2.7 kΩ
Device
Under
Test
CL
Test Specifications
6.2 kΩ
70, 90
Output Load
1 TTL gate
Output Load Capacitance, CL
(including jig capacitance)
30
pF
Input Rise and Fall Times
5
ns
0.0–3.0
V
Input timing measurement
reference levels
1.5
V
Output timing measurement
reference levels
1.5
V
Input Pulse Levels
Note: Diodes are IN3064 or equivalent
Figure 11.
Unit
Test Setup
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
3.0 V
Input
Don’t Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State (High Z)
1.5 V
Measurement Level
1.5 VIO
Output
0.0 V
Figure 12.
38
Input Waveforms and Measurement Levels
Am29DL642G
June 10, 2005
P R E L I M I N A R Y
AC CHARACTERISTICS
Read-Only Operations
Parameter
JEDEC
Std.
Description
Test Setup
70
90
Unit
tAVAV
tRC
Read Cycle Time (Note 1)
Min
70
90
ns
tAVQV
tACC
Address to Output Delay (Note 3)
CE# or CE2#,
OE# = VIL
Max
70
90
ns
tELQV
tCE
Chip Enable to Output Delay
OE# = VIL
Max
70
90
ns
tGLQV
tOE
Output Enable to Output Delay
Max
30
35
ns
tEHQZ
tDF
Chip Enable to Output High Z (Notes 1, 4)
Max
16
ns
tGHQZ
tDF
Output Enable to Output High Z (Notes 1, 4)
Max
16
ns
tAXQX
tOH
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First
Min
0
ns
Read
Output Enable Hold Time (Note
Toggle and
1)
Data# Polling
Min
0
ns
tOEH
Min
10
ns
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 15 for test specifications
3. CE# and CE2# must not be driven low simultaneously.
4. Measurements performed by placing a 50 ohm termination on the data pin with a bias of VCC/2. The time from OE# high to
the data bus driven to VCC/2 is taken as tDF
.
tRC
Addresses Stable
Addresses
tACC
CE# or CE2#
tRH
tRH
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0V
Figure 13.
June 10, 2005
Read Operation Timings
Am29DL642G
39
P R E L I M I N A R Y
AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
JEDEC
Std
Description
70, 90
Unit
tReady
RESET# Pin Low (During Embedded Algorithms)
to Read Mode (See Note)
Max
20
µs
tReady
RESET# Pin Low (NOT During Embedded
Algorithms) to Read Mode (See Note)
Max
500
ns
tRP
RESET# Pulse Width
Min
500
ns
tRH
Reset High Time Before Read (See Note)
Min
50
ns
tRPD
RESET# Low to Standby Mode
Min
20
µs
tRB
RY/BY# Recovery Time
Min
0
ns
Note: Not 100% tested.
RY/BY#
CE# or CE2#, OE#
tRH
RESET#
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE# or CE2#, OE#
RESET#
tRP
Figure 14.
40
Reset Timings
Am29DL642G
June 10, 2005
P R E L I M I N A R Y
AC CHARACTERISTICS
Erase and Program Operations
Parameter
JEDEC
Std
Description
tAVAV
tWC
Write Cycle Time (Note 1)
Min
tAVWL
tAS
Address Setup Time
Min
0
ns
tASO
Address Setup Time to OE# low during toggle bit polling
Min
15
ns
tAH
Address Hold Time
Min
tAHT
Address Hold Time From CE# or OE# high
during toggle bit polling
Min
tDVWH
tDS
Data Setup Time
Min
tWHDX
tDH
Data Hold Time
Min
0
ns
tOEPH
Output Enable High during toggle bit polling
Min
20
ns
tGHWL
tGHWL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
tELWL
tCS
CE# or CE#2 Setup Time
Min
0
ns
tWHEH
tCH
CE# or CE#2 Hold Time
Min
0
ns
tWLWH
tWP
Write Pulse Width
Min
tWHDL
tWPH
Write Pulse Width High
Min
30
ns
tSR/W
Latency Between Read and Write Operations
Min
0
ns
tWLAX
70
90
Unit
70
90
ns
40
45
0
40
ns
45
30
ns
35
ns
ns
tWHWH1
tWHWH1
Programming Operation (Note 2)
Typ
7
µs
tWHWH1
tWHWH1
Accelerated Programming Operation (Note 2)
Typ
4
µs
tWHWH2
tWHWH2
Sector Erase Operation (Note 2)
Typ
0.4
sec
tVCS
VCC Setup Time (Note 1)
Min
50
µs
tRB
Write Recovery Time from RY/BY#
Min
0
ns
Program/Erase Valid to RY/BY# Delay
Max
90
ns
tBUSY
Notes:
1. Not 100% tested.
2. See the “Erase And Programming Performance” section for more information.
June 10, 2005
Am29DL642G
41
P R E L I M I N A R Y
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
tAS
tWC
Addresses
Read Status Data (last two cycles)
555 h
PA
PA
PA
tAH
CE# or CE2#
tCH
OE#
tWHWH1
tWP
WE#
tWPH
tCS
tDS
tDH
PD
A0h
Data
Status
tBUSY
DOUT
tRB
RY/BY#
VCC
tVCS
Note: PA = program address, PD = program data, DOUT is the true data at the program address.
Figure 15.
Program Operation Timings
VHH
WP#/ACC
VIL or VIH
VIL or VIH
tVHH
Figure 16.
42
tVHH
Accelerated Program Timing Diagram
Am29DL642G
June 10, 2005
P R E L I M I N A R Y
AC CHARACTERISTICS
Erase Command Sequence (last two cycles)
tAS
tWC
2AAh
Addresses
Read Status Data
VA
SA
VA
555 h for chip erase
tAH
CE# or CE2#
tCH
OE#
tWP
WE#
tWPH
tCS
tWHWH2
tDS
tDH
Data
55h
In
Progress
30h
Complete
10 for Chip Erase
tBUSY
tRB
RY/BY#
tVCS
VCC
Notes: SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”.)
Figure 17.
June 10, 2005
Chip/Sector Erase Operation Timings
Am29DL642G
43
P R E L I M I N A R Y
AC CHARACTERISTICS
Addresses
tWC
tWC
tRC
Valid PA
Valid RA
tWC
Valid PA
Valid PA
tAH
tCPH
tACC
tCE
CE2# or CE#
tCP
tOE
OE#
tOEH
tGHWL
tWP
WE#
tDF
tWPH
tDS
tOH
tDH
Valid
Out
Valid
In
Data
Valid
In
Valid
In
tSR/W
WE# Controlled Write Cycle
Read Cycle
Figure 18.
CE# or CE2# Controlled Write Cycles
Back-to-back Read/Write Cycle Timings
tRC
Addresses
VA
VA
VA
tACC
tCE
CE# or CE2#
tCH
tOE
OE#
tOEH
tDF
WE#
tOH
High Z
DQ7
Complement
Complement
DQ0–DQ6
Status Data
Status Data
True
Valid Data
High Z
True
Valid Data
tBUSY
RY/BY#
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
Figure 19.
44
Data# Polling Timings (During Embedded Algorithms)
Am29DL642G
June 10, 2005
P R E L I M I N A R Y
AC CHARACTERISTICS
tAHT
tAS
Addresses
tAHT
tASO
CE# or CE2#
tCEPH
tOEH
WE#
tOEPH
OE#
tDH
DQ6/DQ2
tOE
Valid Data
Valid
Status
Valid
Status
Valid
Status
(first read)
(second read)
(stops toggling)
Valid Data
RY/BY#
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status
read cycle, and array data read cycle
Figure 20.
Enter
Embedded
Erasing
WE#
Erase
Suspend
Erase
Toggle Bit Timings (During Embedded Algorithms)
Enter Erase
Suspend Program
Erase Suspend
Read
Erase
Suspend
Program
Erase
Resume
Erase Suspend
Read
Erase
Erase
Complete
DQ6
DQ2
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle
DQ2 and DQ6.
Figure 21.
June 10, 2005
DQ2 vs. DQ6
Am29DL642G
45
P R E L I M I N A R Y
AC CHARACTERISTICS
Temporary Sector Unprotect
Parameter
JEDEC
Std
Description
All Speed Options
Unit
tVIDR
VID Rise and Fall Time (See Note)
Min
500
ns
tVHH
VHH Rise and Fall Time (See Note)
Min
250
ns
tRSP
RESET# Setup Time for Temporary Sector
Unprotect
Min
4
µs
tRRB
RESET# Hold Time from RY/BY# High for
Temporary Sector Unprotect
Min
4
µs
Note: Not 100% tested.
VID
RESET#
VID
VSS, VIL,
or VIH
VSS, VIL,
or VIH
tVIDR
tVIDR
Program or Erase Command Sequence
CE# or CE2#
WE#
tRRB
tRSP
RY/BY#
Figure 22.
46
Temporary Sector Unprotect Timing Diagram
Am29DL642G
June 10, 2005
P R E L I M I N A R Y
AC CHARACTERISTICS
VID
VIH
RESET#
SA, A6,
A1, A0
Valid*
Valid*
Sector Group Protect/Unprotect
Data
60h
60h
Valid*
Verify
40h
Status
1 µs
CE# or CE2#
Sector Group Protect: 150 µs
Sector Group Unprotect: 15 ms
WE#
OE#
* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
Figure 23. Sector/Sector Block Protect and
Unprotect Timing Diagram
June 10, 2005
Am29DL642G
47
P R E L I M I N A R Y
AC CHARACTERISTICS
Alternate CE# Controlled Erase and Program Operations
Parameter
Speed Options
JEDEC
Std.
Description
70
90
Unit
tAVAV
tWC
Write Cycle Time (Note 1)
Min
70
90
ns
tAVWL
tAS
Address Setup Time
Min
tELAX
tAH
Address Hold Time
Min
40
45
ns
tDVEH
tDS
Data Setup Time
Min
40
45
ns
tEHDX
tDH
Data Hold Time
Min
0
ns
tGHEL
tGHEL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
tWLEL
tWS
WE# Setup Time
Min
0
ns
tEHWH
tWH
WE# Hold Time
Min
0
ns
tELEH
tCP
CE# Pulse Width
Min
tEHEL
tCPH
CE# Pulse Width High
Min
30
ns
tWHWH1
tWHWH1
Programming Operation (Note 2)
Typ
7
µs
tWHWH1
tWHWH1
Accelerated Programming Operation (Note 2)
Typ
4
µs
tWHWH2
tWHWH2
Sector Erase Operation (Note 2)
Typ
0.4
sec
0
40
ns
45
ns
Notes:
1. Not 100% tested.
2. See the “Erase And Programming Performance” section for more information.
48
Am29DL642G
June 10, 2005
P R E L I M I N A R Y
AC CHARACTERISTICS
555 for program
2AA for erase
PA for program
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tAS
tAH
tWH
WE#
tGHEL
OE#
tWHWH1 or 2
tCP
CE# or CE2#
tWS
tCPH
tBUSY
tDS
tDH
DQ7#
Data
tRH
A0 for program
55 for erase
DOUT
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device..
Figure 24.
June 10, 2005
Alternate CE# Controlled Write (Erase/Program) Operation Timings
Am29DL642G
49
P R E L I M I N A R Y
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ (Note 1)
Max (Note 2)
Unit
Comments
Sector Erase Time
0.4
5
sec
Chip Erase Time
56
Excludes 00h programming
prior to erasure (Note 4)
Accelerated Word Program Time
4
120
µs
Word Program Time
7
210
µs
Chip Program Time (Note 3)
28
84
sec
sec
Excludes system level
overhead (Note 5)
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table
13 for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Description
Min
Max
Input voltage with respect to VSS on all pins except I/O pins
(including A9, OE#, and RESET#)
–1.0 V
12.5 V
Input voltage with respect to VSS on all I/O pins
–1.0 V
VCC + 1.0 V
–100 mA
+100 mA
VCC Current
Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.
DATA RETENTION
Parameter Description
Test Conditions
Min
Unit
150°C
10
Years
125°C
20
Years
Minimum Pattern Data Retention Time
50
Am29DL642G
June 10, 2005
P R E L I M I N A R Y
PHYSICAL DIMENSIONS
FSD063—63-Ball Fine-Pitch Ball Grid Array (FBGA) 10.95 x 11.95 mm package
A
D
0.15 C
D1
eD
(2X)
8
7
SE 7
6
5
4
E
E1
3
eE
2
1
M
INDEX MARK
PIN A1
CORNER
L
K
B
10
TOP VIEW
J
H
G
F
E
D C B
A
7
SD
0.15 C
PIN A1
CORNER
(2X)
BOTTOM VIEW
0.20 C
A A2
A1
C
63X
0.08 C
SIDE VIEW
6
b
0.15 M C A B
0.08 M C
NOTES:
PACKAGE
FSD 063
1.
DIMENSIONING AND TOLERANCING METHODS PER ASME
Y14.5M-1994.
10.95 mm x 11.95 mm
2.
ALL DIMENSIONS ARE IN MILLIMETERS.
PACKAGE
3.
BALL POSITION DESIGNATION PER JESD 95-1, SPP-010.
JEDEC
N/A
SYMBOL
MIN
NOM
MAX
A
---
---
1.40
A1
0.25
---
---
A2
1.00
---
1.10
NOTE
PROFILE
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E"
DIRECTION.
BODY SIZE
E
10.95 BSC.
BODY SIZE
D1
8.80 BSC.
MATRIX FOOTPRINT
E1
5.60 BSC.
MATRIX FOOTPRINT
MD
12
MATRIX SIZE D DIRECTION
ME
8
MATRIX SIZE E DIRECTION
63
0.30
0.35
SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"
DIRECTION.
BALL HEIGHT
11.95 BSC.
n
e REPRESENTS THE SOLDER BALL GRID PITCH.
5.
BODY THICKNESS
D
φb
4.
n IS THE NUMBER OF POPULATED
SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME.
6
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
BALL COUNT
0.40
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = 0.000.
BALL DIAMETER
eE
0.80 BSC.
BALL PITCH
eD
0.80 BSC.
BALL PITCH
0.40 BSC.
SOLDER BALL PLACEMENT
8.
"+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
DEPOPULATED SOLDER BALLS
9.
NOT USED.
SD / SE
A3,A4,A5,A6,B2,B3,B4,B5,B6
C1,C8,D1,D8,E1,E8,F1,F8
G1,G8,H1,H8,J1,J8,K1,K8
L3,L4,L5,L6,M3,M4,M5,M6
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE
OUTER ROW, SD OR SE = e/2
10. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3224 \ 16-038.14b
June 10, 2005
Am29DL642G
51
P R E L I M I N A R Y
REVISION SUMMARY
Revision A (June 12, 2002)
AC Characteristics
Initial release.
Read-only Operations: Changed tDF from 30 to 16 ns,
and t OE from 35 to 30 ns. Added note reference to
tACC.
Revision B (August 27, 2002)
Global
Changed speed rating from 90 ns to 70 ns. Deleted
references and data related to byte mode.
Erase and Program Operations: Changed tAH and tDS
from 45 to 40 ns, and tWP from 35 to 30 ns.
Physical Dimensions
Ordering Information
Added FSD063 package drawing.
Added FSD063 package drawing and part number
designator.
Revision B+1 (September 5, 2002)
Global
Common Flash Interface (CFI)
In 3rd paragraph, corrected last sentence to indicate
that after a reset command, device returns to reading
array data, not autoselect mode.
Added 90 ns speed option.
DC Characteristics
Deleted IACC parameter from table.
DC Characteristics
Changed maximum current for ICC3, ICC4, ICC5 to 10 mA.
In Note 1, indicated that specification is for one die active at a time.
Revision B+2 (June 10, 2005)
Modified disclaimers
Trademarks
Copyright ©2002-2005 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
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June 10, 2005