ISL22419 ® Single Digitally Controlled Potentiometer (XDCP™) Data Sheet June 28, 2006 Low Noise, Low Power, SPI® Bus, 128 Taps, Wiper Only Features The ISL22419 integrates a single digitally controlled potentiometer (DCP) and non-volatile memory on a monolithic CMOS integrated circuit. • SPI serial interface FN6311.0 • 128 resistor taps • Non-volatile storage of wiper position • Wiper resistance: 70Ω typical @ 3.3V The digitally controlled potentiometer is implemented with a combination of resistor elements and CMOS switches. The position of the wiper is controlled by the user through the SPI serial interface. The potentiometer has an associated volatile Wiper Register (WR) and a non-volatile Initial Value Register (IVR) that can be directly written to and read by the user. The contents of the WR controls the position of the wiper. At power-up the device recalls the content of the DCP’s IVR to the WR. The DCP can be used as a voltage divider in a wide variety of applications including control, parameter adjustments, AC measurement and signal processing. • Shutdown mode • Shutdown current 5µA max • Power supply: 2.7V to 5.5V • 50kΩ or 10kΩ total resistance • High reliability - Endurance: 1,000,000 data changes per bit per register - Register data retention: 50 years @ T ≤ 55 °C • 8 Lead MSOP • Pb-free plus anneal product (RoHS compliant) Pinout ISL22419 (8 LD MSOP) TOP VIEW SCK 1 8 SDO 2 Vcc 7 RW SDI 3 6 SHDN CS 4 5 GND Ordering Information PART NUMBER PART MARKING RESISTANCE OPTION (kΩ) TEMP. RANGE (°C) PACKAGE PKG. DWG. # ISL22419UFU8Z (Notes 1, 2) 419UZ 50 -40 to +125 8 Ld MSOP (Pb-Free) M8.118 ISL22419WFU8Z (Notes 1, 2) 419WZ 10 -40 to +125 8 Ld MSOP (Pb-Free) M8.118 NOTES: 1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. Add “-TK” suffix for 1,000 Tape and Reel option 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL22419 Block Diagram VCC SCK SDO SPI INTERFACE SDI CS POWER UP INTERFACE, CONTROL AND STATUS LOGIC WR RW NON-VOLATILE REGISTERS SHDN GND Pin Descriptions MSOP PIN SYMBOL 1 SCK SPI interface clock input 2 SDO Open Drain Data Output of the SPI serial interface 3 SDI Data Input of the SPI serial interface 4 CS Chip Select active low input 5 GND 6 SHDN 7 RW “Wper” terminal of DCP 8 VCC Power supply pin 2 DESCRIPTION Device ground pin Shutdown active low input FN6311.0 June 28, 2006 ISL22419 Absolute Maximum Ratings Thermal Information Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Voltage at any Digital Interface Pin with Respect to GND . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC+0.3 VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V Voltage at any DCP pin with Respect to GND . . . . . . . -0.3V to VCC Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . . 300°C IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA Latchup (Note 4) . . . . . . . . . . . . . . . . . . Class II, Level B @+125°C ESD (HBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5kV (CDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1kV Thermal Resistance (Typical, Note 3) θJA (°C/W) 8 Lead MSOP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Maximum Junction Temperature (Plastic Package). . . . . . . . . .150°C Recommended Operating Conditions Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 125°C VCC Voltage for DCP Operation . . . . . . . . . . . . . . . . . . 2.7V to 5.5V Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -3mA to 3mA Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 3. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 4. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: using a max positive pulse of 6.5V on the SHDN pin, and using a max negative pulse of -1V for all pins. Analog Specifications SYMBOL RTOTAL Over recommended operating conditions unless otherwise stated. PARAMETER End-to-End Resistance TEST CONDITIONS RW (Note 14) Wiper Resistance CW (Note 14) Wiper Capacitance ILkgRW Leakage on RW Pin TYP (NOTE 5) MAX UNIT W option 10 kΩ U option 50 kΩ End-to-End Resistance Tolerance End-to-End Temperature Coefficient MIN -20 +20 % W option ±50 ppm/°C (Note 14) U option ±80 ppm/°C (Note 14) VCC = 3.3V @ 25°C, wiper current = VCC/RTOTAL 70 Ω 25 pF Voltage at pin from GND to VCC 2 4 µA -1 1 LSB (Note 6) -0.5 0.5 LSB (Note 6) LSB (Note 6) VOLTAGE DIVIDER MODE ( measured at RW, unloaded) INL (Note 10) Integral Non-linearity DNL (Note 9) Differential Non-linearity Monotonic over all tap positions ZSerror (Note 7) Zero-scale Error W option 0 1 5 U option 0 0.5 2 FSerror (Note 8) Full-scale Error W option -5 -1 0 U option -2 -1 0 TCV Ratiometric Temperature Coefficient (Notes 11, 14) 3 DCP register set to 40 hex ±4 LSB (Note 6) ppm/°C FN6311.0 June 28, 2006 ISL22419 Operating Specifications Over the recommended operating conditions unless otherwise specified. SYMBOL ICC1 ICC2 ISB ISD ILkgDig PARAMETER TEST CONDITIONS MIN TYP (NOTE 5) MAX UNIT VCC Supply Current (volatile write/read) 10k DCP, fSPI = 5MHz; (for SPI active, read and write states) 1 mA VCC Supply Current (volatile write/read) 50k DCP, fSPI = 5MHz; (for SPI active, read and write states) 0.5 mA VCC Supply Current ( non-volatile write/read) 10k DCP, fSPI = 5MHz; (for SPI active, read and write states) 3.2 mA VCC Supply Current ( non-volatile write/read) 50k DCP, fSPI = 5MHz; (for SPI active, read and write states) 2.7 mA VCC Current (standby) VCC = +5.5V, 10k DCP, SPI interface in standby state 850 µA VCC = +5.5V, 50k DCP, SPI interface in standby state 160 µA VCC = +3.6V, 10k DCP, SPI interface in standby state 550 µA VCC = +3.6V, 50k DCP, SPI interface in standby state 100 µA VCC = +5.5V @ +85°C, SPI interface in standby state 3 µA VCC = +5.5V@ +125°C, SPI interface in standby state 5 µA VCC = +3.6V @ +85°C, SPI interface in standby state 2 µA VCC = +3.6V @ +125°C, SPI interface in standby state 4 µA 1 µA VCC Current (shutdown) Leakage Current, at Pins SHDN, SCK, Voltage at pin from GND to VCC SDI, SDO and CS -1 tWRT (Note 14) Wiper Response Time Wiper Response Time after SPI write to WR register 1.5 µs tShdnRec (Note 14) DCP Recall Time from Shutdown Mode From rising edge of SHDN signal to wiper stored position and RH connection 1.5 µs SCK rising edge of last bit of ACR data byte to wiper stored position and RH connection 1.5 µs Vpor Power-on Recall Voltage VCC Ramp VCC Ramp Rate tD Power-up Delay Minimum VCC at which memory recall occurs 2.0 2.6 0.2 V V/ms 3 VCC above Vpor, to DCP Initial Value Register recall completed, and SPI Interface in standby state ms EEPROM SPECIFICATION EEPROM Endurance tWC (Note 12) EEPROM Retention Temperature T ≤ 55 °C Non-volatile Write Cycle Time From rising edge of CS 1,000,000 Cycles 50 Years 12 20 ms SERIAL INTERFACE SPECIFICATIONS VIL SHDN, SCK, SDI, and CS Input Buffer LOW Voltage -0.3 0.3*VCC V VIH SHDN, SCK, SDI, and CS Input Buffer HIGH Voltage 0.7*VCC VCC+0.3 V 4 FN6311.0 June 28, 2006 ISL22419 Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued) SYMBOL PARAMETER Hysteresis SHDN, SCK, SDI, and CS Input Buffer Hysteresis VOL TEST CONDITIONS MIN TYP (NOTE 5) MAX UNIT 0.05* VCC SDO Output Buffer LOW Voltage IOL = 4mA Rpu (Note 13) SDO Pull-up Resistor Off-chip Maximum is determined by tRO and tFO with maximum bus load Cbus = 30pF, fSCK = 5MHz Cpin (Note 14) 0.4 V 2 kΩ SHDN, SCK, SDI, SDO and CS Pin Capacitance 10 pF fSCK SPI Frequency 5 MHz tCYC SPI Clock Cycle Time 200 ns tWH SPI Clock High Time 100 ns tWL SPI Clock Low Time 100 ns tLEAD Lead Time 250 ns tLAG Lag Time 250 ns tSU SDI, SCK and CS Input Setup Time 50 ns tH SDI, SCK and CS Input Hold Time 50 ns tRI SDI, SCK and CS Input Rise Time 10 ns tFI SDI, SCK and CS Input Fall Time 10 20 ns SDO Output Disable Time 0 100 ns 350 ns tDIS 0 V tV SDO Output Valid Time tHO SDO Output Hold Time tRO SDO Output Rise Time Rpu = 2k, Cbus = 30pF 60 ns tFO SDO Output Fall Time Rpu = 2k, Cbus = 30pF 60 ns tCS CS Deselect Time 0 ns 2 µs Notes: 5. Typical values are for TA = 25°C and 3.3V supply voltage. 6. LSB: [V(RW)127 – V(RW)0]/127. V(RW)127 and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 7. ZS error = V(RW)0/LSB. 8. FS error = [V(RW)127 – VCC]/LSB. 9. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 127. i is the DCP register setting. 10. INL = [V(RW)i – (i • LSB) – V(RW)0]/LSB for i = 1 to 127 Max ( V ( RW ) i ) – Min ( V ( RW ) i ) 10 6 11. TC = --------------------------------------------------------------------------------------------- × ----------------- for i = 16 to 127 decimal, T = -40°C to 125°C. Max( ) is the maximum value of the wiper V [ Max ( V ( RW ) i ) + Min ( V ( RW ) i ) ] ⁄ 2 165°C voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range. 12. tWC is the time from the end of a Write sequence of SPI serial interface, to the end of the self-timed internal non-volatile write cycle. 13. Rpu is specified for the highest data rate transfer for the device. Higher value pullup can be used at lower data rates. 14. This parameter is not 100% tested. 5 FN6311.0 June 28, 2006 ISL22419 Timing Diagrams Input Timing tCS CS tCYC tLEAD SCK tSU tH ... tWL tRI tFI tWH ... MSB SDI tLAG LSB High Impedance SDO Output Timing CS SCK tV tDIS ... MSB SDO SDI ... tHO LSB ADDR XDCP Timing (for All Load Instructions) CS tWC SCK SDI ... MSB ... tWRT LSB VW SDO High Impedance 6 FN6311.0 June 28, 2006 ISL22419 Typical Performance Curves VCC 100 1.2 80 T =125ºC 70 1 VCC 60 0.8 Isb (µA) WIPER RESISITANCE (Ω) 1.4 Vcc = 3.3V, T = 125ºC 90 50 40 0.6 30 0.4 Vcc = 3.3V, T = -40ºC Vcc = 3.3V, T = 20ºC 20 T =25ºC 10 0.2 0 0 0 20 40 60 80 100 120 2.7 3.2 3.7 4.2 TAP POSITION (DECIMAL) FIGURE 1. WIPER RESISTANCE vs TAP POSITION [ I(RW) = VCC/RTOTAL ] FOR 10kΩ (W) 5.2 FIGURE 2. STANDBY ICC vs VCC 0.2 0.2 Vcc = 2.7V T = 25ºC T = 25ºC Vcc = 2.7V 0.1 INL (LSB) 0.1 DNL (LSB) 4.7 Vcc, V 0 0 -0.1 -0.1 Vcc = 5.5V Vcc = 5.5V -0.2 -0.2 0 20 40 60 80 100 0 120 20 40 FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10kΩ (W) 120 FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10kΩ (W) 10k 1.10 -0.30 0.90 Vcc = 2.7V 0.70 Vcc = 2.7V Vcc = 5.5V 0.30 0.10 -20 0 20 40 60 80 TEMPERATURE (ºC) FIGURE 5. ZSerror vs TEMPERATURE 7 50k Vcc = 5.5V -0.60 -0.90 10k -1.20 50k -0.10 FSerror (LSB) ZSerror (LSB) 100 0.00 1.30 -0.30 -40 80 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) 0.50 60 100 120 -1.50 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (ºC) FIGURE 6. FSerror vs TEMPERATURE FN6311.0 June 28, 2006 ISL22419 (Continued) 1.00 105 50k Vcc = 2.7V 90 0.50 0.00 -0.50 Vcc = 5.5V -1.00 -40 10k 75 TCv (ppm/°C) END TO END RTOTAL CHANGE (%) Typical Performance Curves 10k 60 45 30 50k 15 0 -20 0 20 40 60 80 100 TEMPERATURE (ºC) FIGURE 7. END TO END RTOTAL % CHANGE vs TEMPERATURE FIGURE 9. MIDSCALE GLITCH, CODE 80h TO 7Fh 8 120 16 36 56 76 96 TAP POSITION (DECIM AL) FIGURE 8. TC FOR VOLTAGE DIVIDER MODE IN ppm FIGURE 10. LARGE SIGNAL SETTLING TIME FN6311.0 June 28, 2006 ISL22419 Pin Description Potentiometer Pins RW RW is the wiper terminal and is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the WR register. SHDN The SHDN pin forces the resistor to end-to-end open circuit condition and shorts RW to GND. When SHDN is returned to logic high, the previous latch settings put RW at the same resistance setting prior to shutdown. This pin is logically OR’d with SHDN bit in ACR register. SPI interface is still available in shutdown mode and all registers are accessible. This pin must remain HIGH for normal operation. RW FIGURE 11. DCP CONNECTION IN SHUTDOWN MODE Bus Interface Pins Serial Clock (SCK) This is the serial clock input of the SPI serial interface. Serial Data Output (SDO) The SDO is an open drain serial data output pin. During a read cycle, the data bits are shifted out at the falling edge of the serial clock SCK, while the CS input is low. SDO requires an external pull-up resistor for proper operation. Serial Data Input (SDI) The SDI is the serial data input pin for the SPI interface. It receives device address, operation code, wiper address and data from the SPI external host device. The data bits are shifted in at the rising edge of the serial clock SCK, while the CS input is low. Chip Select (CS) CS LOW enables the ISL22419, placing it in the active power mode. A HIGH to LOW transition on CS is required prior to the start of any operation after power up. When CS is HIGH, the ISL22419 is deselected and the SDO pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. SPI serial interface providing direct communication between host and potentiometer and memory. The resistor array is comprised of individual resistors connected in series. At either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. The electronic switches on the device operate in a “make before break” mode when the wiper changes tap positions. When the device is powered down, the last value stored in IVR will be maintained in the non-volatile memory. When power is restored, the contents of the IVR is recalled and loaded into the WR to set the wiper to the initial value. DCP Description The DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of each DCP are equivalent to the fixed terminals of a mechanical potentiometer and internally connected to VCC and GND. The RW pin of the DCP is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal within the DCP is controlled by an 7-bit volatile Wiper Register (WR). When the WR of a DCP contains all zeroes (WR[6:0]: 00h), its wiper terminal (RW) is closest to GND. When the WR register of a DCP contains all ones (WR[6:0]: 7Fh), its wiper terminal (RW) is closest to VCC. As the value of the WR increases from all zeroes (0) to all ones (127 decimal), the wiper moves monotonically from the position closest to GND to the closest to VCC. While the ISL22419 is being powered up, the WR is reset to 40h (64 decimal), which locates RW roughly at the center between GND and VCC. After the power supply voltage becomes large enough for reliable non-volatile memory reading, the WR will be reload with the value stored in a nonvolatile Initial Value Register (IVR). The WR and IVR can be read or written to directly using the SPI serial interface as described in the following sections. Memory Description The ISL22419 contains one non-volatile 7-bit register, known as the Initial Value Register (IVR), volatile 7-bit Wiper Register (WR), and volatile 8-bit Access Control Register (ACR). The memory map of ISL22419 is on Table 1. The non-volatile register (IVR) at address 0, contains initial wiper position and volatile register (WR) contains current wiper position. TABLE 1. MEMORY MAP ADDRESS NON-VOLATILE VOLATILE 2 — ACR Principles of Operation 1 The ISL22419 is an integrated circuit incorporating one DCP with its associated registers, non-volatile memory and the 0 9 Reserved IVR WR FN6311.0 June 28, 2006 ISL22419 The non-volatile IVR and volatile WR registers are accessible with the same address. There are only two valid instruction sets: 1011(binary) - is a Read operation The Access Control Register (ACR) contains information and control bits described below in Table 2. The VOL bit (ACR[7]) determines whether the access is to wiper registers WR or initial value registers IVR. TABLE 2. ACCESS CONTROL REGISTER (ACR) BIT # 7 6 5 4 3 2 1 0 BIT NAME VOL SHDN WIP 0 0 0 0 0 If VOL bit is 0, the non-volatile IVR register is accessible. If VOL bit is 1, only the volatile WR is accessible. Note, value is written to IVR register also is written to the WR. The default value of this bit is 0. The SHDN bit (ACR[6]) disables or enables Shutdown mode. This bit is logically OR’d with SHDN pin. When this bit is 0, DCP is in Shutdown mode. Default value of SHDN bit is 1. The WIP bit (ACR[5]) is read only bit. It indicates that nonvolatile write operation is in progress. The WIP bit can be read repeatedly after a non-volatile write to determine if the write has been completed. It is impossible to write to the WR or ACR while WIP bit is 1. SPI Serial Interface The ISL22419 supports an SPI serial protocol, mode 0. The device is accessed via the SDI input and SDO output with data clocked in on the rising edge of SCK, and clocked out on the falling edge of SCK. CS must be LOW during communication with the ISL22419. SCK and CS lines are controlled by the host or master. The ISL22419 operates only as a slave device. All communication over the SPI interface is conducted by sending the MSB of each byte of data first. 1100(binary) - is a Write operation There are only two registers address possible for this DCP. If the R1, R0 bits are zero, then the read or write is to either the IVR or the WR register (depends of VOL bit at ACR). If the R1 bit is 1and R0 bit is 0, then the operation is on the ACR. Write Operation A Write operation to the ISL22419 is a three-byte operation. It requires first, the CS transition from HIGH to LOW, then a valid Identification Byte, then a valid instruction byte followed by Data Byte is sent to SDI pin. The host terminates the write operation by pulling the CS pin from LOW to HIGH. For a write to address 0 (WR), the byte at address 2 (ACR[7]) determines if the Data Byte is to be written to volatile or both volatile and non-volatile registers. Refer to “Memory Description” and Figure 12. The internal non-volatile write cycle starts after rising edge of CS and takes up to 20ms. Read Operation A read operation to the ISL22419 is a three byte operation. It requires first, the CS transition from HIGH to LOW, then a valid Identification Byte, then a valid instruction byte followed by “dummy” Data Byte is sent to SDI pin. The SPI host reads the data from SDO pin on falling edge of SCK. The host terminates the read operation by pulling the CS pin from LOW to HIGH (see Figure 13). In order to read back the non-volatile IVR, it is recommended that the application reads the ACR first to verify the WIP bit is 0. If the WIP bit (ACR[5]) is not 0, the host should repeat its reading sequence again. Protocol Conventions The first byte sent to the ISL22419 from the SPI host is the Identification Byte. A valid Identification Byte contains 0101 as the four MSBs, with the following four bits set to 0. TABLE 3. IDENTIFICATION BYTE FORMAT 0 1 0 1 0 0 0 (MSB) 0 (LSB) The next byte sent to the ISL22419 contains the instruction and register pointer information. The four MSBs are the instruction and two LSBs are register address (see Table 4). TABLE 4. IDENTIFICATION BYTE FORMAT 7 6 5 4 3 2 1 0 I3 I2 I1 I0 0 0 R1 R0 10 FN6311.0 June 28, 2006 ISL22419 CS SCK SDI 0 1 0 1 0 0 0 0 0 I3 I2 I1 I0 0 0 R1 R0 0 D6 D5 D4 D3 D2 D1 D0 FIGURE 12. THREE BYTE WRITE SEQUENCE CS SCK SDI Don’t Care 0 1 0 1 0 0 0 0 0 I3 I2 I1 I0 0 0 R1 R0 SDO 0 D6 D5 D4 D3 D2 D1 D0 FIGURE 13. THREE BYTE READ SEQUENCE Applications Information Communicating with ISL22419 Communication with ISL22419 proceeds using SPI interface through the ACR (address 11b), IVR (address 00b) and WR (address 00b) registers. The typical application diagram is shown in Figure 14. For proper operation adding 0.1µF decoupling ceramic capacitor to VCC is recommended. The capacitor value may vary based on expected noise frequency of the design. The wiper of the potentiometer is controlled by the WR register. Writes and reads can be made directly to this register to control and monitor the wiper position without any non-volatile memory changes. This is done by setting MSB bit (ACR[7]) at address 11b to 1. The non-volatile IVR stores the power up value of the wiper. IVR is accessible when MSB bit (ACR[7]) at address 11b is set to 0. Writing a new value to the IVR register will set a new power up position for the wiper. Also, writing to this register will load the same value into the WR as the IVR. Reading from the IVR will not change the WR, if its contents are different. 11 FN6311.0 June 28, 2006 ISL22419 Examples: A. Writing to the IVR: This sequence will write a new value (77h) to the IVR(non-volatile): Set the ACR (Addr 02h) for NV write (40h) Send the ID byte, Instruction Byte, then the Data byte 0 1 0 1 0 0 0 0 1 1 0 0 0 0 1 0 0 1 0 0 (Sent to SDI) 0 0 0 0 Set the IVR (Addr 00h) to 77h Send the ID byte, Instruction Byte, then the Data byte 0 1 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 1 (Sent to SDI) 0 1 1 1 0 1 1 0 0 (Sent to SDI) 0 0 0 0 x x x B. Reading from the WR: This sequence will read the value from the WR (volatile): Write to ACR first to access the WR Send the ID byte, Instruction Byte, then the Data byte 0 1 0 1 0 0 0 0 1 1 0 0 0 0 1 Read the data from WR (Addr 00h) Send the ID byte, Instruction Byte, then Read the Data byte 0 1 0 1 0 0 0 0 1 0 1 1 0 0 0 0 x x x x x (Out on SDO) VCC VCC 0.1µF Rpu VCC SHDN 0.1µF SCK SDO SDI RW VOUT CS R2 ISL22419 R1 FIGURE 14. TYPICAL APPLICATION DIAGRAM FOR IMPLEMENTING ADJUSTABLE VOLTAGE REFERANCE 12 FN6311.0 June 28, 2006 ISL22419 Mini Small Outline Plastic Packages (MSOP) N M8.118 (JEDEC MO-187AA) 8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE E1 INCHES E -B- INDEX AREA 1 2 0.20 (0.008) A B C TOP VIEW 4X θ 0.25 (0.010) R1 R GAUGE PLANE A SEATING PLANE -C- A2 A1 b -He D 0.10 (0.004) 4X θ L1 SEATING PLANE C 0.20 (0.008) C a CL E1 C D MAX MIN MAX NOTES 0.037 0.043 0.94 1.10 - A1 0.002 0.006 0.05 0.15 - A2 0.030 0.037 0.75 0.95 - b 0.010 0.014 0.25 0.36 9 c 0.004 0.008 0.09 0.20 - D 0.116 0.120 2.95 3.05 3 E1 0.116 0.120 2.95 3.05 4 0.026 BSC 0.65 BSC - E 0.187 0.199 4.75 5.05 - L 0.016 0.028 0.40 0.70 6 0.037 REF N C 0.20 (0.008) MIN A L1 -A- SIDE VIEW SYMBOL e L MILLIMETERS 0.95 REF 8 R 0.003 R1 0 α - 8 - 0.07 0.003 - 5o 15o 0o 6o 7 - - 0.07 - - 5o 15o - 0o 6o -B- Rev. 2 01/03 END VIEW NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-187BA. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. Dimension “D” does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions and are measured at Datum Plane. - H - Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. Formed leads shall be planar with respect to one another within 0.10mm (0.004) at seating Plane. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Datums -A -H- . and - B - to be determined at Datum plane 11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 13 FN6311.0 June 28, 2006