MC14562B 128-Bit Static Shift Register The MC14562B is a 128–bit static shift register constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. Data is clocked in and out of the shift register on the positive edge of the clock input. Data outputs are available every 16 bits, from 16 through bit 128. This complementary MOS shift register is primarily used where low power dissipation and/or high noise immunity is desired. • • • • • http://onsemi.com MARKING DIAGRAMS Diode Protection on All Inputs Fully Static Operation Cascadable to Provide Longer Shift Register Lengths Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Low–power TTL Loads or One Low–power Schottky TTL Load Over the Rated Temperature Range 14 PDIP–14 P SUFFIX CASE 646 MC14562BCP AWLYYWW 1 A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.) Parameter Value Unit – 0.5 to +18.0 V – 0.5 to VDD + 0.5 V Input or Output Current (DC or Transient) per Pin ± 10 mA PD Power Dissipation, per Package (Note 2.) 500 mW TA Ambient Temperature Range – 55 to +125 °C Tstg Storage Temperature Range – 65 to +150 °C TL Lead Temperature (8–Second Soldering) 260 °C Symbol VDD Vin, Vout Iin, Iout DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) ORDERING INFORMATION Device MC14562BCP Package Shipping PDIP–14 25/Rail 1. Maximum Ratings are those values beyond which damage to the device may occur. 2. Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high–impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. v v Semiconductor Components Industries, LLC, 2000 March, 2000 – Rev. 3 1 Publication Order Number: MC14562B/D MC14562B PIN ASSIGNMENT Q64 1 14 VDD Q96 2 13 Q32 Q128 3 12 DATA NC 4 11 NC CLOCK 5 10 Q16 Q112 6 9 Q48 VSS 7 8 Q80 NC = NO CONNECTION BLOCK DIAGRAM 12 Q16 Q32 Q48 Q64 Q80 Q96 Q112 Q128 DATA 5 CLOCK 10 13 9 1 8 2 6 3 VDD = PIN 14 VSS = PIN 7 Pins 4 and 11 not used. LOGIC DIAGRAM CLOCK 5 DATA IN 12 D Q C 1 D Q C 2 D Q C 3 D Q C 16 D Q C 17 D Q C 32 D Q C 33 D Q C 48 D Q C 49 D Q C 64 10 Q16 D Q C D Q C D Q C D Q C D Q C D Q C D Q C D Q C 65 80 81 96 97 112 113 128 13 Q32 9 Q48 1 Q64 8 Q80 2 Q96 6 Q112 3 Q128 http://onsemi.com 2 MC14562B ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Characteristic Output Voltage Vin = VDD or 0 Symbol – 55_C 25_C 125_C VDD Vdc Min Max Min Typ (3.) Max Min Max Unit “0” Level VOL 5.0 10 15 — — — 0.05 0.05 0.05 — — — 0 0 0 0.05 0.05 0.05 — — — 0.05 0.05 0.05 Vdc “1” Level VOH 5.0 10 15 4.95 9.95 14.95 — — — 4.95 9.95 14.95 5.0 10 15 — — — 4.95 9.95 14.95 — — — Vdc Input Voltage “0” Level (VO = 4.5 or 05 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) VIL 5.0 10 15 — — — 1.5 3.0 4.0 — — — 2.25 4.50 6.75 1.5 3.0 4.0 — — — 1.5 3.0 4.0 “1” Level VIH 5.0 10 15 3.5 7.0 11 — — — 3.5 7.0 11 2.75 5.50 8.25 — — — 3.5 7.0 11 — — — 5.0 5.0 10 15 – 3.0 – 0.64 – 1.6 – 4.2 — — — — – 2.4 – 0.51 – 1.3 – 3.4 – 4.2 – 0.88 – 2.25 – 8.8 — — — — – 1.7 – 0.36 – 0.9 – 2.4 — — — — IOL 5.0 10 15 0.64 1.6 4.2 — — — 0.51 1.3 3.4 0.88 2.25 8.8 — — — 0.36 0.9 2.4 — — — mAdc Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc Input Capacitance (Vin = 0) Cin — — — — 5.0 7.5 — — pF Quiescent Current (Per Package) IDD 5.0 10 15 — — — 5.0 10 20 — — — 0.010 0.020 0.030 5.0 10 20 — — — 150 300 600 µAdc IT 5.0 10 15 Vin = 0 or VDD (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Vdc Vdc IOH Source Sink Total Supply Current (4.) (5.) (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) mAdc IT = (1.94 µA/kHz) f + IDD IT = (3.81 µA/kHz) f + IDD IT = (5.52 µA/kHz) f + IDD 3. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. 4. The formulas given are for the typical characteristics only at 25_C. 5. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL – 50) Vfk where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.004. http://onsemi.com 3 µAdc MC14562B ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHARACTERISTICS (6.) (CL = 50 pF, TA = 25_C) Characteristic Symbol Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns tTLH, tTHL Propagation Delay Time Clock to Q tPLH, tPHL = (1.7 ns/pF) CL + 515 ns tPLH, tPHL = (0.66 ns/pF) CL + 217 ns tPLH, tPHL = (0.5 ns/pF) CL + 145 ns tPLH, tPHL Clock Pulse Width (50% Duty Cycle) Clock Pulse Frequency Data to Clock Setup Time Data to Clock Hold Time Clock Input Rise and Fall Times VDD Min Typ (7.) Max 5.0 10 15 — — — 100 50 40 200 100 80 Unit ns ns 5.0 10 15 — — — 600 250 170 1200 500 340 tWH 5.0 10 15 600 220 150 300 110 75 — — — ns fcl 5.0 10 15 — — — 1.9 5.6 8.0 1.1 3.0 4.0 MHz tsu(1) 5.0 10 15 – 20 – 10 0 – 170 – 64 – 60 — — — ns tsu(0) 5.0 10 15 – 20 – 10 0 – 91 – 58 – 48 — — — ns th(1) 5.0 10 15 350 165 155 263 109 100 — — — ns th(0) 5.0 10 15 350 200 140 267 140 93 — — — ns tr, tf 5.0 10 15 — — — — — — 15 5 4 µs 6. The formulas given are for the typical characteristics only at 25_C. 7. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. http://onsemi.com 4 MC14562B VDD Q16 Q32 Q48 Q64 Q80 Q96 Q112 Q128 DATA CLOCK CL VSS 7 ID CL CL CL CL CL CL CL 500 µF fo CLOCK VDD DATA (f = 1/2 fo) VDD VSS VSS Figure 1. Power Dissipation Test Circuit and Waveforms http://onsemi.com 5 MC14562B TIMING DIAGRAM PIN NO.’S PULSE 16 PULSE 1 PULSE 32 PULSE 128 CLOCK 5 DATA IN 12 Q16 10 Q32 13 Q28 3 AC TEST WAVEFORMS PULSE 1 CLOCK 50% 50% PULSE 2 50% tWH tr tWL DATA IN PULSE 16 90% 10% PULSE 17 VSS tf VDD 50% 50% VSS tsu(0) th(0) 50% 10% Q16 tPHL PULSE 1 CLOCK VDD 50% 50% 50% PULSE 2 90% VSS tTHL PULSE 17 PULSE 16 VDD 50% 50% VSS tWH tWL DATA IN 50% tsu(1) VDD VDD 50% VSS th(1) Q16 50% tPLH 90% 10% VDD VSS tTHL NOTE: The remaining Data–Bit Outputs (Q32, Q48, Q64, Q80, Q96, Q112 and Q128) will occur at Clock Pulse 32, 48, 64, 80, 96, 112, 128 in the same relationship as Q16. http://onsemi.com 6 MC14562B PACKAGE DIMENSIONS P SUFFIX PLASTIC DIP PACKAGE CASE 646–06 ISSUE M 14 8 1 7 B A F L N C –T– SEATING PLANE J K H G D 14 PL 0.13 (0.005) M M http://onsemi.com 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M N INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 ––– 10_ 0.015 0.039 MILLIMETERS MIN MAX 18.16 18.80 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 ––– 10_ 0.38 1.01 MC14562B ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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