ONSEMI MJB41C

MJB41C (NPN), MJB42C
(PNP)
Preferred Devices
Complementary Silicon
Plastic Power Transistors
D2PAK for Surface Mount
http://onsemi.com
• Lead Formed for Surface Mount Applications in Plastic Sleeves
•
•
(No Suffix)
Lead Formed Version in 16 mm Tape & Reel (“T4” Suffix)
Electrically the Same as TIP41 and T1P42 Series
MAXIMUM RATINGS
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎ
Rating
Symbol
Value
Unit
VCEO
100
Vdc
Collector–Base Voltage
VCB
100
Vdc
Emitter–Base Voltage
VEB
5.0
Vdc
Collector Current – Continuous
– Peak
IC
6.0
10
Adc
Base Current
IB
2.0
Adc
Total Power Dissipation
@ TC = 25C
Derate above 25C
PD
65
0.52
Watts
W/C
Total Power Dissipation
@ TA = 25C
Derate above 25C
PD
Unclamped Inductive Load Energy
(Note 1.)
Collector–Emitter Voltage
Operating and Storage Junction
Temperature Range
2.0
0.016
Watts
W/C
E
62.5
mJ
TJ, Tstg
–65 to
+150
C
THERMAL CHARACTERISTICS
COMPLEMENTARY SILICON
POWER TRANSISTORS
6 AMPERES
100 VOLTS
65 WATTS
MARKING DIAGRAM
MJB4xC
YWW
D2PAK
CASE 418B
STYLE 1
MJB4xC = Specific Device Code
x
= 1 or 2
Y
= Year
WW
= Work Week
ORDERING INFORMATION
Device
Package
Shipping
50 Units/Rail
Symbol
Max
Unit
MJB41C
D2PAK
Thermal Resistance, Junction to Case
RθJC
1.92
C/W
MJB41CT4
D2PAK
800/Tape & Reel
Thermal Resistance, Junction to Ambient
RθJA
62.5
C/W
MJB42C
D2PAK
50 Units/Rail
Thermal Resistance, Junction to Ambient
(Note 2.)
RθJA
50
C/W
MJB42CT4
D2PAK
800/Tape & Reel
TL
260
C
Characteristic
Maximum Lead Temperature
for Soldering Purposes,
1/8″ from Case for 10 Seconds
Preferred devices are recommended choices for future use
and best overall value.
1. IC = 2.5 A, L = 20 mH, P.R.F. = 10 Hz, VCC = 10 V, RBE = 100 2. When surface mounted to an FR–4 board using the minimum recommended
pad size.
 Semiconductor Components Industries, LLC, 2001
March, 2001 – Rev. 0
1
Publication Order Number:
MJB41C/D
MJB41C (NPN), MJB42C (PNP)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎ
ELECTRICAL CHARACTERISTICS (TC = 25C unless otherwise noted)
Characteristic
Symbol
Min
Max
Unit
VCEO(sus)
100
–
Vdc
Collector Cutoff Current (VCE = 60 Vdc, IB = 0)
ICEO
–
0.7
mAdc
Collector Cutoff Current (VCE = 100 Vdc, VEB = 0)
ICES
–
100
µAdc
Emitter Cutoff Current (VBE = 5.0 Vdc, IC = 0)
IEBO
–
50
Adc
hFE
30
15
–
75
–
Collector–Emitter Saturation Voltage (IC = 6.0 Adc, IB = 600 mAdc)
VCE(sat)
–
1.5
Vdc
Base–Emitter On Voltage (IC = 6.0 Adc, VCE = 4.0 Vdc)
VBE(on)
–
2.0
Vdc
Current–Gain – Bandwidth Product
(IC = 500 mAdc, VCE = 10 Vdc, ftest = 1.0 MHz)
fT
3.0
–
MHz
Small–Signal Current Gain
(IC = 0.5 Adc, VCE = 10 Vdc, f = 1.0 kHz)
hfe
20
–
–
OFF CHARACTERISTICS
Collector–Emitter Sustaining Voltage (Note 3.) (IC = 30 mAdc, IB = 0)
ON CHARACTERISTICS (Note 3.)
DC Current Gain (IC = 0.3 Adc, VCE = 4.0 Vdc)
DC Current Gain (IC = 3.0 Adc, VCE = 4.0 Vdc)
DYNAMIC CHARACTERISTICS
PD, POWER DISSIPATION (WATTS)
3. Pulse Test: Pulse Width 300 µs, Duty Cycle 2.0%.
TA
4.0
TC
80
3.0
60
2.0
40
1.0
20
0
0
TC
TA
0
20
40
60
100
80
T, TEMPERATURE (°C)
120
140
160
Figure 1. Power Derating
VCC
+30 V
tr, tf ≤ 10 ns
DUTY CYCLE = 1.0%
t, TIME (s)
µ
-9.0 V
0.7
0.5
SCOPE
RB
0
TJ = 25°C
VCC = 30 V
IC/IB = 10
1.0
RC
25 µs
+11 V
2.0
D1
-4 V
RB and RC VARIED TO OBTAIN DESIRED CURRENT LEVELS
0.3
0.2
0.1
0.07
0.05
0.03
0.02
0.06
D1 MUST BE FAST RECOVERY TYPE, e.g.:
1N5825 USED ABOVE IB ≈ 100 mA
MSD6100 USED BELOW IB ≈ 100 mA
tr
td @ VBE(off) ≈ 5.0 V
0.1
0.4 0.6
0.2
2.0
1.0
IC, COLLECTOR CURRENT (AMP)
Figure 3. Turn–On Time
Figure 2. Switching Time Test Circuit
http://onsemi.com
2
4.0
6.0
r(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED)
MJB41C (NPN), MJB42C (PNP)
1.0
0.7
0.5
D = 0.5
0.3
0.2
0.2
0.1
0.1
0.07
0.05
0.02
0.03
0.02
0.01
0.01
0.01
SINGLE PULSE
0.02
0.05
1.0
P(pk)
ZθJC(t) = r(t) RθJC
RθJC = 1.92°C/W MAX
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) - TC = P(pk) ZθJC(t)
0.05
0.2
0.5
1.0
2.0
5.0
t, TIME (ms)
10
20
t1
t2
DUTY CYCLE, D = t1/t2
50
100
200
500
1.0 k
Figure 4. Thermal Response
10
IC, COLLECTOR CURRENT (AMP)
5.0
1.0ms
3.0
2.0
1.0
0.5
0.3
0.2
There are two limitations on the power handling ability of
a transistor: average junction temperature and second
breakdown. Safe operating area curves indicate IC – VCE
limits of the transistor that must be observed for reliable
operation; i.e., the transistor must not be subjected to greater
dissipation than the curves indicate.
The data of Figure 5 is based on TJ(pk) = 150C; TC is
variable depending on conditions. Second breakdown pulse
limits are valid for duty cycles to 10% provided TJ(pk)
150C. TJ(pk) may be calculated from the data in
Figure 4. At high case temperatures, thermal limitations will
reduce the power that can be handled to values less than the
limitations imposed by second breakdown.
0.5ms
SECONDARY BREAKDOWN LTD
BONDING WIRE LTD
THERMAL LIMITATION @ TC = 25°C
(SINGLE PULSE)
CURVES APPLY BELOW RATED VCEO
0.1
5.0
5.0ms
40
10
20
60
VCE, COLLECTOR-EMITTER VOLTAGE (VOLTS)
80 100
Figure 5. Active–Region Safe Operating Area
5.0
300
ts
1.0
TJ = 25°C
VCC = 30 V
IC/IB = 10
IB1 = IB2
0.7
0.5
0.3
0.2
0.1
0.07
0.05
0.06
TJ = 25°C
200
C, CAPACITANCE (pF)
t, TIME (s)
µ
3.0
2.0
tf
Cib
100
70
Cob
50
0.1
0.2
0.4 0.6
1.0
2.0
IC, COLLECTOR CURRENT (AMP)
4.0
30
0.5
6.0
Figure 6. Turn–Off Time
1.0
2.0 3.0
5.0
10
20
VR, REVERSE VOLTAGE (VOLTS)
Figure 7. Capacitance
http://onsemi.com
3
30
50
MJB41C (NPN), MJB42C (PNP)
300
200
VCE = 2.0 V
TJ = 150°C
100
70
50
25°C
30
20
10
7.0
5.0
0.06
VCE , COLLECTOR-EMITTER VOLTAGE (VOLTS)
hFE, DC CURRENT GAIN
500
-55°C
0.1
4.0
0.2 0.3 0.4 0.6
1.0
2.0
IC, COLLECTOR CURRENT (AMP)
6.0
2.0
TJ = 25°C
1.6
1.2
IC = 1.0 A
0.4
0
10
θV, TEMPERATURE COEFFICIENTS (mV/°C)
TJ = 25°C
V, VOLTAGE (VOLTS)
1.6
1.2
VBE(sat) @ IC/IB = 10
VBE @ VCE = 4.0 V
VCE(sat) @ IC/IB = 10
0.1
0.2 0.3 0.4
0.6
1.0
2.0 3.0 4.0
6.0
IC, COLLECTOR CURRENT (A)
µ
100°C
IC = ICES
10-1
REVERSE
-0.1
+1.0
+0.5
+25°C to +150°C
*θVC FOR VCE(sat)
0
-55°C to +25°C
-0.5
+25°C to +150°C
-1.0
-1.5
θVB FOR VBE
-55°C to +25°C
-2.0
-2.5
0.06
0.1
0.2 0.3
0.5
1.0
2.0 3.0 4.0
FORWARD
0
+0.1 +0.2 +0.3
+0.4 +0.5 +0.6
+0.7
6.0
10M
VCE = 30 V
IC = 10 x ICES
IC ≈ ICES
100k
25°C
10-3
-0.3 -0.2
*APPLIES FOR IC/IB ≤ hFE/4
+1.5
1.0M
TJ = 150°C
1000
+2.5
+2.0
Figure 11. Temperature Coefficients
100
10-2
500
Figure 10. “On” Voltages
VCE = 30 V
101
50
100
200 300
IB, BASE CURRENT (mA)
IC, COLLECTOR CURRENT (AMP)
103
102
30
IC, COLLECTOR CURRENT (AMP)
R BE , EXTERNAL BASE-EMITTER RESISTANCE (OHMS)
0
0.06
20
Figure 9. Collector Saturation Region
2.0
0.4
5.0 A
0.8
Figure 8. DC Current Gain
0.8
2.5 A
10k
IC = 2 x ICES
1.0k
0.1k
(TYPICAL ICES VALUES
OBTAINED FROM FIGURE 12)
20
40
60
80
100
120
140
160
VBE, BASE-EMITTER VOLTAGE (VOLTS)
TJ, JUNCTION TEMPERATURE (°C)
Figure 12. Collector Cut–Off Region
Figure 13. Effects of Base–Emitter Resistance
http://onsemi.com
4
MJB41C (NPN), MJB42C (PNP)
INFORMATION FOR USING THE D2PAK SURFACE MOUNT PACKAGE
RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the
total design. The footprint for the semiconductor packages
must be the correct size to ensure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self align when
subjected to a solder reflow process.
0.33
8.38
0.08
2.032
0.42
10.66
0.24
6.096
0.04
1.016
0.12
3.05
0.63
17.02
inches
mm
POWER DISSIPATION FOR A SURFACE MOUNT DEVICE
Although one can almost double the power dissipation with
this method, one will be giving up area on the printed
circuit board which can defeat the purpose of using surface
mount technology. For example, a graph of RθJA versus
Collector pad area is shown in Figure 14.
PD =
R
JA , Thermal Resistance, Junctionto Ambient (C/W)
The power dissipation for a surface mount device is a
function of the Collector pad size. These can vary from the
minimum pad size for soldering to a pad size given for
maximum power dissipation. Power dissipation for a
surface mount device is determined by TJ(max), the
maximum rated junction temperature of the die, RθJA, the
thermal resistance from the device junction to ambient, and
the operating temperature, TA. Using the values provided
on the data sheet, PD can be calculated as follows:
°
TJ(max) – TA
RθJA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values
into the equation for an ambient temperature TA of 25°C,
one can calculate the power dissipation of the device. For a
D2PAK device, PD is calculated as follows.
Board Material = 0.0625″
G-10/FR-4, 2 oz Copper
60
TA = 25°C
2.5 Watts
50
3.5 Watts
40
5 Watts
30
20
0
θ
PD = 150°C – 25°C = 2.5 Watts
50°C/W
70
2
4
6
8
10
A, Area (square inches)
12
14
16
Figure 14. Thermal Resistance versus Collector Pad
Area for the D2PAK Package (Typical)
The 50°C/W for the D2PAK package assumes the use of
the recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 2.5 Watts. There are
other alternatives to achieving higher power dissipation
from the surface mount packages. One is to increase the
area of the Collector pad. By increasing the area of the
collection pad, the power dissipation can be increased.
Another alternative would be to use a ceramic substrate
or an aluminum core board such as Thermal Clad. Using a
board material such as Thermal Clad, an aluminum core
board, the power dissipation can be doubled using the same
footprint.
http://onsemi.com
5
MJB41C (NPN), MJB42C (PNP)
SOLDER STENCIL GUIDELINES
typical stencil for the DPAK and D2PAK packages. The
pattern of the opening in the stencil for the Collector pad is
not critical as long as it allows approximately 50% of the
pad to be covered with paste.
Prior to placing surface mount components onto a printed
circuit board, solder paste must be applied to the pads.
Solder stencils are used to screen the optimum amount.
These stencils are typically 0.008 inches thick and may be
made of brass or stainless steel. For packages such as the
SC–59, SC–70/SOT–323, SOD–123, SOT–23, SOT–143,
SOT–223, SO–8, SO–14, SO–16, and SMB/SMC diode
packages, the stencil opening should be the same as the pad
size or a 1:1 registration. This is not the case with the DPAK
and D2PAK packages. If one uses a 1:1 opening to screen
solder onto the Collector pad, misalignment and/or
“tombstoning” may occur due to an excess of solder. For
these two packages, the opening in the stencil for the paste
should be approximately 50% of the tab area. The opening
for the leads is still a 1:1 registration. Figure 15. shows a
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇÇ
ÇÇÇ
ÇÇ
ÇÇÇ
ÇÇÇ ÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
SOLDER PASTE
OPENINGS
STENCIL
Figure 15. Typical Stencil for DPAK and
D2PAK Packages
SOLDERING PRECAUTIONS
• When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
• After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.
• Mechanical stress or shock should not be applied
during cooling.
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within
a short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
• Always preheat the device.
• The delta temperature between the preheat and
soldering should be 100°C or less.*
• When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering
method, the difference shall be a maximum of 10°C.
• The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
* Soldering a device without preheating can cause
excessive thermal shock and stress which can result in
damage to the device.
* Due to shadowing and the inability to set the wave height
to incorporate other surface mount components, the D2PAK
is not recommended for wave soldering.
http://onsemi.com
6
MJB41C (NPN), MJB42C (PNP)
TYPICAL SOLDER HEATING PROFILE
The line on the graph shows the actual temperature that
might be experienced on the surface of a test board at or
near a central solder joint. The two profiles are based on a
high density and a low density board. The Vitronics
SMD310 convection/infrared reflow soldering system was
used to generate this profile. The type of solder used was
62/36/2 Tin Lead Silver with a melting point between
177–189°C. When this type of furnace is used for solder
reflow work, the circuit boards and solder joints tend to
heat first. The components on the board are then heated by
conduction. The circuit board, because it has a large surface
area, absorbs the thermal energy more efficiently, then
distributes this energy to the components. Because of this
effect, the main body of a component may be up to 30
degrees cooler than the adjacent solder joints.
For any given circuit board, there will be a group of
control settings that will give the desired heat pattern. The
operator must set temperatures for several heating zones,
and a figure for belt speed. Taken together, these control
settings make up a heating “profile” for that particular
circuit board. On machines controlled by a computer, the
computer remembers these profiles from one operating
session to the next. Figure 16. shows a typical heating
profile for use when soldering a surface mount device to a
printed circuit board. This profile will vary among
soldering systems but it is a good starting point. Factors that
can affect the profile include the type of soldering system in
use, density and types of components on the board, type of
solder used, and the type of board or substrate material
being used. This profile shows temperature versus time.
STEP 1
PREHEAT
ZONE 1
RAMP"
200°C
150°C
STEP 2
STEP 3
VENT
HEATING
SOAK" ZONES 2 & 5
RAMP"
DESIRED CURVE FOR HIGH
MASS ASSEMBLIES
STEP 5
STEP 4
HEATING
HEATING
ZONES 3 & 6 ZONES 4 & 7
SPIKE"
SOAK"
170°C
160°C
140°C
100°C
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
(DEPENDING ON
MASS OF ASSEMBLY)
DESIRED CURVE FOR LOW
MASS ASSEMBLIES
TIME (3 TO 7 MINUTES TOTAL)
TMAX
Figure 16. Typical Solder Heating Profile
http://onsemi.com
7
STEP 7
COOLING
205° TO 219°C
PEAK AT
SOLDER JOINT
150°C
100°C
50°C
STEP 6
VENT
MJB41C (NPN), MJB42C (PNP)
PACKAGE DIMENSIONS
D2PAK
CASE 418B–03
ISSUE D
C
E
V
–B–
4
DIM
A
B
C
D
E
G
H
J
K
S
V
A
1
2
S
3
–T–
SEATING
PLANE
K
J
G
D
M
T B
INCHES
MIN
MAX
0.340
0.380
0.380
0.405
0.160
0.190
0.020
0.035
0.045
0.055
0.100 BSC
0.080
0.110
0.018
0.025
0.090
0.110
0.575
0.625
0.045
0.055
STYLE 1:
PIN 1.
2.
3.
4.
H
3 PL
0.13 (0.005)
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
M
MILLIMETERS
MIN
MAX
8.64
9.65
9.65
10.29
4.06
4.83
0.51
0.89
1.14
1.40
2.54 BSC
2.03
2.79
0.46
0.64
2.29
2.79
14.60
15.88
1.14
1.40
BASE
COLLECTOR
EMITTER
COLLECTOR
Thermal Clad is a registered trademark of the Bergquist Company
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable
attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
NORTH AMERICA Literature Fulfillment:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada
Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada
Email: [email protected]
Fax Response Line: 303–675–2167 or 800–344–3810 Toll Free USA/Canada
N. American Technical Support: 800–282–9855 Toll Free USA/Canada
EUROPE: LDC for ON Semiconductor – European Support
German Phone: (+1) 303–308–7140 (Mon–Fri 2:30pm to 7:00pm CET)
Email: ONlit–[email protected]
French Phone: (+1) 303–308–7141 (Mon–Fri 2:00pm to 7:00pm CET)
Email: ONlit–[email protected]
English Phone: (+1) 303–308–7142 (Mon–Fri 12:00pm to 5:00pm GMT)
Email: [email protected]
CENTRAL/SOUTH AMERICA:
Spanish Phone: 303–308–7143 (Mon–Fri 8:00am to 5:00pm MST)
Email: ONlit–[email protected]
Toll–Free from Mexico: Dial 01–800–288–2872 for Access –
then Dial 866–297–9322
ASIA/PACIFIC: LDC for ON Semiconductor – Asia Support
Phone: 303–675–2121 (Tue–Fri 9:00am to 1:00pm, Hong Kong Time)
Toll Free from Hong Kong & Singapore:
001–800–4422–3781
Email: ONlit–[email protected]
JAPAN: ON Semiconductor, Japan Customer Focus Center
4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031
Phone: 81–3–5740–2700
Email: [email protected]
ON Semiconductor Website: http://onsemi.com
EUROPEAN TOLL–FREE ACCESS*: 00–800–4422–3781
*Available from Germany, France, Italy, UK, Ireland
For additional information, please contact your local
Sales Representative.
http://onsemi.com
8
MJB41C/D