NBVSPA015 Series 3.3 V, LVDS Voltage-Controlled Clock Oscillator (VCXO) PureEdget Product Series The NBVSPXXXX voltage−controlled crystal oscillator (VCXO) devices are designed to meet today’s requirements for 3.3 V LVDS clock generation applications. These devices use a high Q fundamental mode crystal and Phase Locked Loop (PLL) multiplier to provide a wide range of frequencies from 60 MHz to 700 MHz (factory configurable per user specifications) with a pullable range of ±100 ppm and a frequency stability of ±50 ppm. The silicon−based PureEdge t products design provides users with exceptional frequency stability and reliability. They produce an ultra low jitter and phase noise LVDS differential output. The NBVSPXXXX series devices are a member of ON Semiconductor’s PureEdget clock family that provides accurate and precision clock generation solutions. Available in the industry standard 5.0 x 7.0 x 1.8 mm and in a new smaller 3.2 x 5.0 x 1.2 mm SMD (CLCC) package on 16 mm tape and reel in quantities of 1,000. Features • • • • • • • • • • • LVDS Differential Output Uses High Q Fundamental Mode Crystal Ultra Low Jitter and Phase Noise − 0.5 ps (12 kHz − 20 MHz) Factory Configurable Frequencies from 60 MHz to 700 MHz (see Standard Frequencies in the Ordering Information Table on page 6) Pullable Range Minimum of ±100 ppm Frequency Stability of ±50 ppm Control Voltage with Positive Slope Voltage Control Linearity of ±10% Hermetically Sealed Ceramic SMD Packages of size 5.0 x 7.0 x 1.8 mm and 3.2 x 5.0 x 1.2 mm Operating Range: 3.3 V ±10% These Devices are Pb−Free and are RoHS Compliant http://onsemi.com MARKING DIAGRAMS 6 PIN CLCC LN SUFFIX CASE 848AB 6 PIN CLCC LU SUFFIX CASE 848AC NBVSPXXXX XXX.XXXX A WL YY WW G NBVSPXXXX XXX.XXXX AWLYYWWG NBVSPXXXX XXX.XXXX AWLYYWWG = NBVSPXXXX (±50 ppm) = Output Frequency (MHz) = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. Applications • • • • • Networking SONET 10 Gigabit Ethernet Networking Base Stations Broadcasting © Semiconductor Components Industries, LLC, 2010 December, 2010 − Rev. 1 1 Publication Order Number: NBVSPA015/D NBVSPA015 Series VDD 6 CLK CLK 5 4 PLL Clock Multiplier Crystal 20−30 MHz LVDS 1 VC 2 OE 3 GND Figure 1. Simplified Logic Diagram VC 1 6 VDD OE 2 5 CLK GND 3 4 CLK Figure 2. Pin Connections (Top View) Table 1. PIN DESCRIPTION Pin No. Symbol I/O Description 1 VC (Note 1) Analog Input Analog control voltage input pin that adjusts output oscillation frequency. f0 =VC = 1.65 V 2 OE LVTTL/LVCMOS Control Input 3 GND Power Supply Ground at 0 V. Electrical and Case Ground. 4 CLK LVDS Output Non−Inverted Clock Output. Typically loaded with 100 W receiver termination resistor across differential pair. 5 CLK LVDS Output Inverted Clock Output. Typically loaded with 100 W receiver termination resistor across differential pair. 6 VDD Power Supply Positive Power Supply Voltage. Voltage should not exceed 3.3 V ±10%. Output Enable Pin. When left floating pin defaults to logic HIGH and output is active. See OE pin description Table 2. 1. Control voltage has a positive slope with a typical linearity of ±10%; VC = 1.65 V ± 1 V. Table 2. OUTPUT ENABLE TRI−STATE FUNCTION OE Pin Output Pins Open Active HIGH Level Active LOW Level High Z Table 3. ATTRIBUTES Characteristic Value Input Default State Resistor ESD Protection 170 kW Human Body Model Machine Model 2 kV 200 V Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test 2. For additional Moisture Sensitivity information, refer to Application Note AND8003/D. http://onsemi.com 2 NBVSPA015 Series Table 4. MAXIMUM RATINGS Symbol Parameter Condition 1 VDD Positive Power Supply VIN Control Input (VC and OE) IOSC Output Short Circuit Current CLK to CLK CLK or CLK to GND Condition 2 GND = 0 V Rating Units 4.6 V VIN ≤ VDD + 200 mV VIN ≥ GND − 200 mV Continuous Continuous V 12 24 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −55 to +120 °C Tsol Wave Solder 260 °C See Figure 4 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 5. DC CHARACTERISTICS (VDD = 3.3 V ±10%, GND = 0 V, TA = −40°C to +85°C) (Note 3) Symbol Characteristic Conditions Min. Typ. Max. Units 75 100 mA VDD mV IDD Power Supply Current VIH OE and FSEL Input HIGH Voltage 2000 VIL OE and FSEL Input LOW Voltage GND − 300 800 mV IIH Input HIGH Current OE −100 +100 mA IIL Input LOW Current OE −100 +100 mA 25 mV 1375 mV 1 25 mV 1425 1600 mV DVOD VOS DVOS Change in Magnitude of VOD for Complementary Output States (Note 4) Offset Voltage Change in Magnitude of VOS for Complementary Output States 0 1 1125 (Note 4) 0 VOH Output HIGH Voltage VOL Output LOW Voltage 900 VOD Differential Output Voltage 250 1075 mV 450 mV NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 Ifpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. Measurement taken with outputs terminated with 100 ohm across differential pair. See Figure 3. 4. Parameter guaranteed by design verification not tested in production. http://onsemi.com 3 NBVSPA015 Series Table 6. AC CHARACTERISTICS (VDD = 3.3 ±10%, GND = 0 V, TA = −40°C to +85°C) (Note 5) Symbol Characteristic Conditions fCLKOUT Output Clock Frequency NBVSPA019 125.00 NBVSPA027 148.50 NBVSPA018 155.52 NBVSPA017 156.25 NBVSPA024 160.00 NBVSPA015 200.00 NBVSPA042 74.25 Df Frequency Stability – NBVSPAXXX (Note 6) tjit(f) RMS Phase Jitter 12 kHz to 20 MHz tjitter Min. Typ. 0.4 Max. Units MHz ±50 ppm 0.9 ps Cycle to Cycle, RMS 1000 Cycles 3 8 ps Cycle to Cycle, Peak−to−Peak 1000 Cycles 15 30 ps Period, RMS 10,000 Cycles 2 4 ps Period, Peak−to−Peak 10,000 Cycles 10 20 ps 200 ns tOE/OD Output Enable/Disable Time FP Crystal Pullability (Note 7) 0 V ≤ VC ≤ 3.3 V ±100 ppm VC(bw) Control Voltage Bandwidth −3 dB 20 KHz tDUTY_CYCLE Output Clock Duty Cycle (Measured at Cross Point) tR 45 50 55 % Output Rise Time (20% and 80%) 245 400 ps tF Output Fall Time (80% and 20%) 245 400 ps tstart Start−up Time 1 5 ms 3 ppm 1st Aging Year Every Year After 1st 1 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 Ifpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Measurement taken with outputs terminated with 100 ohm across differential pair. See Figure 3. 6. Parameter guarantees 10 years of aging. Includes initial stability at 25°C, shock, vibration and first year aging. 7. Gain transfer is positive with a rate of 130 ppm/V. Table 7. PHASE NOISE PERFORMANCE FOR NBVSPXXXX Parameter fNOISE Characteristic Output Phase−N oise Performa nce Condition 74.25 MHZ 125.00 MHZ 148.50 MHz 155.52 MHz 156.25 MHZ 160.00 MHz 200.00 MHZ Units 100 Hz of Carrier −94 −90 −90 −90 −90 −90 −91 dBc/Hz 1 kHz of Carrier −122 −117 −116 −116 −116 −116 −117 dBc/Hz 10 kHz of Carrier −132 −128 −126 −126 −126 −126 −127 dBc/Hz 100 kHz of Carrier −132 −128 −126 −126 −126 −126 −127 dBc/Hz 1 MHz of Carrier −142 −136 −136 −134 −134 −135 −135 dBc/Hz 10 MHz of Carrier −160 −159 −159 −159 −159 −159 −159 dBc/Hz http://onsemi.com 4 NBVSPA015 Series Table 8. RELIABILITY COMPLIANCE ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Parameter Standard Method Shock Mechanical MIL−STD−833, Method 2002, Condition B Solderability Mechanical MIL−STD−833, Method 2003 Vibration Mechanical MIL−STD−833, Method 2007, Condition A Solvent Resistance Mechanical MIL−STD−202, Method 215 Thermal Shock Environment MIL−STD−833, Method 1011, Condition A Moisture Level Sensitivity Environment MSL1 260°C per IPC/JEDEC J−STD−020D NBVSPAXXX Zo = 50 W CLK D Driver Device Receiver Device 100 W CLK D Zo = 50 W Figure 3. Typical Termination for Output Driver and Device Evaluation temp. 260°C 20 − 40 sec. max. peak Temperature (°C) 260 6°C/sec. max. 3°C/sec. max. 217 ramp−up 175 150 cooling pre−heat reflow 60180 sec. Time 60150 sec. Figure 4. Recommended Reflow Soldering Profile http://onsemi.com 5 NBVSPA015 Series Table 9. ORDERING INFORMATION Device Output Frequency (MHz) Package Shipping† 5.0 x 7.0 x 1.8 mm NBVSPA017LN1TAG 156.2500 CLCC−6, Pb−Free 1000 / Tape & Reel NBVSPA018LN1TAG 155.5200 CLCC−6, Pb−Free 1000 / Tape & Reel NBVSPA024LN1TAG 160.0000 CLCC−6, Pb−Free 1000 / Tape & Reel NBVSPA015LN1TAG 200.0000 CLCC−6, Pb−Free 1000 / Tape & Reel NBVSPA027LN1TAG 148.5000 CLCC−6, Pb−Free 1000 / Tape & Reel NBVSPA019LN1TAG 125.0000 CLCC−6, Pb−Free 1000 / Tape & Reel NBVSPA042LN1TAG 74.2500 CLCC−6, Pb−Free 1000 / Tape & Reel 3.2 x 5.0 x 1.2 mm NBVSPA017LU1TAG* 156.2500 CLCC−6, Pb−Free 1000 / Tape & Reel NBVSPA018LU1TAG* 155.5200 CLCC−6, Pb−Free 1000 / Tape & Reel NBVSPA024LU1TAG* 160.0000 CLCC−6, Pb−Free 1000 / Tape & Reel NBVSPA015LU1TAG* 200.0000 CLCC−6, Pb−Free 1000 / Tape & Reel NBVSPA027LU1TAG* 148.5000 CLCC−6, Pb−Free 1000 / Tape & Reel NBVSPA019LU1TAG* 125.0000 CLCC−6, Pb−Free 1000 / Tape & Reel NBVSPA042LU1TAG* 74.2500 CLCC−6, Pb−Free 1000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and Reel Packaging Specification Brochure, BRD8011/D *Consult factory for availability. http://onsemi.com 6 NBVSPA015 Series PACKAGE DIMENSIONS 6 PIN CLCC, 5x3.2, 1.27P CASE 848AC−01 ISSUE O A D D1 PIN ONE REFERENCE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. B DIM A A1 A3 b D D1 E E1 E2 e L E1 E 2X 0.15 C 2X 0.15 C TOP VIEW 0.10 C A A1 METALLIZED ZONES A3 C SEATING PLANE SIDE VIEW 1 E2 6X L 6X b e 0.10 C A B BOTTOM VIEW 0.05 C SOLDERING FOOTPRINT* 6X 6X 0.74 1.13 3.30 PACKAGE OUTLINE 1 1.27 PITCH DIMENSION: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 7 MILLIMETERS MIN MAX 1.05 1.35 0.35 0.65 0.90 REF 0.50 0.80 5.00 BSC 4.25 4.55 3.20 BSC 2.45 2.75 2.90 3.20 1.27 BSC 0.75 1.05 NBVSPA015 Series PACKAGE DIMENSIONS 6 PIN CLCC, 7x5, 2.54P CASE 848AB−01 ISSUE O A D 4X 0.15 C E2 TERMINAL 1 INDICATOR NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. B D1 DIM A A1 A2 A3 b D D1 D2 D3 E E1 E2 E3 e L R E E1 D2 TOP VIEW A2 A3 0.10 C A SIDE VIEW A1 C 6.17 6.66 4.37 4.65 1.17 SOLDERING FOOTPRINT* 3 2 e 6X R 1.50 E3 0.10 C A B 0.05 C 0.08 1.30 MILLIMETERS NOM MAX 1.80 1.90 0.70 REF 0.36 REF 0.10 0.12 1.40 1.50 7.00 BSC 6.20 6.23 6.81 6.96 5.08 BSC 5.00 BSC 4.40 4.43 4.80 4.95 3.49 BSC 2.54 BSC 1.27 1.37 0.70 REF SEATING PLANE D3 1 MIN 1.70 6X b 6 5 4 6X L BOTTOM VIEW 2.54 PITCH 5.06 6X 1.50 DIMENSION: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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