Order this document by UC3842B/D The UC3842B, UC3843B series are high performance fixed frequency current mode controllers. They are specifically designed for Off–Line and dc–to–dc converter applications offering the designer a cost–effective solution with minimal external components. These integrated circuits feature a trimmed oscillator for precise duty cycle control, a temperature compensated reference, high gain error amplifier, current sensing comparator, and a high current totem pole output ideally suited for driving a power MOSFET. Also included are protective features consisting of input and reference undervoltage lockouts each with hysteresis, cycle–by–cycle current limiting, programmable output deadtime, and a latch for single pulse metering. These devices are available in an 8–pin dual–in–line and surface mount (SO–8) plastic package as well as the 14–pin plastic surface mount (SO–14). The SO–14 package has separate power and ground pins for the totem pole output stage. The UCX842B has UVLO thresholds of 16 V (on) and 10 V (off), ideally suited for off–line converters. The UCX843B is tailored for lower voltage applications having UVLO thresholds of 8.5 V (on) and 7.6 V (off). • Trimmed Oscillator for Precise Frequency Control • • • • • • • • HIGH PERFORMANCE CURRENT MODE CONTROLLERS N SUFFIX PLASTIC PACKAGE CASE 626 8 1 D1 SUFFIX PLASTIC PACKAGE CASE 751 (SO–8) 8 1 D SUFFIX PLASTIC PACKAGE CASE 751A (SO–14) 14 1 Oscillator Frequency Guaranteed at 250 kHz Current Mode Operation to 500 kHz PIN CONNECTIONS Automatic Feed Forward Compensation Latching PWM for Cycle–By–Cycle Current Limiting Compensation Voltage Feedback Current Sense RT/CT Internally Trimmed Reference with Undervoltage Lockout High Current Totem Pole Output Undervoltage Lockout with Hysteresis 1 8 2 7 3 6 4 5 Vref VCC Output Gnd (Top View) Low Startup and Operating Current Compensation NC Voltage Feedback NC Current Sense NC RT/CT Simplified Block Diagram VCC 7(12) 1 14 2 13 3 12 4 11 5 10 6 9 7 8 Vref NC VCC VC Output Gnd Power Ground (Top View) Vref 5.0V Reference 8(14) R Vref Undervoltage Lockout R RT/CT 2(3) Output Compensation 1(1) ORDERING INFORMATION VC 7(11) Output Oscillator 4(7) Voltage Feedback Input VCC Undervoltage Lockout Latching PWM + – Error Amplifier 6(10) Power Ground 5(8) Current Sense 3(5) Input Gnd 5(9) Pin numbers in parenthesis are for the D suffix SO–14 package. Operating Device Temperature Range UC384XBD UC384XBD1 TA = 0° to +70°C UC384XBN UC284XBD TA = – 25° to +85°C UC284XBD1 UC284XBN UC384XBVD UC384XBVD1 TA = – 40° to +105°C UC384XBVN X indicates either a 2 or 3 to define specific device part numbers. Motorola, Inc. 1996 MOTOROLA ANALOG IC DEVICE DATA Package SO–14 SO–8 Plastic SO–14 SO–8 Plastic SO–14 SO–8 Plastic Rev 1 1 UC3842B, 43B UC2842B, 43B MAXIMUM RATINGS Rating Symbol Value Unit (ICC + IZ) IO 30 mA 1.0 A Output Energy (Capacitive Load per Cycle) W 5.0 µJ Current Sense and Voltage Feedback Inputs Vin IO – 0.3 to + 5.5 V 10 mA PD RθJA 862 145 mW °C/W PD RθJA 702 178 mW °C/W PD RθJA TJ 1.25 100 W °C/W +150 °C Total Power Supply and Zener Current Output Current, Source or Sink (Note 1) Error Amp Output Sink Current Power Dissipation and Thermal Characteristics D Suffix, Plastic Package, SO–14 Case 751A Maximum Power Dissipation @ TA = 25°C Thermal Resistance, Junction–to–Air D1 Suffix, Plastic Package, SO–8 Case 751 Maximum Power Dissipation @ TA = 25°C Thermal Resistance, Junction–to–Air N Suffix, Plastic Package, Case 626 Maximum Power Dissipation @ TA = 25°C Thermal Resistance, Junction–to–Air Operating Junction Temperature Operating Ambient Temperature UC3842B, UC3843B UC2842B, UC2843B UC3842BV, UC3843BV Storage Temperature Range °C TA 0 to + 70 – 25 to + 85 –40 to +105 Tstg °C – 65 to +150 ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 2], RT = 10 k, CT = 3.3 nF. For typical values TA = 25°C, for min/max values TA is the operating ambient temperature range that applies [Note 3], unless otherwise noted.) UC284XB Characteristics UC384XB, XBV Symbol Min Typ Max Min Typ Max Unit Vref Regline Regload 4.95 5.0 5.05 4.9 5.0 5.1 V – 2.0 20 – 2.0 20 mV – 3.0 25 – 3.0 25 mV mV/°C REFERENCE SECTION Reference Output Voltage (IO = 1.0 mA, TJ = 25°C) Line Regulation (VCC = 12 V to 25 V) Load Regulation (IO = 1.0 mA to 20 mA) Temperature Stability Total Output Variation over Line, Load, and Temperature Output Noise Voltage (f = 10 Hz to 10 kHz, TJ = 25°C) Long Term Stability (TA = 125°C for 1000 Hours) Output Short Circuit Current TS Vref Vn – 0.2 – – 0.2 – 4.9 – 5.1 4.82 – 5.18 V – 50 – – 50 – µV S – 5.0 – – 5.0 – mV ISC – 30 – 85 –180 – 30 – 85 –180 mA 49 48 225 52 – 250 55 56 275 49 48 225 52 – 250 55 56 275 ∆fOSC/∆V ∆fOSC/∆T – 0.2 1.0 – 0.2 1.0 % – 1.0 – – 0.5 – % VOSC Idischg – 1.6 – – 1.6 – V 7.8 7.5 – 8.3 – – 8.8 8.8 – 7.8 7.6 7.2 8.3 – – 8.8 8.8 8.8 OSCILLATOR SECTION Frequency TJ = 25°C TA = Tlow to Thigh TJ = 25°C (RT = 6.2 k, CT = 1.0 nF) Frequency Change with Voltage (VCC = 12 V to 25 V) Frequency Change with Temperature TA = Tlow to Thigh Oscillator Voltage Swing (Peak–to–Peak) Discharge Current (VOSC = 2.0 V) TJ = 25°C TA = Tlow to Thigh (UC284XB, UC384XB) TA = Tlow to Thigh (UC384XBV) fOSC kHz mA NOTES: 1. Maximum Package power dissipation limits must be observed. 2. Adjust VCC above the Startup threshold before setting to 15 V. 3. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. Tlow = 0°C for UC3842B, UC3843B Thigh = +70°C for UC3842B, UC3843B Tlow = –25°C for UC2842B, UC2843B Thigh = +85°C for UC2842B, UC2843B Tlow = –40°C for UC3842BV, UC3843BV Thigh = +105°C for UC3842BV, UC3843BV 2 MOTOROLA ANALOG IC DEVICE DATA UC3842B, 43B UC2842B, 43B ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 2], RT = 10 k, CT = 3.3 nF. For typical values TA = 25°C, for min/max values TA is the operating ambient temperature range that applies [Note 3], unless otherwise noted.) UC284XB Characteristics UC384XB, XBV Symbol Min Typ Max Min Typ Max Unit VFB 2.45 2.5 2.55 2.42 2.5 2.58 V IIB – – 0.1 –1.0 – – 0.1 – 2.0 µA AVOL 65 90 – 65 90 – dB BW 0.7 1.0 – 0.7 1.0 – MHz PSRR 60 70 – 60 70 – dB ISink ISource 2.0 – 0.5 12 –1.0 – – 2.0 – 0.5 12 –1.0 – – VOH VOL 5.0 6.2 – 5.0 6.2 – – – 0.8 – 1.1 – – – 0.8 0.8 1.1 1.2 2.85 – 3.0 – 3.15 – 2.85 2.85 3.0 3.0 3.15 3.25 0.9 – 1.0 – 1.1 – 0.9 0.85 1.0 1.0 1.1 1.1 PSRR – 70 – – 70 – dB IIB – – 2.0 –10 – – 2.0 –10 µA – 150 300 – 150 300 ns – – – 13 – 12 0.1 1.6 – 13.5 – 13.4 0.4 2.2 – – – – – – – 13 12.9 12 0.1 1.6 1.6 13.5 13.5 13.4 0.4 2.2 2.3 – – – VOL(UVLO) – 0.1 1.1 – 0.1 1.1 V Output Voltage Rise Time (CL = 1.0 nF, TJ = 25°C) tr – 50 150 – 50 150 ns Output Voltage Fall Time (CL = 1.0 nF, TJ = 25°C) tf – 50 150 – 50 150 ns 15 7.8 16 8.4 17 9.0 14.5 7.8 16 8.4 17.5 9.0 9.0 7.0 10 7.6 11 8.2 8.5 7.0 10 7.6 11.5 8.2 ERROR AMPLIFIER SECTION Voltage Feedback Input (VO = 2.5 V) Input Bias Current (VFB = 5.0 V) Open Loop Voltage Gain (VO = 2.0 V to 4.0 V) Unity Gain Bandwidth (TJ = 25°C) Power Supply Rejection Ratio (VCC = 12 V to 25 V) Output Current Sink (VO = 1.1 V, VFB = 2.7 V) Source (VO = 5.0 V, VFB = 2.3 V) Output Voltage Swing High State (RL = 15 k to ground, VFB = 2.3 V) Low State (RL = 15 k to Vref, VFB = 2.7 V) (UC284XB, UC384XB) (UC384XBV) mA V CURRENT SENSE SECTION Current Sense Input Voltage Gain (Notes 4 & 5) (UC284XB, UC384XB) (UC384XBV) AV Maximum Current Sense Input Threshold (Note 4) (UC284XB, UC384XB) (UC384XBV) Vth Power Supply Rejection Ratio VCC = 12 V to 25 V, Note 4 Input Bias Current Propagation Delay (Current Sense Input to Output) tPLH(In/Out) V/V V OUTPUT SECTION Output Voltage Low State (ISink = 20 mA) (ISink = 200 mA) VOL High State VOH (UC284XB, UC384XB) (UC384XBV) (ISource = 20 mA) (UC284XB, UC384XB) (UC384XBV) (ISource = 200 mA) Output Voltage with UVLO Activated VCC = 6.0 V, ISink = 1.0 mA V UNDERVOLTAGE LOCKOUT SECTION Startup Threshold (VCC) UCX842B, BV UCX843B, BV Minimum Operating Voltage After Turn–On (VCC) UCX842B, BV UCX843B, BV Vth V VCC(min) V NOTES: 2. Adjust VCC above the Startup threshold before setting to 15 V. 3. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. Tlow = 0°C for UC3842B, UC3843B Thigh = +70°C for UC3842B, UC3843B Tlow = –25°C for UC2842B, UC2843B Thigh = +85°C for UC2842B, UC2843B Tlow = –40°C for UC3842BV, UC3843BV Thigh = +105°C for UC3842BV, UC3843BV 4. This parameter is measured at the latch trip point with VFB = 0 V. ∆V Output Compensation 5. Comparator gain is defined as: AV ∆V Current Sense Input MOTOROLA ANALOG IC DEVICE DATA 3 UC3842B, 43B UC2842B, 43B ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 2], RT = 10 k, CT = 3.3 nF, for typical values TA = 25°C, for min/max values TA is the operating ambient temperature range that applies [Note 3], unless otherwise noted.) UC284XB Characteristics UC384XB, BV Symbol Min Typ Max Min Typ Max DC(max) 94 – – 96 – – – – 0 94 93 – 96 96 – – – 0 – 0.3 0.5 – 0.3 0.5 – 12 17 – 12 17 30 36 – 30 36 – Unit PWM SECTION Duty Cycle Maximum (UC284XB, UC384XB) Maximum (UC384XBV) Minimum % DC(min) TOTAL DEVICE Power Supply Current Startup (VCC = 6.5 V for UCX843B, Startup (VCC 14 V for UCX842B, BV) Operating (Note 2) ICC + IC Power Supply Zener Voltage (ICC = 25 mA) mA VZ V NOTES: 2. Adjust VCC above the Startup threshold before setting to 15 V. 3. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. Tlow = 0°C for UC3842B, UC3843B Thigh = +70°C for UC3842B, UC3843B Tlow = –25°C for UC2842B, UC2843B Thigh = +85°C for UC2842B, UC2843B Tlow = –40°C for UC3842BV, UC3843BV Thigh = +105°C for UC3842BV, UC3843BV Figure 1. Timing Resistor versus Oscillator Frequency Figure 2. Output Deadtime versus Oscillator Frequency 80 100 % DT, PERCENT OUTPUT DEADTIME R T, TIMING RESISTOR (k Ω) 50 20 8.0 5.0 2.0 0.8 10 k VCC = 15 V TA = 25°C 20 k 50 k 100 k 200 k 500 k fOSC, OSCILLATOR FREQUENCY (kHz) 1. CT = 10 nF 50 2. CT = 5.0 nF 3. CT = 2.0 nF 4. CT = 1.0 nF 20 5. CT = 500 pF 6. CT = 200 pF 10 7. CT = 100 pF D max , MAXIMUM OUTPUT DUTY CYCLE (%) I dischg , DISCHARGE CURRENT (mA) VCC = 15 V VOSC = 2.0 V 8.5 8.0 7.5 4 0 25 50 75 TA, AMBIENT TEMPERATURE (°C) 100 5 6 7 VCC = 15 V TA = 25°C 20 k 50 k 100 k 200 k 500 k fOSC, OSCILLATOR FREQUENCY (kHz) 1.0 M Figure 4. Maximum Output Duty Cycle versus Timing Resistor 9.0 – 25 1 2.0 Figure 3. Oscillator Discharge Current versus Temperature 7.0 – 55 3 2 5.0 1.0 10 k 1.0 M 4 125 100 90 80 Idischg = 7.5 mA 70 60 Idischg = 8.8 mA 50 40 0.8 1.0 2.0 3.0 4.0 RT, TIMING RESISTOR (kΩ) VCC = 15 V CT = 3.3 nF TA = 25°C 5.0 6.0 7.0 8.0 MOTOROLA ANALOG IC DEVICE DATA UC3842B, 43B UC2842B, 43B Figure 5. Error Amp Small Signal Transient Response VCC = 15 V AV = –1.0 TA = 25°C VCC = 15 V AV = –1.0 TA = 25°C 20 mV/DIV 3.0 V 2.50 V / 2.55 V Figure 6. Error Amp Large Signal Transient Response 2.5 V 2.45 V 2.0 V 0.5 µs/DIV 1.0 µs/DIV VCC = 15 V VO = 2.0 V to 4.0 V RL = 100 K TA = 25°C 80 Gain 60 0 30 60 40 90 Phase 20 120 0 150 100 1.0 k 10 k 100 k 1.0 M 180 10 M VCC = 15 V 1.0 0.8 TA = 25°C 0.6 TA = 125°C 0.4 TA = –55°C 0.2 0 Figure 9. Reference Voltage Change versus Source Current Figure 10. Reference Short Circuit Current versus Temperature ÄÄÄÄ ÄÄÄÄ ÄÄÄ ÄÄÄÄ ÄÄÄ ÄÄÄÄ ÄÄÄÄ – 4.0 – 8.0 TA = –55°C –12 TA = 125°C –16 – 20 TA = 25°C 20 40 60 80 100 Iref, REFERENCE SOURCE CURRENT (mA) MOTOROLA ANALOG IC DEVICE DATA 120 I SC , REFERENCE SHORT CIRCUIT CURRENT (mA) 2.0 4.0 6.0 VO, ERROR AMP OUTPUT VOLTAGE (V) VCC = 15 V 0 1.2 f, FREQUENCY (Hz) 0 – 24 Vth, CURRENT SENSE INPUT THRESHOLD (V) 100 – 20 10 ∆ Vref , REFERENCE VOLTAGE CHANGE (mV) Figure 8. Current Sense Input Threshold versus Error Amp Output Voltage φ, EXCESS PHASE (DEGREES) A VOL , OPEN LOOP VOLTAGE GAIN (dB) Figure 7. Error Amp Open Loop Gain and Phase versus Frequency 0 8.0 ÄÄÄÄ ÄÄÄÄ 110 VCC = 15 V RL ≤ 0.1 Ω 90 70 50 – 55 – 25 0 25 50 75 100 125 TA, AMBIENT TEMPERATURE (°C) 5 UC3842B, 43B UC2842B, 43B Figure 12. Reference Line Regulation ∆ V O , OUTPUT VOLTAGE CHANGE (2.0 mV/DIV) ∆ V O , OUTPUT VOLTAGE CHANGE (2.0 mV/DIV) Figure 11. Reference Load Regulation VCC = 15 V IO = 1.0 mA to 20 mA TA = 25°C 2.0 ms/DIV VCC = 12 V to 25 TA = 25°C 2.0 ms/DIV 0 – 2.0 Source Saturation (Load to Ground) Figure 14. Output Waveform VCC = 15 V 80 µs Pulsed Load 120 Hz Rate VCC = 15 V CL = 1.0 nF TA = 25°C 90% TA = – 55°C 3.0 TA = – 55°C 2.0 TA = 25°C 1.0 0 ÄÄÄ ÄÄÄÄÄ ÄÄÄÄÄ ÄÄÄÄ ÄÄÄ ÄÄÄÄÄ ÄÄÄÄÄ ÄÄÄÄ ÄÄÄÄÄ ÄÄÄÄ ÄÄÄ ÄÄÄ ÄÄÄ ÄÄÄÄ ÄÄ ÄÄÄÄ ÄÄ VCC TA = 25°C –1.0 0 200 Sink Saturation (Load to VCC) Gnd 400 600 10% 800 50 ns/DIV Figure 16. Supply Current versus Supply Voltage Figure 15. Output Cross Conduction 20 15 10 5 0 0 10 ÄÄÄÄ ÄÄÄÄ ÄÄÄÄ ÄÄÄÄ RT = 10 k CT = 3.3 nF VFB = 0 V ISense = 0 V TA = 25°C UCX842B UCX843B 20 V/DIV 100 ns/DIV I CC , SUPPLY CURRENT (mA) 25 VCC = 30 V CL = 15 pF TA = 25°C 100 mA/DIV V O , OUTPUT VOLTAGE IO, OUTPUT LOAD CURRENT (mA) I CC , SUPPLY CURRENT Vsat, OUTPUT SATURATION VOLTAGE (V) Figure 13. Output Saturation Voltage versus Load Current 20 30 40 VCC, SUPPLY VOLTAGE (V) 6 MOTOROLA ANALOG IC DEVICE DATA UC3842B, 43B UC2842B, 43B PIN FUNCTION DESCRIPTION Pin 8–Pin 14–Pin F Function i 1 1 Compensation This pin is the Error Amplifier output and is made available for loop compensation. 2 3 Voltage Feedback This is the inverting input of the Error Amplifier. It is normally connected to the switching power supply output through a resistor divider. 3 5 Current Sense A voltage proportional to inductor current is connected to this input. The PWM uses this information to terminate the output switch conduction. 4 7 RT/CT The Oscillator frequency and maximum Output duty cycle are programmed by connecting resistor RT to Vref and capacitor CT to ground. Operation to 500 kHz is possible. 5 D Description i i Gnd This pin is the combined control circuitry and power ground. 6 10 Output This output directly drives the gate of a power MOSFET. Peak currents up to 1.0 A are sourced and sunk by this pin. 7 12 VCC This pin is the positive supply of the control IC. 8 14 Vref This is the reference output. It provides charging current for capacitor CT through resistor RT. 8 Power Ground This pin is a separate power ground return that is connected back to the power source. It is used to reduce the effects of switching transient noise on the control circuitry. 11 VC The Output high state (VOH) is set by the voltage applied to this pin. With a separate power source connection, it can reduce the effects of switching transient noise on the control circuitry. 9 Gnd This pin is the control circuitry ground return and is connected back to the power source ground. 2,4,6,13 NC No connection. These pins are not internally connected. MOTOROLA ANALOG IC DEVICE DATA 7 UC3842B, 43B UC2842B, 43B OPERATING DESCRIPTION The UC3842B, UC3843B series are high performance, fixed frequency, current mode controllers. They are specifically designed for Off–Line and dc–to–dc converter applications offering the designer a cost–effective solution with minimal external components. A representative block diagram is shown in Figure 17. Oscillator The oscillator frequency is programmed by the values selected for the timing components RT and CT. Capacitor CT is charged from the 5.0 V reference through resistor RT to approximately 2.8 V and discharged to 1.2 V by an internal current sink. During the discharge of CT, the oscillator generates an internal blanking pulse that holds the center input of the NOR gate high. This causes the Output to be in a low state, thus producing a controlled amount of output deadtime. Figure 1 shows RT versus Oscillator Frequency and Figure 2, Output Deadtime versus Frequency, both for given values of CT. Note that many values of RT and CT will give the same oscillator frequency but only one combination will yield a specific output deadtime at a given frequency. The oscillator thresholds are temperature compensated to within ±6% at 50 kHz. Also because of industry trends moving the UC384X into higher and higher frequency applications, the UC384XB is guaranteed to within ±10% at 250 kHz. These internal circuit refinements minimize variations of oscillator frequency and maximum output duty cycle. The results are shown in Figures 3 and 4. In many noise–sensitive applications it may be desirable to frequency–lock the converter to an external system clock. This can be accomplished by applying a clock signal to the circuit shown in Figure 20. For reliable locking, the free–running oscillator frequency should be set about 10% less than the clock frequency. A method for multi–unit synchronization is shown in Figure 21. By tailoring the clock waveform, accurate Output duty cycle clamping can be achieved. Error Amplifier A fully compensated Error Amplifier with access to the inverting input and output is provided. It features a typical dc voltage gain of 90 dB, and a unity gain bandwidth of 1.0 MHz with 57 degrees of phase margin (Figure 7). The non–inverting input is internally biased at 2.5 V and is not pinned out. The converter output voltage is typically divided down and monitored by the inverting input. The maximum input bias current is –2.0 µA which can cause an output voltage error that is equal to the product of the input bias current and the equivalent input divider source resistance. The Error Amp Output (Pin 1) is provided for external loop compensation (Figure 31). The output voltage is offset by two diode drops (≈1.4 V) and divided by three before it connects to the non–inverting input of the Current Sense Comparator. This guarantees that no drive pulses appear at the Output (Pin 6) when pin 1 is at its lowest state (VOL). This occurs when the power supply is operating and the load is removed, 8 or at the beginning of a soft–start interval (Figures 23, 24). The Error Amp minimum feedback resistance is limited by the amplifier’s source current (0.5 mA) and the required output voltage (VOH) to reach the comparator’s 1.0 V clamp level: Rf(min) ≈ 3.0 (1.0 V) + 1.4 V = 8800 Ω 0.5 mA Current Sense Comparator and PWM Latch The UC3842B, UC3843B operate as a current mode controller, whereby output switch conduction is initiated by the oscillator and terminated when the peak inductor current reaches the threshold level established by the Error Amplifier Output/Compensation (Pin 1). Thus the error signal controls the peak inductor current on a cycle–by–cycle basis. The Current Sense Comparator PWM Latch configuration used ensures that only a single pulse appears at the Output during any given oscillator cycle. The inductor current is converted to a voltage by inserting the ground–referenced sense resistor RS in series with the source of output switch Q1. This voltage is monitored by the Current Sense Input (Pin 3) and compared to a level derived from the Error Amp Output. The peak inductor current under normal operating conditions is controlled by the voltage at pin 1 where: V – 1.4 V Ipk = (Pin 1) 3 RS Abnormal operating conditions occur when the power supply output is overloaded or if output voltage sensing is lost. Under these conditions, the Current Sense Comparator threshold will be internally clamped to 1.0 V. Therefore the maximum peak switch current is: Ipk(max) = 1.0 V RS When designing a high power switching regulator it becomes desirable to reduce the internal clamp voltage in order to keep the power dissipation of RS to a reasonable level. A simple method to adjust this voltage is shown in Figure 22. The two external diodes are used to compensate the internal diodes, yielding a constant clamp voltage over temperature. Erratic operation due to noise pickup can result if there is an excessive reduction of the Ipk(max) clamp voltage. A narrow spike on the leading edge of the current waveform can usually be observed and may cause the power supply to exhibit an instability when the output is lightly loaded. This spike is due to the power transformer interwinding capacitance and output rectifier recovery time. The addition of an RC filter on the Current Sense Input with a time constant that approximates the spike duration will usually eliminate the instability (refer to Figure 26). MOTOROLA ANALOG IC DEVICE DATA UC3842B, 43B UC2842B, 43B Figure 17. Representative Block Diagram VCC VCC 7(12) 36V Vref Reference Regulator 8(14) R 2.5V RT Vin + – VCC UVLO Internal Bias R + – 3.6V (See Text) VC 7(11) Vref UVLO Output Q1 Oscillator CT 4(7) 6(10) + 1.0mA S Voltage Feedback Input 2(3) Output/ Compensation 1(1) 2R Q R Error Amplifier R Power Ground PWM Latch 1.0V Current Sense Comparator Gnd 5(8) Current Sense Input 3(5) RS 5(9) Pin numbers adjacent to terminals are for the 8–pin dual–in–line package. Pin numbers in parenthesis are for the D suffix SO–14 package. = Sink Only Positive True Logic Figure 18. Timing Diagram Capacitor CT Latch “Set” Input Output/ Compensation Current Sense Input Latch “Reset” Input Output Large RT/Small CT MOTOROLA ANALOG IC DEVICE DATA Small RT/Large CT 9 UC3842B, 43B UC2842B, 43B Undervoltage Lockout Two undervoltage lockout comparators have been incorporated to guarantee that the IC is fully functional before the output stage is enabled. The positive power supply terminal (VCC) and the reference output (Vref) are each monitored by separate comparators. Each has built–in hysteresis to prevent erratic output behavior as their respective thresholds are crossed. The VCC comparator upper and lower thresholds are 16 V/10 V for the UCX842B, and 8.4 V/7.6 V for the UCX843B. The Vref comparator upper and lower thresholds are 3.6 V/3.4 V. The large hysteresis and low startup current of the UCX842B makes it ideally suited in off–line converter applications where efficient bootstrap startup techniques are required (Figure 33). The UCX843B is intended for lower voltage dc–to–dc converter applications. A 36 V zener is connected as a shunt regulator from VCC to ground. Its purpose is to protect the IC from excessive voltage that can occur during system startup. The minimum operating voltage (VCC) for the UCX842B is 11 V and 8.2 V for the UCX843B. These devices contain a single totem pole output stage that was specifically designed for direct drive of power MOSFETs. It is capable of up to ±1.0 A peak drive current and has a typical rise and fall time of 50 ns with a 1.0 nF load. Additional internal circuitry has been added to keep the Output in a sinking mode whenever an undervoltage lockout is active. This characteristic eliminates the need for an external pull–down resistor. The SO–14 surface mount package provides separate pins for VC (output supply) and Power Ground. Proper implementation will significantly reduce the level of switching transient noise imposed on the control circuitry. This becomes particularly useful when reducing the Ipk(max) clamp level. The separate VC supply input allows the designer added flexibility in tailoring the drive voltage independent of VCC. A zener clamp is typically connected to this input when driving power MOSFETs in systems where VCC is greater than 20 V. Figure 25 shows proper power and control ground connections in a current–sensing power MOSFET application. Reference The 5.0 V bandgap reference is trimmed to ±1.0% tolerance at TJ = 25°C on the UC284XB, and ±2.0% on the UC384XB. Its primary purpose is to supply charging current to the oscillator timing capacitor. The reference has short– circuit protection and is capable of providing in excess of 20 mA for powering additional control system circuitry. Design Considerations Do not attempt to construct the converter on wire–wrap or plug–in prototype boards. High frequency circuit layout techniques are imperative to prevent pulse–width jitter. This is usually caused by excessive noise pick–up imposed on the Current Sense or Voltage Feedback inputs. Noise immunity can be improved by lowering circuit impedances at these points. The printed circuit layout should contain a ground plane with low–current signal and high–current switch and output grounds returning on separate paths back to the input filter capacitor. Ceramic bypass capacitors (0.1 µF) connected directly to VCC, VC, and Vref may be required depending upon circuit layout. This provides a low impedance path for filtering the high frequency noise. All high current loops should be kept as short as 10 possible using heavy copper runs to minimize radiated EMI. The Error Amp compensation circuitry and the converter output voltage divider should be located close to the IC and as far as possible from the power switch and other noise–generating components. Current mode converters can exhibit subharmonic oscillations when operating at a duty cycle greater than 50% with continuous inductor current. This instability is independent of the regulator’s closed loop characteristics and is caused by the simultaneous operating conditions of fixed frequency and peak current detecting. Figure 19A shows the phenomenon graphically. At t0, switch conduction begins, causing the inductor current to rise at a slope of m1. This slope is a function of the input voltage divided by the inductance. At t1, the Current Sense Input reaches the threshold established by the control voltage. This causes the switch to turn off and the current to decay at a slope of m2, until the next oscillator cycle. The unstable condition can be shown if a perturbation is added to the control voltage, resulting in a small ∆I (dashed line). With a fixed oscillator period, the current decay time is reduced, and the minimum current at switch turn–on (t2) is increased by ∆I + ∆I m2/m1. The minimum current at the next cycle (t3) decreases to (∆I + ∆I m2/m1) (m2/m1). This perturbation is multiplied by m2/m1 on each succeeding cycle, alternately increasing and decreasing the inductor current at switch turn–on. Several oscillator cycles may be required before the inductor current reaches zero causing the process to commence again. If m2/m1 is greater than 1, the converter will be unstable. Figure 19B shows that by adding an artificial ramp that is synchronized with the PWM clock to the control voltage, the ∆I perturbation will decrease to zero on succeeding cycles. This compensating ramp (m3) must have a slope equal to or slightly greater than m2/2 for stability. With m2/2 slope compensation, the average inductor current follows the control voltage, yielding true current mode operation. The compensating ramp can be derived from the oscillator and added to either the Voltage Feedback or Current Sense inputs (Figure 32). Figure 19. Continuous Current Waveforms (A) ∆I Control Voltage m2 m1 Dl ) Inductor Current Dl mm2 1 Dl ) Dl m2 m 1 m2 m1 Oscillator Period t0 t1 t2 t3 (B) Control Voltage ∆I m3 m1 m2 Inductor Current Oscillator Period t4 t5 t6 MOTOROLA ANALOG IC DEVICE DATA UC3842B, 43B UC2842B, 43B Figure 20. External Clock Synchronization Figure 21. External Duty Cycle Clamp and Multi–Unit Synchronization Vref 8(14) R 8(14) Bias RT R Bias 8 Osc 4(7) CT 5.0k 6 3 + 0.01 5 5.0k + 7 2R S R EA 4(7) Q 2 2(3) Osc R 2R 47 R 4 RB External Sync Input R RA 5.0k C 1(1) 2(3) MC1455 R EA 1 1(1) 5(9) The diode clamp is required if the Sync amplitude is large enough to cause the bottom side of CT to go more than 300 mV below ground. f + 1.44 (RA 2RB)C ) Figure 22. Adjustable Reduction of Clamp Level VCC D(max) + RA ) 2RB RB 5(9) To Additional UCX84XBs Figure 23. Soft–Start Circuit Vin 7(12) 5.0V Ref 8(14) 5.0V Ref 8(14) R R Bias + – Bias R R + – 7(11) + – Q1 Osc Osc 4(7) 4(7) 6(10) VClamp + R2 2(3) Q 2(3) R 2R R 1.0V 5(8) 3(5) VClamp ≈ ǒ )Ǔ R2 R1 1 + 0.33x10–3 ǒ)Ǔ R1R2 R1 R2 2R R R 1.0V 1(1) RS C 5(9) 1.67 Q EA 1.0M Comp/Latch 1(1) R1 S 1.0mA S 1.0 mA EA + Where: 0 ≤ VClamp ≤ 1.0 V Ipk(max) MOTOROLA ANALOG IC DEVICE DATA tSoft–Start ≈ 3600C in µF 5(9) [ VClamp RS 11 UC3842B, 43B UC2842B, 43B Figure 24. Adjustable Buffered Reduction of Clamp Level with Soft–Start VCC Figure 25. Current Sensing Power MOSFET VCC Vin Vin VPin 5 (12) 7(12) S Ipk rDS(on) [ RrDM(on) ) RS If: SENSEFET = MTP10N10M RS = 200 5.0V Ref 5.0V Ref 8(14) Bias R Then : VPin 5 + – + – R D 7(11) + – Q1 S G Osc 4(7) K 6(10) VClamp + (10) S 1.0 mA R 2R R EA R1 3(5) (8) RS (5) 5(9) MPSA63 VClamp tSoft-Start R Comp/Latch 1(1) C Q 5(8) Comp/Latch 1.0V R2 [ ǒ )Ǔ 1.67 R2 1 R1 ƪ ƫ C R1 R2 R2 R1 ) Ipk(max) [ VClamp RS Figure 26. Current Waveform Spike Suppression VCC Virtually lossless current sensing can be achieved with the implementation of a SENSEFET power switch. For proper operation during over–current conditions, a reduction of the Ipk(max) clamp level must be implemented. Refer to Figures 22 and 24. Figure 27. MOSFET Parasitic Oscillations Vin VCC 7(12) Vin 7(12) 5.0V Ref 5.0V Ref + – + – 7(11) + – 7(11) + – Rg Q1 6(10) S Q Comp/Latch Q1 6(10) S 5(8) Q R R 3(5) R C 5(8) Comp/Latch RS The addition of the RC filter will eliminate instability caused by the leading edge spike on the current waveform. 12 Power Ground: To Input Source Return RS 1/4 W Control Circuitry Ground: To Pin (9) Where: 0 ≤ VClamp ≤ 1.0 V C + * In 1 * 3 VVClamp M S Q 2(3) SENSEFET (11) + – [ 0.075 Ipk 3(5) RS Series gate resistor Rg will damp any high frequency parasitic oscillations caused by the MOSFET input capacitance and any series wiring inductance in the gate–source circuit. MOTOROLA ANALOG IC DEVICE DATA UC3842B, 43B UC2842B, 43B Figure 28. Bipolar Transistor Drive IB Figure 29. Isolated MOSFET Drive Vin Vin VCC + 7(12) 0 Isolation Boundary Base Charge Removal – 5.0V Ref + – C1 + – Q1 VGS Waveforms 7(11) + Q1 + 0 6(10) 0 – – 50% DC 6(10) S 5(8) 5(8) Q Ipk R 3(5) * 1.4 + V(Pin1) 3 RS NS Np R 3(5) Comp/Latch RS ǒǓ 25% DC C RS NS NP The totem pole output can furnish negative base current for enhanced transistor turn–off, with the addition of capacitor C1. Figure 30. Latched Shutdown Figure 31. Error Amplifier Compensation From VO 8(14) 2.5V + R Ri Bias R Rd Cf Osc 4(7) 2(3) EA EA Rf Rf ≥ 8.8 k 5(9) 2R Error Amp compensation circuit for stabilizing any current mode topology except for boost and flyback converters operating with continuous inductor current. R From VO 2.5V + 1(1) MCR 101 2N 3905 R 1(1) + 1.0 mA 1.0mA 2R 2(3) 5(9) 2N 3903 Rp Cp 1.0mA Ri Rd 2(3) Cf Rf EA 2R R 1(1) The MCR101 SCR must be selected for a holding of < 0.5 mA @ TA(min). The simple two transistor circuit can be used in place of the SCR as shown. All resistors are 10 k. MOTOROLA ANALOG IC DEVICE DATA 5(9) Error Amp compensation circuit for stabilizing current mode boost and flyback topologies operating with continuous inductor current. 13 UC3842B, 43B UC2842B, 43B Figure 32. Slope Compensation VCC Vin 7(12) 36V 5.0V Ref 8(14) RT Bias R MPS3904 RSlope From VO + – + 1.0mA Ri 2(3) Cf Rd 7(11) Osc 4(7) CT + – R –m R EA Rf 1(1) R 6(10) S 2R 1.0V Q 5(8) Comp/Latch 3(5) m – 3.0m RS 5(9) The buffered oscillator ramp can be resistively summed with either the voltage feedback or current sense inputs to provide slope compensation. Figure 33. 27 W Off–Line Flyback Regulator L1 MBR1635 4.7Ω + MDA 202 4.7k 250 3300 pF 56k 115 Vac T1 2200 + 1000 + 5.0V RTN MUR110 1N4935 7(12) + 1N4935 68 1000 + 1000 0.01 8(14) 10k R 10 + 10 + –12V/0.3A + – Bias R 12V/0.3A + ±12V RTN 1N4937 5.0V Ref + L2 47 100 5.0V/4.0A MUR110 680pF L3 7(11) + – 2.7k 22 1N4937 Osc 4700pF 4(7) 18k 2(3) 4.7k 1N5819 S 100 pF 150k MTP 4N50 6(10) + Q R EA 5(8) 1.0k Comp/Latch 3(5) 1(1) 0.5 470pF 5(9) L1 – 15 µH at 5.0 A, Coilcraft Z7156 L2, L3 – 25 µH at 5.0 A, Coilcraft Z7157 Test Conditions Results ∆ = 50 mV or ± 0.5% ∆ = 24 mV or ± 0.1% Line Regulation: 5.0 V ±12 V Vin = 95 to 130 Vac Load Regulation: 5.0 V Vin = 115 Vac, ∆ = 300 mV or ± 3.0% Iout = 1.0 A to 4.0 A Vin = 115 Vac, ∆ = 60 mV or ± 0.25% Iout = 100 mA to 300 mA ±12 V Output Ripple: Efficiency 5.0 V ±12 V Vin = 115 Vac 40 mVpp 80 mVpp Vin = 115 Vac 70% T1 – Primary: 45 Turns #26 AWG Secondary ±12 V: 9 Turns #30 AWG (2 Strands) Bifiliar Wound Secondary 5.0 V: 4 Turns (six strands) #26 Hexfiliar Wound Secondary Feedback: 10 Turns #30 AWG (2 strands) Bifiliar Wound Core: Ferroxcube EC35–3C8 Bobbin: Ferroxcube EC35PCB1 Gap: ≈ 0.10” for a primary inductance of 1.0 mH All outputs are at nominal load currents, unless otherwise noted 14 MOTOROLA ANALOG IC DEVICE DATA UC3842B, 43B UC2842B, 43B OUTLINE DIMENSIONS 8 N SUFFIX PLASTIC PACKAGE CASE 626–05 ISSUE K 5 NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. –B– 1 4 F DIM A B C D F G H J K L M N –A– NOTE 2 L C J –T– N SEATING PLANE D M K MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC ––– 10_ 0.76 1.01 INCHES MIN MAX 0.370 0.400 0.240 0.260 0.155 0.175 0.015 0.020 0.040 0.070 0.100 BSC 0.030 0.050 0.008 0.012 0.115 0.135 0.300 BSC ––– 10_ 0.030 0.040 G H 0.13 (0.005) T A M M B M D1 SUFFIX PLASTIC PACKAGE CASE 751–06 (SO–8) ISSUE T D A 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS ARE IN MILLIMETER. 3. DIMENSION D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. C 5 0.25 H E M B M 1 4 h B e X 45 _ q A C SEATING PLANE L 0.10 A1 B 0.25 M C B S A S MOTOROLA ANALOG IC DEVICE DATA DIM A A1 B C D E e H h L q MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.35 0.49 0.19 0.25 4.80 5.00 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.25 0_ 7_ 15 UC3842B, 43B UC2842B, 43B OUTLINE DIMENSIONS D SUFFIX PLASTIC PACKAGE CASE 751A–03 (SO–14) ISSUE F –A– 14 8 –B– 1 P 7 PL 0.25 (0.010) 7 G M B F –T– M K D 14 PL 0.25 (0.010) M T B S M R X 45 _ C SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. A S J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. 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