TS3842B/3843B High Performance Current Mode Controller Designed for Off-Line and DC-to-DC converter applications. DIP-8 SOP-8 General Description The TS3842B and TS3843B series are high performance fixed frequency current mode controllers. This is specifically designed for Off-Line and DC-to-DC converter applications offering the designer a cost effective solution with minimal external components. This integrated circuits feature a trimmed oscillator for precise duty cycle control, a temperature compensated reference, high gain error amplifier, current sensing comparator, and a high current totem pole output ideally suited for driving a power MOSFET. Also included are protective features consisting of input and reference undervoltage lockouts each with hysteresis, cycle-by-cycle current limiting, programmable output deadtime, and a latch for single pulse metering. This device is available in 8-pin dual-in-line plastic packages as well as the 8-pin plastic surface mount (SOP-8). The SOP-8 package has separate power and ground pins for the totem pole output stage. The TS3842B has UVLO thresholds of 16V (on) and 10V (off), ideally suited for off-line converters. Features Trimmed Oscillator Discharge Current for Precise Duty Cycle Control Current Mode Operation to 500KHz Automatic Feed Forward Compensation Latching PWM for Cycle-By-Cycle Current Limiting Block Diagram Ordering Information VCC Vref 5.0V Reference 8(14) R R RT /CT 4(7) Voltage Feedback Input 2(3) Output Compensation 1(1) Vref Undervoltage Lockout 7(12) VCC Undervoltage Lockout DEVICE VC 7(11) Output Oscillator Latching PWM + - Error Amplifier Internally Trimmed Reference with Undervoltage Lockout High Current Totem Pole Output Undervoltage Lockout with Hystersis Low Start-Up and Operating Current 6(10) Power Ground 5(8) Current Sense 3(5)Input The document contains information on a new product.Specifications and information herein are subject to change without notice. TS3842/3843BCD TS3842/3843BCS OPERATING TEMPERATURE (Ambient) -20 to +85 PACKAGE DIP-8 SOP-8 Absolute Maximum Ratings RATING SYMBOL VALUE UNIT Total Power Supply and Zener Current (ICC+IZ) 30 mA Output Current Source or Sink (Note 1) Io 1.0 A Output Energy (Capacitive Load per Cycle) W 5.0 µJ Current Sense and Voltage Feedback Inputs Vin -0.3 to +5.5 V Error Amp Output Sink Current Io 10 mA PD RθJA 862 145 mW /W PD RθJA 1.25 100 W /W Operating Junction Temperature TJ 0 to +150 Operating Ambient Temperature TA Power Dissipation and Thermal Characteristics Plastic DIP Maximum Power Dissipation @ TA=25 Thermal Resistance Junction to Air Plastic SOP Maximum Power Dissipation @ TA=25 Thermal Resistance Junction to Air Storage Temperature Range Tstg to +85 -25 to +150 -20 Electrical Characteristics VCC=15V (Note 2), RT=10K, CT=3.3nF, TA=Tlow to Thigh (Note 3), unless otherwise noted. CHARACTERISTIC SYMBOL MIN TYP MAX UNIT Vref 4.9 5.0 5.1 V Line Regulation (VCC =12V to 25V) Regline - 2.0 20 mV Load Regulation (Io =1.0mA to 20mA) Regload - 3.0 25 mV Ts - 0.2 - mV/ Vref 4.82 - 5.18 V Output Noise Voltage (f = 10Hz to 10kHz, TJ=25) Vn - 50 - µV Long Term Stability ( TA=125 for 1000 Hours) S - 5.0 - mV Isc -30 -85 180 mA Fosc 47 52 57 KHz 46 - 60 fosc/V - 0.2 1.0 % fosc/T - 5.0 - % Vosc - 1.6 - V Idischg 7.5 8.4 9.3 mA 7.2 - 9.5 REFFRENCE SECTION Reference Output Voltage (Io=1.0mA,TJ = 25) Temperature Stability Total Output Variation over Line,Load ,and Temperature Output Short Circuit Current OSCILLATOR SECTION Frequency TJ=25 TA=Tlow to Thigh Frequency Change with Voltage (VCC =12V to 25V) Frequency Change with Temperature TA=Tlow to Thigh Oscillator Voltage Swing ( Peak-to-Peak) Discharge Current (Vosc=2.0V) TJ=25 TA=Tlow to Thigh Electrical Characteristics VCC=15V (Note 2), RT=10K, CT=3.3nF, TA=Tlow to Thigh (Note 3), unless otherwise noted. CHARACTERISTIC SYMBOL MIN TYP MAX UNIT VFB 2.42 2.5 2.58 V IIB - -0.1 -2.0 aA Open-Loop Voltage Gain (Vo=2.0V to 4.0V) AVOL 65 90 - dB Unity Gain Bandwidth (TJ=25) BW 0.7 1.0 - MHz PSRR 60 70 - dB Isink 2.0 12 - mA ISource -0.5 -1.0 - High State (RL=15K to ground, VFB=2.3V) VOH 5.0 6.2 - Low State (RL=15K to Vref, VFB=2.7V) VOL - 0.8 1.1 Current Sense Input Voltage Gain (Note 4&5) Av 2.85 3.0 3.15 V/V Maximum Current Sense Input Threshold(Note 4) Vth 0.9 1.0 1.1 V PSRR - 70 - dB IIB - -2.0 -10 µA tPLH(IN/OUT) - 150 300 ns ERROR AMPLIFIER SECTION Voltage Feedback Input (Vo=2.5V) Input Bias Current (VFB=5.0V) Power Supply Rejection Radio (VCC=12V to 25V) Output Current Sink (Vo=1.1V, VFB =2.7V) Source ( Vo=5.0V, VFB =2.3V) Output Voltage Swing V CURRENT SENSE SECTION Power Supply Rejection Radio VCC=12V to 25V,Note 4 Input Bias Current Propagation Delay(Current Sense Input to Output) Electrical Characteristics VCC=15V (Note 2), RT=10K, CT=3.3nF, TA=Tlow to Thigh (Note 3), unless otherwise noted. CHARACTERISTIC SYMBOL MIN TYP MAX UNIT VOL - 0.1 0.4 - 1.6 2.2 VOH 13 13.5 - 12 13.4 - VOL(UVLO) - 0.1 1.1 V Output Voltage Rise Time (CL=1.0nF,TJ=25) tr - 50 150 ns Output Voltage Fall Time (CL=1.0nF,TJ=25) tf - 50 150 ns Vth 14.5 16 17.5 V 7.8 8.4 9.0 8.5 10 11.5 7.0 7.6 8.2 OUTPUT SECTION Output Voltage Low State (Isink=20mA) (Isink=200mA) High State (Isource=20mA) (Isource=200mA) Output Voltage with UVLO Activated V VCC=6.0V,Isink=1.0mA UNDERVOLTAGE LOCKOUT SECTION Start-Up Threshold TS3842B TS3843B Minimum Operating Voltage After Turn-On TS3842B VCC(min) TS3843B V PWM SECTION Duty Cycle Maximum DCmax 94 96 - Minimum DCmin - - 0 ICC - 0.25 0.5 - 12 17 Vz 30 36 - % TOTAL DEVICE Power Supply Current Start-Up, VCC= 14V Operating (Note 2) Power Supply Zener Voltage (ICC=25mA) Note: 1. Maximum package power dissipation limits must be observed. 2. Adjust VCC above the Start-Up threshold before setting to 15V. 3. Low duty cycle pulse technique are used during test to maintain junction temperature as close to ambient as possible. Tlow = -20 ,Thigh = +85 4. This parameter is measured at the latch trip point with VFB = 0V. V Output Compensation 5. Comparator gain is defined as : Av = V Current Sense Input mA V Figure 2 - Output Dead Time vs. Oscillator Frequency Figure 1 - Timing Resistor vs. Oscillator Frequency 80 100 % DT. PERCENT OUTPUT DEAD-TIME RT. TIMING RESISTOR (KΩ) 20 20 8.0 5.0 2.0 0.8 10K 50 20 10 5.0 2.0 1.0 10K 20K 50K 100K 200K 500K 1.0M fosc, OSCILLATOR FREQUENCY (KHz) 20K 50K 100K 200K 500K 1.0M fosc, OSCILLATOR FREQUENCY (KHz) Figure 4 - Maximum Output Duty Cycle vs. Timing Resistor Figure 3 - Oscillator Discharge Current vs. Temperature 100 Dmax. MAXIMUM OUTPUT DUTY CYCLE (%) Idischg. DISCHARGE CURRENT (mA) 9.0 8.5 8.0 7.5 7.0 -55 -25 0 25 50 75 100 90 80 70 60 50 40 800 1.0K 125 TA. AMBIENT TEMPERATURE (oC) 2.0K 3.0K 4.0K 6.0K 8.0K RT. TIMING RESISTOR (Ω) Figure 5 - Error Amp Small Figure 6 - Error Amp Large Signal Transient Response Signal Transient Response 2.55V 2.5V 2.45V 200mA/DIV 20mV/DIV 3.0V 2.5V 2.0V 0.15µs/DIV 10µs/DIV Figure 8 - Current Sense Input Threshold vs. Error Amp Output voltage 0 80 30 60 60 40 90 20 120 0 150 -20 10 1.2 Vth. CURRENT SENSE INPUT THRESHOLD (V) 100 EXCESS PHASE (DEGREES) Avol.OPEN-LOOP VOLTAGE GAIN (dB) Figure 7 - Error Amp Open-Loop Gain and Phase vs. Frequency 180 100 1.0K 10K 100K 1.0M 1.0 0.8 0.6 0.4 0.2 0 10M 0 Figure 9 - Reference Voltage Change vs. Source Current 6.0 8.0 110 Isc. REFERENCE CIRCUIT CURRENT (mA) rVref. REFERENCE VOLTAGE CHANGE (mV) 4.0 Figure 10 - Reference Short Circuit Current vs. Temperature 0 -4.0 -8.0 -12 -16 -20 -24 0 2.0 Vo. ERROR OUTPUT VOLTAGE (Vo) f. FREQUENCY (Hz) 20 40 60 80 100 70 50 -55 120 Iref.REFERENCE SOURCE CURRENT (mA) -25 0 25 50 100 125 Figure 12 - Reference Line Regulation rVo.OUTPUT VOLTAGE CHANGE (2.0mV/DIV) 2.0ms/DIV 75 TA. AMBIENT TEMPERATURE (oC) Figure 11 - Reference Load Regulation rVo.OUTPUT VOLTAGE CHANGE (2.0mV/DIV) 90 2.0ms/DIV Figure 13 - Output Saturation Voltage vs. Load Current Figure 14 - Output Waveform Vsat. OUTPUT SATURATION VOLTAGE (V) 0 -1.0 -2.0 90% 3.0 2.0 10% 1.0 0 0 200 400 600 800 50ns / DIV Io. OUTPUT LOAD CURRENT (mA) Figure 16 - Supply Current vs. Supply Voltage Figure 15 - Output Cross Conduction 20 Icc. SUPPLY CURRENT (mA) 100mA / DIV Icc. SUPPLY CURRENT 20V / DIV Vo. OUTPUT VOLTAGE 25 15 10 5 0 0 10 20 30 50ns / DIV Vcc. SUPPLY VOLTAGE (V) 40 Figure 17- Representative Block Diagram VCC VCC 7(12) 36V Vref Reference Regulator 8(14) R VCC UVLO Internal Bias 2.5V RT Vin R 3.6V + - + - (See Text) VC 7(11) Vref UVLO Output Q1 Oscillator CT 4(7) 6(10) + 1.0mA S Voltage Feedback Input 2(3) Output/ Compensation 1(1) 2R Q R Error Amplifier R PowerGround PWM Latch 1.0V Current Sense Comparator Gnd 5(8) Current Sense Input 3(5) 5(9) Pin numbers adjacent to terminals are for the 8-pin dual-in-line package. Pin numbers in parenthesis are for the D suffix SOP-14 package. = Sink Only Positive True Logic Figure 18 - Timing Diagram Capacitor CT Latch "Set" Input Output/ Compensation Current Sense Input Latch "Reset" Input Output Large R T /Small C T RS Small RT /Large C T Undervoltage Lockout Two undervoltage lockout comparators have been incorporated to guarantee that the IC is fully functional before the output stage is enabled. The positive power supply terminal (Vcc) and the reference output (Vref) are each monitored by separate comparators. Each has built-in hysteresis to prevent erratic output behavior as their respective thresholds are crossed. The large hysteresis and low start-up current of the TS3842B makes it ideally suited in off-line converter applications where efficient bootstrap start-up technique (Figure 33). 36V zener is connected as a shunt regulator from Vcc to ground. Its purpose is to protect the IC from excessive voltage that can occur during system start-up. The minimum operating voltage for the TS3842B is 11V. Output These devices contain a single totem pole output stage that was specifically designed for direct drive of power MOSFET’s. It is capable of up to ±1.0A peak drive current and has a typical rise and fall time of 50 ns with a 1.0nF load. Additional internal circuitry has been added to keep the output in a sinking mode whenever an undervoltage lockout is active. This characteristic eliminates the need for an external pull-down resistor. The SOP-8 surface mount package provides separate pins for Vc(output supply) and Power Ground. Proper implementation will significantly reduce the level of switching transient noise imposed on the control circuitry. This becomes particularly useful when reducing the Ipk(max) clamp level. The separate Vc supply input allows the designer added flexibility in tailling the drive voltage independent of Vcc. A zener clamp is typically connected to this input when driving power MOSFETs in systems where Vcc is greater than 20V. Figure 25 shows proper power and control ground connections in a current sensing power MOSFET application. Reference The 5.0V bandgap reference is trimmed to ±2.0% on the TS3842B. Its primary purpose to supply charging current to the oscillator timing capacitor. The reference has short circuit protection and is capable of providing in excess of 20mA for powering additional control system circuitry. Design Considerations Do not attempt to construct the converter on wire wrap or plug-in prototype boards. High frequency circuit layout techniques are imperative to prevent pulsewidth jitter. This is usually caused by excessive noise pick-up imposed on the Current Sense or Voltage Feedback inputs. Noise immunity can be improved by lowering circuit impedances at these points. The printed circuit layout should contain a ground plane with low-current signal and high-current switch and output grounds returning separate paths back to the input filter capacitor. Ceramic bypass capacitors (0.1µF) connected directly to Vcc,Vc, and Vref may be required depending upon circuit layout. Undervoltage Lockout(contd.) This provides a low impedance path for filtering the high frequency noised. All high current loops should be kept as short as possible using heavy copper runs to minimize radiated EMI. The Error Amp compensation circuitry and the converter output voltage divider should be located close to the IC and as far as possible from the power switch and other noise generating components. Figure 19 - Continuous Current Waveforms (A) ∆1 Control Voltage m2 m1 Inductor Current m2 ∆ 1 + ∆1 m 1 ∆ 1 + ∆1 m2 m2 m1 m 1 Oscillator Period t0 t1 t2 t3 (B) Control Voltage m3 m1 m2 Inductor Current Oscillator Period t4 t5 t6 Current mode converters can exhibit subharmonic oscillations when operating at a duty cycle greater than 50% with continuous inductor current. This instability is independent of the regulators closed loop characteristics and is caused by the simultaneous operating conditions of fixed frequency and peak current detecting. Figure 19(A) shows the phenomenon graphically. At t0, switch conduction begins causing the inductor current to rise at a slope of m1. This slope is a function of the input voltage divided by the inductance. At t1, the Current Sense Input reaches the threshold established by the control voltage. This causes the switch to turn off and the current to decay at a slope of m2, until the next oscillator cycle. This unstable condition can be shown if a perturbation is added to the control voltage, resulting in a small 1(dashed line). With a fixed oscillator period, the current decay time is reduced, and the minimum current at switch turn-on(t2) 1+ 1m2/m1. The minimum current at the next cycle (t3) decreases to ( is increased by 1+ 1m2/m1)(m2/m1). This perturbation is multiplied by m2/m1 on each succeeding cycle, alternately increasing and decreasing the inductor current at switch turn-on. Several oscillator cycles may be required before the inductor current reaches zero causing the process to commence again. If m2/ m1 is greater than 1, the converter will be unstable. Figure 19(B) shows that by adding an artificial ramp that is synchronized with the PWM clock to the control voltage, the 1 perturbation will decrease to zero on succeeding cycles. This compensating ramp (m3) must have a slope equal to or slightly greater than m2/2 for stability. With m2/2 slope compensation, the average inductor current follows the control voltage yielding true current mode operation. The compensating ramp can be derived from the oscillator and added to either the Voltage Feedback or Current Sense inputs (Figure 32). Undervoltage Lockout(contd.) Figure 20 - External Clock Synchronization Figure 21 - External Duty Cycle Clamp and Multi Unit Synchronization Vref 8(14) 8(14) R Bias 8 R RB 6 External Sync Input 4(7) 5.0k 3 4 2(3) Osc R 5 + 0.01 R 4 Osc CT R RA Bias RT R 4(7) Q 2 2R EA 5.0k 2R S 2(3) 5.0k C + 7 R EA 1 1(1) 1(1) f = 1.44 (RA + R B) D m ax = 5(9) To Additional TS384X's 5(9) RB R A + 2R B The diode clamp is required if the Sync amplitude is large enough to cause the bottom side of CT to go more than 300mV below ground. Firuge 22-Adjustable Reduction of Clamp Level Figure 23- Soft-Start Circuit Vin VCC 7(12) 5.0V Ref 8(14) Vref R 5.0V Ref 8(14) Bias R + - Bias R R + - 7(11) + - Q1 Osc Osc 4(7) + R2 4(7) 6(10) VClamp 1.0mA Q EA 2(3) + S 1.0 mA 2(3) R 2R R ( 1.0V RS 1(1) 5(9) V Ipk(max) = Clamp RS 1.67 VClamp = R2 +1 R1 R EA 1.0M 3(5) 1(1) R1 Q R Comp/Latch 1.0V S 2R 5(8) C 5(9) Where: 0 ɷVClamp ɷ 1.0 V + 0.33x10 ) -3 ISoft-Start=3600c in µF R R ( R11+ R2 2 ) Figure 24- Adjustable Buffered Reduction of Clamp Level with Soft-Start Figure 25- Current Sensing Power MOSFET Vin VCC Vpin 5 (12) Rs 5.0V Ref 5.0V Ref 8(14) Bias + - S K 2(3) R Q S 2R R Q R EA M S + 1.0mA 1.0M 0.075 Ipk G (10) Osc 4(7) = D SENSEFET (11) + - R RS Ipk x rDS(on) rDM(on) + RS Then : Vpin 5 + - R = If: SENSEFET = MTP10N10M R S = 200 1.0V (8) Comp/Latch (5) RS 1/4 W Power Ground: To Input Source Return Control Circuitry Ground: To pin (9) 1(1) C 5(9) Virtually lossless current sensing can be achieved with the implementation of a SENSEFET power switch. For proper operation during over current conditions, a reduction of the Ipk(max) clamp level must be implemented. Refer to Figure 22 and 24. Undervoltage Lockout(contd.) Figure 26- Current Waveform Spike Suppression VCC Figure 27- MOSFET Parasitic Oscillations VCC Vin 7(12) Vin 7(12) 5.0V Ref 5.0V Ref + - + 7(11) + - 7(11) + - Q1 Rg 6(10) S S 5(8) Q Q1 6(10) Q R R 3(5) Comp/Latch 5(8) R Comp/Latch C RS 3(5) RS The addition of RC filter will eliminate instability caused by the leading edge spike on the current waveform. Figure 28- Bipolar Transistor Drive IB Figure 29- Isolated MOSFET Drive V in VCC Vin + 7(12) Isolation Boundary 0 Base Charge Removal - 5.0V Ref + - VGS Waveforms 7(11) + - C1 Q1 + + 0 0 - - Q1 50% DC 6(10) 6(10) S Q 5(8) Ip k = R 5(8) Comp/Latch R 3(5) C 3(5) RS The totem-pole output can finish negative base current for enhanced transistor turn-off with the additions of capacitor C1. Figure 30- Latched Shutdown 8(14) R Bias R Osc 4(7) + 1.0 mA 2(3) EA 2R R 1(1) MCR 101 2N 3905 5(9) 2N 3903 The MCR101 SCR must selected for a holding of less than 0.5mA at TA(min.). The simple two transistor circuit can be used in place of the SCR as shown. All resistors are 10k. RS NS NP 25% DC V(p in1) _ 1.4 N S (N ) 3 RS p Undervoltage Lockout(contd.) Figure 31-Error Amplifier Compensation From VO 2.5V + Ri Rd 1.0mA 2R 2(3) Cf EA Rf R 1(1) 5(9) Error Amp compensation circuit for stabilizing any current mode topology except for boost and flyback converters operating with continuous inductor current. From VO 2.5V + Rp Cp Ri 1.0mA 2R 2(3) Rd Cf R EA Rf 1(1) 5(9) Figure 32-Slope Compenstaion VCC Vin 7(12) 36V 8(14) RT Rslope CT Rd Bias + + 2(3) Cf Rf 1(1) 7(11) Q1 Osc 4(7) 1.0mA Ri + - R R MPS3904 From VO 5.0V Ref 6(10) -m S 2R R EA R 1.0V 5(8) Comp/Latch m - 3.0m Q 3(5) RS 5(9) The buffered oscillator ramp can resistively summed with either the voltage feedback or current sense inputs to provide slope compensation. Undervoltage Lockout(contd.) Figure 33-27 Watt Off-Line Regulation L1 MBR1635 4.7W + MDR 202 4.7k 250 + 3300 56k 115 Vac T1 2200 pF + + 1000 5.0V RTN MUR1 10 1N4935 1N4935 7(12) + 68 1000 + 0.01 1000 8(14) 10k 1N4937 R + 10 + -12V/0.3A + - Bias R + 10 + -12V RTN Vref 5.0VRef 12V/0.3A + L2 47 100 5.0V/4.0A MUR1 10 680pF L3 7(11) + - 2.7k 22 1N4937 Osc 4700pF 4(7) 1.0mA 18k S 2(3) 4.7k 100 pF 150k MTP 4N50 6(10) + Q EA 2R 1.0V R 5(8) 1.0k Comp/Latch R 3(5) 1(1) 0.5 470pF 5(9) TEST CONDITIONS Line Regulation: 5.0V RESULTS =50mV or ±0.5% T1 Primary : 45 Turns #26 AWG Vin=95 to 130 Vac ±12V Load Regulation: 5.0V ±12V Output Ripple: =24mV or ±0.1% Vin=115Vac, Iout =1.0A to 4.0A =300mV or ±3.0% Vin=115Vac,Iout=100mA to 300mA =60mV or ±0.25% 5.0V 40mVp-p Vin=115Vac ±12V Efficiency Secondary ±12V : 9 Turns #30 AWG (2 strands ) Bifiliar Wound. Secondary 5.0V : 4 Turns (six strands) #26 Hexfiliar Wound. 80 Vp-p Vin=115Vac 70% All outputs are at nominal load currents unless otherwise noted. Secondary Feedback : 10 Turns #30 AWG (2 strands) Bifiliar Wound. Core : Ferroxcube EC35-3C8 Bobbin : Ferroxcube EC35PCB1 Gap : ≅@0.10” for a primary inductance of 1.0mH. L1: 15µH at 5.0A, Coilcraft 27156. L2,L3: 25µH at 1.0A, Coilcraft 27157. Undervoltage Lockout(contd.) Figure 34-33 Watt Off-Line Flyback Converter with Soft-Start and Primary Power Limiting 1N4003 3 each 0.0047 UL / CSA 3/200 Vac 1N4001 1N5824 1N4934 2200 /10V 1N4934 47 / 25V 22K 1N4742 1 1.0A T 15 Cold 1N4687 180/ 200V 3 Comp 6.8K 14 PJ34060 7.5K Pout 5.0K Pout 25K E 13 8.2K 0.01 1.5K 12 Vref CT DT 10 5 4 0.001 27K TEST 1000 /25V 1000 /25V 9 CONDITIONS Vin=95 to 135 Vac, Io=3.0A MPS A05 10/25V 8 Gnd 7 RT 6 200 47 2.7K RESULTS 20mV 0.40% Vin=95 to 135 Vac, Io=±0.75A 52mV 0.26% Vin=115 Vac, Io=1.0 to 4.0A 476mV 9.5% Line Regulation± 12V Vin=115 Vac, Io=±0.4 to ±0.9A 300mV 2.5% Line Regulation 5.0V Vin=115 Vac, Io=3.0A 45 mVp-p P.A.R.D. Line Regulation± 12V Vin=115 Vac, Io=±0.75A 75 mV p-p P.A.R.D. Io(±12V)=±0.75A MJE 13005 1.0 Line Regulation 5.0V Vin=115 Vac, Io(5.0V)=3.0A L3 1N4934 12V /0.75A Common 10 /35V 12V /0.75A 47K Line Regulation± 12V Efficiency 5.0V /3.0A MPS A55 11K 1N4148 Line Regulation 5.0V C 2 33K 0.01 2.2M Optional R.F.I Filter 10 Vcc L1 100 /10V L2 10 /35V 74% T1 Coilcraft 11-464-16, 0.025” gap in each leg Bobbin : Coilcraft 37-573 Windings: Primary, 2 each: 75 turns #26 Awg Bifilar wound Feedback: 15 turns #26 Awg Secondary , 5.0V: 6 turns #22 Awg Bifilar wound Secondary , 5.0V: 14 turns #24 Awg Bifilar wound L1 Coilcraft Z7156. 15µF @ 5.0A L2,L3 Coilcraft Z7157. 25µF @ 1.0A Pin Function Description PIN NO. FUNCTION DESCRIPTION 1 Compensation This pin is the Error Amplifier output and is made available for loop compensation 2 Voltage Feedback This is the inverting input of the Error Amplifier. It is normally connected to the switching power supply output through a resistor divider. 3 Current Sense A voltage proportional to inductor current is connected to this input. The PWM uses this information to terminate the output switch conduction. 4 RT/CT The Oscillator Frequency and maximum Output duty are programmed by connecting resistor RT to Vref and capacitor CT to ground operation to 500kHz is possible 5 Gnd This pin is the combined control circuitry and power ground (8-pin package only). 6 Output 7 Vcc This pin is the positive supply of the control IC. 8 Vref This pin is the reference output. It provides charging current for capacitor CT through resistor RT. This output directly drives the gate of a power MOSFET. Peak current up to 1.0A are sourced and sunk by this pin. DIP-8 8 SOP-8 5 8 5 1 1 4 PIN : 1. Compensation 2. Voltage feedback 3. Current Sense 4. RT / CT 5. Gnd 6. Output 7. VCC 8. Vref 4 Operating Description The TS3842B series are high performance, fixed frequency, current mode controllers. They are specifically designed for Off-Line and DC-to-DC converter applications offering the designer a cost effective solution with minimal external components. A representative block diagram is shown in Figure 17. Oscillator The oscillator frequency is programmed by the values selected for the timing components RT and CT . Capacitor CT is charged from the 5.0V reference through resistor RT to approximately 2.8V and discharge to 1.2V by an internal current sink. During the discharge of CT, the oscillator generates an internal blanking pulse that holds the center input of the NOR gate high. This causes the Output to be in a low state, thus producing a controlled amount of output deadtime. Figure 1 shows RT versus Oscillator Frequency and Figure 2, Output Deadtime versus Oscillator Frequency, both for given values of CT . Note that many values of RT and C T will give the same oscillator frequency but only one combination will yield a specific output deadtime at a given frequency. The oscillator thresholds are temperature compensated, and the discharge current is . These internal circuit refines minimum trimmed and guaranteed to within ±10% at TJ =25 variations of oscillator frequency and maximum output duty cycle. The results are shown in Figure 3 and 4. In many noise sensitive applications it may be desirable to frequency-lock the converter to an external system clock. This can be accomplished by applying a clock signal to the circuit shown in Figure 20 for reliable locking. The free-running oscillator frequency should be set about 10% less than the clock frequency. A method for multi unit synchronization is shown in Figure 21. By tailling the clock waveform, accurate Output duty cycle clamping can be achieved. Error Amplifier A fully compensated Error Amplifier with access to the inverting input and output is provided. It features a typical DC voltage gain of 90dB, and a unity gain bandwidth of 1.0MHz with 57 degrees of phase margin (Figure 7). The non-inverting input is internally biased at 2.5V and is not pinned out. The converter output voltage is typically divided down and monitored by the inverting input. The maximum input bias current is -2.0µA which can cause an output voltage error that is equal to the product of the input bias current and the equivalent input divider source resistance. The Error Amp Output (Pin 1) is provided for external loop compensation (Figure 31). The output ≈1.4V) and divided by three before it connects to the inverting voltage is offset by two diode drops (≈ input of the Current Sense Comparator. This guarantees that no drive pulses appear at the Output (Pin 6) when Pin 1 is at its lowest state (VOL). This occurs when the power supply is operating and the load is removed, or at the beginning of a soft-start interval (Figure 23,24). The Error Amp minimum feedback resistance is limited by the amplifier’s source current (0.5mA) and the required output voltage (VOH) to reach the comparator’s 1.0V clamp level: Rf(MIN) = [3x(1.0V)+1.4V] / 0.5mA = 8800Ω Current Sense Comparator and PWM Latch The TS3842B operate as a current mode controller, whereby output switch conduction is initiated by the oscillator and terminated when the peak inductor current reaches the threshold level established by the Error Amplifier Output/Compensation (Pin 1). Thus the error signal controls the peak inductor current on a cycle-by-cycle basis. The Current Sense Comparator PWM Latch configuration used ensures that only a single appears at the Output during any given oscillator cycle. The inductor current is converted to a voltage by inserting the ground referenced sense resistor RS in series with the source of output switch Q1. This voltage is monitored by the Current Sense Input (Pin 3) and compared to a level derived from the Error Amp Output. The peak inductor current under normal operating conditions is controlled by the voltage at pin 1 where: IPK = [V(Pin 1) - 1.4V] / 3RS Abnormal operating conditions occur when the power supply output is overloaded or if output voltage sensing is lost. Under these conditions, the Current Sense Comparator threshold will be internally clamped to 1.0V. Therefore the maximum peak switch current is: IPK (MAX) = 1.0V / RS When designing a high power switching regulator it becomes desirable to reduce the internal clamp voltage in order to keep the power dissipation of RS to a reasonable level. A simple method to adjust this voltage is shown in Figure 22. The two external diodes are used to compensate the internal diodes yielding a constant clamp voltage over temperature. Erratic operation due to noise pickup can result if there is an excessive reduction of the IPK (max) clamp voltage. A narrow spike on the leading edge of the current waveform can usually be observed and may cause the power supply to exhibit an instability when the output is lightly loaded. This spike is due to the power transformer interwinding capacitance and output rectifier recovery time. The addition of an RC filter on the Current Sense Input with a time constant that approximates the spike duration will usually eliminate the instability: refer to Figure 26. DIP-8 MILLIMETERS INCHES A B C D G MIN MAX 9.07 9.32 6.22 6.48 3.18 4.43 0.35 0.55 2.54BSC MIN MAX 0.357 0.367 0.245 0.255 0.125 0.135 0.019 0.020 0.10BSC SYMBOLS 8 5 B 1 4 A L C J D J 0.29 0.31 0.011 K 3.25 3.35 0.128 0.012 0.132 L 7.75 8.00 0.305 0.315 M - 10° - 10° M K G SOP-8 SYMBOLS A 8 5 P B 1 4 G C K D R X 45 O M F J A B C D F G K M P R MILLIMETERS INCHES MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27BSC MIN MAX 0.189 0.196 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.05BSC 0.10 0° 5.80 0.25 0.004 0° 0.229 0.010 0.25 7° 6.20 0.50 0.009 7° 0.244 0.019