ONSEMI MC33363BDWR2

MC33363B
High Voltage Switching
Regulator
The MC33363B is a monolithic high voltage switching regulator
that is specifically designed to operate from a rectified 240 Vac line
source. This integrated circuit features an on−chip 700 V/1.0 A
SENSEFETt power switch, 500 V active off−line startup FET, duty
cycle controlled oscillator, current limiting comparator with a
programmable threshold and leading edge blanking, latching pulse
width modulator for double pulse suppression, high gain error
amplifier, and a trimmed internal bandgap reference. Protective
features include cycle−by−cycle current limiting, input undervoltage
lockout with hysteresis, overvoltage protection, and thermal
shutdown. This device is available in a 16−lead dual−in−line and wide
body surface mount packages.
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MARKING
DIAGRAMS
16
SO−16WB
DW SUFFIX
CASE 751N
1
MC33363BDW
AWLYYWWG
Features
•
•
•
•
•
•
•
•
•
•
On−Chip 700 V, 1.0 A SENSEFET Power Switch
Rectified 240 Vac Line Source Operation
On−Chip 500 V Active Off−Line Startup FET
Latching PWM for Double Pulse Suppression
Cycle−By−Cycle Current Limiting
Input Undervoltage Lockout with Hysteresis
Over−Voltage Protection
Trimmed Internal Bandgap Reference
Internal Thermal Shutdown
Pb−Free Packages are Available*
A
WL
YY
WW
G
PIN CONNECTIONS
AC Input
1
VCC
3
16
4
13
5
12
RT
6
11
CT
7
10
Regulator Output
8
9
Startup
Mirror
VCC
8
UVLO
6
OVP
RT
PWM Latch
Osc
7
Driver
S
Q
DC Output
Ipk
Overvoltage
Protection Input
Voltage Feedback
Input
Compensation
(Top View)
11
16
ORDERING INFORMATION
Power Switch
Drain
Package
Shipping†
MC33363BDW
SO−16WB
47 Units/Rail
MC33363BDWG
SO−16WB
(Pb−Free)
47 Units/Rail
9
MC33363BDWR2
SO−16WB 1000 Tape & Reel
10
MC33363BDWR2G SO−16WB 1000 Tape & Reel
(Pb−Free)
R
PWM
LEB
Device
Compensation
Thermal
EA
GND
3
Overvoltage
Protection
Input
Power Switch
Drain
GND
1
Reg
CT
Startup Input
GND
Startup Input
Regulator
Output
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
4, 5, 12, 13
Voltage
Feedback
Input
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Figure 1. Simplified Application
*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2005
November, 2005 − Rev. 6
1
Publication Order Number:
MC33363B/D
MC33363B
MAXIMUM RATINGS (Note 1)
Symbol
Value
Unit
Power Switch (Pin 16)
Drain Voltage
Drain Current
VDS
IDS
700
1.0
V
A
Startup Input Voltage (Pin 1, Note 2)
Vin
500
V
Power Supply Voltage (Pin 3)
VCC
40
V
Input Voltage Range
Voltage Feedback Input (Pin 10)
Compensation (Pin 9)
Overvoltage Protection Input (Pin 11)
RT (Pin 6)
CT (Pin 7)
VIR
−1.0 to Vreg
V
Rating
°C/W
Thermal Characteristics
P Suffix, Dual−In−Line Case 648E
Thermal Resistance, Junction−to−Air
Thermal Resistance, Junction−to−Case
DW Suffix, Surface Mount Case 751G
Thermal Resistance, Junction−to−Air
Thermal Resistance, Junction−to−Case
RqJA
RqJC
80
15
RqJA
RqJC
95
15
Operating Junction Temperature
TJ
−25 to +150
°C
Storage Temperature
Tstg
−55 to +150
°C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. This device series contains ESD protection and exceeds the following tests:
Human Body Model 2000 V per MIL−STD−883, Method 3015.
Machine Model Method 200 V.
2. Maximum power dissipation limits must be observed.
Thigh = +125°C
3. Tested junction temperature range for the MC33363B: Tlow = −25°C
ELECTRICAL CHARACTERISTICS (VCC = 20 V, RT = 10 k, CT = 390 pF, CPin 8 = 1.0 mF, for typical values TJ = 25°C,
for min/max values TJ is the operating junction temperature range that applies (Note 3), unless otherwise noted.)
Characteristic
Symbol
Min
Typ
Max
Unit
REGULATOR (Pin 8)
Output Voltage (IO = 0 mA, TJ = 25°C)
Vreg
5.5
6.5
7.5
V
Line Regulation (VCC = 20 V to 40 V)
Regline
−
30
500
mV
Load Regulation (IO = 0 mA to 10 mA)
Regload
−
44
200
mV
Vreg
5.3
−
8.0
V
Total Output Variation over Line, Load, and Temperature
OSCILLATOR (Pin 7)
Frequency
CT = 390 pF
TJ = 25°C (VCC = 20 V)
TJ = Tlow to Thigh (VCC = 20 V to 40 V)
CT = 2.0 nF
TJ = 25°C (VCC = 20 V)
TJ = Tlow to Thigh (VCC = 20 V to 40 V)
fOSC
Frequency Change with Voltage (VCC = 20 V to 40 V)
kHz
260
255
285
−
310
315
60
59
67.5
−
75
76
DfOSC/DV
−
0.1
2.0
kHz
ERROR AMPLIFIER (Pins 9, 10)
Voltage Feedback Input Threshold
VFB
2.52
2.6
2.68
V
Line Regulation (VCC = 20 V to 40 V, TJ = 25°C)
Regline
−
0.6
5.0
mV
Input Bias Current (VFB = 2.6 V, TJ = 0 − 125°C)
IIB
−
20
500
nA
Open Loop Voltage Gain (TJ = 25°C)
AVOL
70
82
94
dB
Gain Bandwidth Product (f = 100 kHz, TJ = 25°C)
GBW
0.85
1.0
1.15
MHz
Output Voltage Swing
High State (ISource = 100 mA, VFB < 2.0 V)
Low State (ISink = 100 mA, VFB > 3.0 V)
VOH
VOL
4.0
−
5.3
0.2
−
0.35
V
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2
MC33363B
ELECTRICAL CHARACTERISTICS (VCC = 20 V, RT = 10 k, CT = 390 pF, CPin 8 = 1.0 mF, for typical values TJ = 25°C,
for min/max values TJ is the operating junction temperature range that applies (Note 4), unless otherwise noted.)
Characteristic
Symbol
Min
Typ
Max
Unit
Input Threshold Voltage
Vth
2.47
2.6
2.73
V
Input Bias Current (Vin = 2.6 V, TJ = −25 − 125°C)
IIB
−
100
500
nA
DC(max)
DC(min)
48
−
50
0
52
0
−
−
15
−
17
39
−
−
0.25
−
1.0
50
OVERVOLTAGE DETECTION (Pin 11)
PWM COMPARATOR (Pins 7, 9)
%
Duty Cycle
Maximum (VFB = 0 V)
Minimum (VFB = 2.7 V)
POWER SWITCH (Pin 16)
Drain−Source On−State Resistance (ID = 200 mA)
TJ = 25°C
TJ = Tlow to Thigh
W
RDS(on)
Drain−Source Off−State Leakage Current (VDS = 650 V)
TJ = 25°C
TJ = Tlow to Thigh
mA
ID(off)
Rise Time
tr
−
50
−
ns
Fall Time
tf
−
50
−
ns
Ilim
0.5
0.72
0.9
A
2.0
2.0
5.0
5.0
8.0
8.0
−
40
200
mA
Vth(on)
11
15.2
18
V
VCC(min)
7.5
9.5
11.5
V
−
−
0.25
3.2
0.5
5.0
−
−
135
30
−
−
OVERCURRENT COMPARATOR (Pin 16)
Current Limit Threshold (RT = 10 k)
STARTUP CONTROL (Pin 1)
Peak Startup Current (Vin = 50 V) (TJ = −25 − 100°C)
VCC = 0 V
VCC = (Vth(on) − 0.2 V)
Istart
Off−State Leakage Current (Vin = 50 V, VCC = 20 V)
ID(off)
mA
UNDERVOLTAGE LOCKOUT (Pin 3)
Startup Threshold (VCC Increasing)
Minimum Operating Voltage After Turn−On
TOTAL DEVICE (Pin 3)
Power Supply Current
Startup (VCC = 10 V, Pin 1 Open)
Operating
ICC
mA
THERMAL SHUTDOWN
Tsd
TH
Shutdown (Junction Temperature Increasing)
Hysteresis (Junction Temperature Decreasing)
4. Tested junction temperature range for the MC33363B: Tlow = −25°C
Thigh = +125°C
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3
°C
CT = 100 pF
VCC = 20 V
TA = 25°C
500 k C = 200 pF
T
200 k CT = 500 pF
100 k CT = 1.0 nF
50 k
20 k
CT = 2.0 nF
CT = 5.0 nF
CT = 10 nF
10
15
20
30
70
50
0.2
0.15
0.1
7.0
Inductor supply voltage and inductance value are
adjusted so that Ipk turn−off is achieved at 5.0 ms.
10
15
20
30
40
50
Figure 2. Oscillator Frequency
versus Timing Resistor
Figure 3. Power Switch Peak Drain Current
versus Timing Resistor
VCC = 20 V
TA = 25°C
0.5
0.3
0.2
0.15
0.1
10
15
20
30
70
50
70
60
50
40
RC/RT Ratio
Charge Resistor
Pin 7 to Vreg
30
1.0
2.0
3.0
5.0
7.0
TIMING RESISTOR RATIO
Figure 4. Oscillator Charge/Discharge
Current versus Timing Resistor
Figure 5. Maximum Output Duty Cycle
versus Timing Resistor Ratio
100
VCC = 20 V
VO = 1.0 to 4.0 V
RL = 5.0 MW
CL = 2.0 pF
TA = 25°C
80
Gain
60
0
30
60
Phase
40
90
20
120
0
150
100
1.0 k
10 k
100 k
180
10 M
1.0 M
10
0
Source Saturation
(Load to Ground)
−1.0
Vref
−2.0
2.0
Sink Saturation
(Load to Vref)
VCC = 20 V
TA = 25°C
1.0
GND
0
0
f, FREQUENCY (Hz)
0.2
0.4
0.6
0.8
IO, OUTPUT LOAD CURRENT (mA)
Figure 6. Error Amp Open Loop Gain and
Phase versus Frequency
Figure 7. Error Amp Output Saturation
Voltage versus Load Current
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4
70
VCC = 20 V
CT = 2.0 nF
TA = 25°C
RD/RT Ratio
Discharge Resistor
Pin 7 to GND
RT, TIMING RESISTOR (kW)
θ, EXCESS PHASE (DEGREES)
I chg /I dscg , OSCILLATOR
CHARGE/DISCHARGE CURRENT (mA)
0.3
RT, TIMING RESISTOR (kW)
0.08
7.0
A VOL, OPEN LOOP VOLTAGE GAIN (dB)
0.4
RT, TIMING RESISTOR (kW)
0.8
−20
10
VCC = 20 V
CT = 1.0 mF
TA = 25°C
0.6
Dmax, MAXIMUM OUTPUT DUTY CYCLE (%)
10 k
7.0
1.0
0.8
Vsat , OUTPUT SATURATION VOLTAGE (V)
f OSC , OSCILLATOR FREQUENCY (Hz)
1.0 M
I PK, POWER SWITCH PEAK DRAIN CURRENT (A
MC33363B
1.0
MC33363B
VCC = 20 V
AV = −1.0
CL = 10 pF
TA = 25°C
1.75 V
1.75 V
0.50 V
1.0 ms/DIV
1.0 ms/DIV
Figure 8. Error Amplifier Small Signal
Transient Response
Figure 9. Error Amplifier Large Signal
Transient Response
0
6
−20
I pk , PEAK STARTUP CURRENT (mA)
VCC = 20 V
RT = 10 k
CPin 8 = 1.0 mF
TA = 25°C
−40
−60
−80
0
32
4.0
8.0
12
16
4
3
2
1
0
2.0
4.0
6.0
8.0
10
Ireg, REGULATOR SOURCE CURRENT (mA)
VCC, POWER SUPPLY VOLTAGE (V)
Figure 10. Regulator Output Voltage
Change versus Source Current
Figure 11. Peak Startup Current
versus Power Supply Voltage
12
160
ID = 200 mA
24
VCC = 20 V
TA = 25°C
120
16
8.0
Pulse tested at 5.0 ms with < 1.0% duty cycle
so that TJ is as close to TA as possible.
0
−50
VPin 1 = 50 V
TA = 25°C
5
0
20
COSS, DRAIN−SOURCE CAPACITANCE (pF)
Δ V reg, REGULATOR VOLTAGE CHANGE (mV)
1.70 V
R DS(on), DRAIN−SOURCE ON−RESISTANCE (Ω )
0.5 V/DIV
3.00 V
20 mV/DIV
1.80 V
VCC = 20 V
AV = −1.0
CL = 10 pF
TA = 25°C
−25
0
25
50
75
100
125
150
80
40
0
1.0
COSS measured at 1.0 MHz with 50 mVpp.
10
100
TA, AMBIENT TEMPERATURE (°C)
VDS, DRAIN−SOURCE VOLTAGE (V)
Figure 12. Power Switch Drain−Source
On−Resistance versus Temperature
Figure 13. Power Switch
Drain−Source Capacitance versus Voltage
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5
1000
MC33363B
3.2
100
RT = 10 k
Pin 1 = Open
Pin 4, 5, 10, 11,
12, 13 = GND
TA = 25°C
0.8
0
10
20
30
1.0
0.01
40
0.1
1.0
10
100
t, TIME (s)
Figure 14. Supply Current versus Supply Voltage
Figure 15. DW and P Suffix Transient
Thermal Resistance
90
2.4
ÎÎÎÎÎ
ÎÎÎÎÎ
80
Printed circuit board heatsink example
70
2.0 oz
Copper
L
60
L
3.0 mm
Graphs represent symmetrical layout
50
2.0
1.6
1.2
0.8
RqJA
0.4
40
10
20
30
40
100
R θ JA, THERMAL RESISTANCE
JUNCTION−TO−AIR (°C/W)
2.8
PD(max) for TA = 50°C
0
10
VCC, SUPPLY VOLTAGE (V)
100
30
L = 12.7 mm of 2.0 oz.
copper. Refer to Figures
16 and 17.
0
50
ÎÎÎÎÎ
ÎÎÎÎÎ
Printed circuit board heatsink example
80
L
RqJA
60
2.0 oz
Copper
L
3.0 mm
Graphs represent symmetrical layout
40
4.0
3.0
2.0
PD(max) for TA = 70°C
20
0
5.0
0
L, LENGTH OF COPPER (mm)
10
20
1.0
30
40
0
50
P D , MAXIMUM POWER DISSIPATION (W)
1.6
0
Rθ JA , THERMAL RESISTANCE
JUNCTION−TO−AIR ( °C/W)
Rθ JA , THERMAL RESISTANCE
JUNCTION−TO−AIR (°C/W)
CT = 2.0 nF
2.4
PD, MAXIMUM POWER DISSIPATION (W)
I CC, SUPPLY CURRENT (mA)
CT = 390 pF
L, LENGTH OF COPPER (mm)
Figure 16. DW Suffix (SOP−16L) Thermal Resistance and
Maximum Power Dissipation versus P.C.B. Copper Length
Figure 17. P Suffix (DIP−16) Thermal Resistance and
Maximum Power Dissipation versus P.C.B. Copper Length
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6
MC33363B
PIN FUNCTION DESCRIPTION
Pin
Function
Description
1
Startup Input
This pin connects directly to the rectified ac line voltage source. Internally Pin 1 is tied to the drain of
a high voltage startup MOSFET. During startup, the MOSFET supplies internal bias, and charges an
external capacitor that connects from the VCC pin to ground.
2
−
3
VCC
This is the positive supply voltage input. During startup, power is supplied to this input from Pin 1.
When VCC reaches the UVLO upper threshold, the startup MOSFET turns off and power is supplied
from an auxiliary transformer winding.
4, 5, 12, 13
Ground
These pins are the control circuit grounds. They are part of the IC lead frame and provide a thermal
path from the die to the printed circuit board.
6
RT
Resistor RT connects from this pin to ground. The value selected will program the Current Limit
Comparator threshold and affect the Oscillator frequency.
7
CT
Capacitor CT connects from this pin to ground. The value selected, in conjunction with resistor RT,
programs the Oscillator frequency.
8
Regulator Output
This 6.5 V output is available for biasing external circuitry. It requires an external bypass capacitor of
at least 1.0 mF for stability.
9
Compensation
This pin is the Error Amplifier output and is made available for loop compensation. It can be used as
an input to directly control the PWM Comparator.
10
Voltage
Feedback Input
This is the inverting input of the Error Amplifier. It has a 2.6 V threshold and normally connects
through a resistor divider to the converter output, or to a voltage that represents the converter output.
11
Overvoltage
Protection Input
This input provides runaway output voltage protection due to an external component or connection
failure in the control loop feedback signal path. It has a 2.6 V threshold and normally connects
through a resistor divider to the converter output, or to a voltage that represents the converter output.
14, 15
−
16
Power Switch
Drain
This pin has been omitted for increased spacing between the rectified ac line voltage on Pin 1 and
the VCC potential on Pin 3.
These pins have been omitted for increased spacing between the high voltages present on the
Power Switch Drain, and the ground potential on Pins 12 and 13.
This pin is designed to directly drive the converter transformer and is capable of switching a
maximum of 700 V and 1.0 A.
2.6 V
Capacitor CT
0.6 V
Compensation
Oscillator Output
PWM
Comparator
Output
PWM Latch
Q Output
Current Limit
Propagation
Delay
Power Switch
Gate Drive
Current
Limit
Threshold
Leading Edge
Blanking Input
(Power Switch
Drain Current)
Normal PWM Operating Range
Figure 18. Timing Diagram of Normal Operation
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7
Output Overload
MC33363B
AC Input
Startup Input
Startup
Control
Current
Mirror
Regulator Output
6.5 V
8
Band Gap
Regulator
I
VCC
2.25 I
CT
Overvoltage
Protection
Input
14.5 V/
9.5 V
4I
11
OVP
2.6 V
Oscillator
7
DC
Output
3
UVLO
6
RT
1
16
PWM Latch
Power Switch
Drain
Driver
S
Q
R
PWM
Comparator
Leading Edge
Blanking
8.1
Thermal
Shutdown
Current Limit
Comparator
Compensation
405
270 m A
GND
9
Error
Amplifier
2.6 V
10
Voltage
Feedback Input
4, 5, 12, 13
Figure 19. Representative Block Diagram
15.2 V
VCC
9.5 V
Drain Current
Figure 20. Timing Diagram of Short−Circuit Condition
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8
MC33363B
OPERATING DESCRIPTION
Introduction
The MC33363B represents a new higher level of
integration by providing all the active high voltage power,
control, and protection circuitry required for
implementation of a flyback or forward converter on a single
monolithic chip. This device is designed for direct operation
from a rectified 240 Vac line source and requires a minimum
number of external components to implement a complete
converter. A description of each of the functional blocks is
given below, and the representative block and timing
diagrams are shown in Figures 19, 18 and 20.
The formula for the charge/discharge current along with
the oscillator frequency are given below. The frequency
formula is a first order approximation and is accurate for CT
values greater than 500 pF. For smaller values of CT, refer to
Figure 2. Note that resistor RT also programs the Current
Limit Comparator threshold.
I
1.0
2.25 I
I
RC
Current
Limit
Reference
6
RT
4I
RD
CT
7
Oscillator
chgńdscg
4C
T
Current Limit Comparator and Power Switch
The MC33363B uses cycle−by−cycle current limiting as a
means of protecting the output switch transistor from
overstress. Each on−cycle is treated as a separate situation.
Current limiting is implemented by monitoring the output
switch current buildup during conduction, and upon sensing
an overcurrent condition, immediately turning off the switch
for the duration of the oscillator ramp−up period.
The Power Switch is constructed as a SENSEFET allowing
a virtually lossless method of monitoring the drain current. It
consists of a total of 1462 cells, of which 36 are connected to
a 8.1 W ground−referenced sense resistor. The Current Sense
Comparator detects if the voltage across the sense resistor
exceeds the reference level that is present at the inverting
input. If exceeded, the comparator quickly resets the PWM
Latch, thus protecting the Power Switch. The current limit
reference level is generated by the 2.25 I output of the Current
Mirror. This current causes a reference voltage to appear
across the 405 W resistor. This voltage level, as well as the
Oscillator charge/discharge current are both set by resistor RT.
Therefore when selecting the values for RT and CT, RT must
be chosen first to set the Power Switch peak drain current,
while CT is chosen second to set the desired Oscillator
frequency. A graph of the Power Switch peak drain current
versus RT is shown in Figure 3 with the related formula
below.
Current
Mirror
8
f [
PWM Comparator and Latch
The pulse width modulator consists of a comparator with
the oscillator ramp voltage applied to the non−inverting input,
while the error amplifier output is applied into the inverting
input. The Oscillator applies a set pulse to the PWM Latch
while CT is discharging, and upon reaching the valley voltage,
Power Switch conduction is initiated. When CT charges to a
voltage that exceeds the error amplifier output, the PWM
Latch is reset, thus terminating Power Switch conduction for
the duration of the oscillator ramp−up period. This
PWM Comparator/Latch combination prevents multiple
output pulses during a given oscillator clock cycle. The
timing diagram shown in Figure 18 illustrates the Power
Switch duty cycle behavior versus the Compensation voltage.
Oscillator and Current Mirror
The oscillator frequency is controlled by the values
selected for the timing components RT and CT. Resistor RT
programs the oscillator charge/discharge current via the
Current Mirror 4 I output, Figure 4. Capacitor CT is charged
and discharged by an equal magnitude internal current
source and sink. This generates a symmetrical 50 percent
duty cycle waveform at Pin 7, with a peak and valley
threshold of 2.6 V and 0.6 V respectively. During the
discharge of CT, the oscillator generates an internal blanking
pulse that holds the inverting input of the AND gate Driver
high. This causes the Power Switch gate drive to be held in
a low state, thus producing a well controlled amount of
output deadtime. The amount of deadtime is relatively
constant with respect to the oscillator frequency when
operating below 1.0 MHz. The maximum Power Switch
duty cycle at Pin 16 can be modified from the internal 50%
limit by providing an additional charge or discharge current
path to CT, Figure 21. In order to increase the maximum duty
cycle, a discharge current resistor RD is connected from
Pin 7 to ground. To decrease the maximum duty cycle, a
charge current resistor RC is connected from Pin 7 to the
Regulator Output. Figure 5 shows an obtainable range of
maximum output duty cycle versus the ratio of either RC or
RD with respect to RT.
Regulator Output
I
5.4
+ R
chgńdscg
T
Blanking
Pulse
PWM
Comparator
ǒ Ǔ
R
I
Figure 21. Maximum Duty Cycle Modification
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9
pk
+ 8.8
T − 1.077
1000
MC33363B
associated power dissipation, commonly used in most
off−line converters that utilize a UC3842 type of controller.
Rectified ac line voltage is applied to the Startup Input, Pin 1.
This causes the MOSFET to enhance and supply internal bias
as well as charge current to the VCC bypass capacitor that
connects from Pin 3 to ground. When VCC reaches the UVLO
upper threshold of 15.2 V, the IC commences operation and
the startup MOSFET is turned off. Operating bias is now
derived from the auxiliary transformer winding, and all of the
device power is efficiently converted down from the rectified
ac line.
The startup MOSFET will provide a steady current of
1.7 mA, Figure 11, as VCC increases or shorted to ground.
The startup MOSFET is rated at a maximum of 400 V with
VCC shorted to ground, and 500 V when charging a VCC
capacitor of 1000 mF or less.
The Power Switch is designed to directly drive the converter
transformer and is capable of switching a maximum of 700 V
and 1.0 A. Proper device voltage snubbing and heatsinking
are required for reliable operation.
A Leading Edge Blanking circuit was placed in the current
sensing signal path. This circuit prevents a premature reset of
the PWM Latch. The premature reset is generated each time
the Power Switch is driven into conduction. It appears as a
narrow voltage spike across the current sense resistor, and is
due to the MOSFET gate to source capacitance, transformer
interwinding capacitance, and output rectifier recovery time.
The Leading Edge Blanking circuit has a dynamic behavior
in that it masks the current signal until the Power Switch
turn−on transition is completed. The current limit
propagation delay time is typically 262 ns. This time is
measured from when an overcurrent appears at the Power
Switch drain, to the beginning of turn−off.
Output Short−Circuit Condition
When the output is short−circuited, the VCC is powered by
the internal startup circuit instead of the VCC auxiliary
winding. The internal startup circuit turns on and charges up
VCC voltage when VCC reaches its UVLO lower threshold of
9.5V. It turns off and VCC voltage drops when VCC reaches
its UVLO upper threshold of 15.2V. The device only delivers
drain current for the time when VCC goes from 15.2V to 9.5V.
No drain current is delivered when VCC goes from 9.5V to
15.2V. As a result, some of the switching cycle is missed as
shown in Figure 20. The drain current limit is limited by the
cycle−by−cycle current limit.
Error Amplifier
An fully compensated Error Amplifier with access to the
inverting input and output is provided for primary side
voltage sensing, Figure 19. It features a typical dc voltage
gain of 82 dB, and a unity gain bandwidth of 1.0 MHz with
78 degrees of phase margin, Figure 6. The noninverting input
is internally biased at 2.6 V ±3.1% and is not pinned out. The
Error Amplifier output is pinned out for external loop
compensation and as a means for directly driving the PWM
Comparator. The output was designed with a limited sink
current capability of 270 mA, allowing it to be easily
overridden with a pullup resistor. This is desirable in
applications that require secondary side voltage sensing.
Regulator
A low current 6.5 V regulated output is available for
biasing the Error Amplifier and any additional control system
circuitry. It is capable of up to 10 mA and has short−circuit
protection. This output requires an external bypass capacitor
of at least 1.0 mF for stability.
Overvoltage Protection
An Overvoltage Protection Comparator is included to
eliminate the possibility of runaway output voltage. This
condition can occur if the control loop feedback signal path
is broken due to an external component or connection failure.
The comparator is normally used to monitor the primary side
VCC voltage. When the 2.6 V threshold is exceeded, it will
immediately turn off the Power Switch, and protect the load
from a severe overvoltage condition. This input can also be
driven from external circuitry to inhibit converter operation.
Thermal Shutdown and Package
Internal thermal circuitry is provided to protect the Power
Switch in the event that the maximum junction temperature
is exceeded. When activated, typically at 135°C, the Latch is
forced into a ‘reset’ state, disabling the Power Switch. The
Latch is allowed to ‘set’ when the Power Switch temperature
falls below 105°C. This feature is provided to prevent
catastrophic failures from accidental device overheating. It is
not intended to be used as a substitute for proper heatsinking.
The MC33363B is contained in a heatsinkable plastic
dual−in−line package in which the die is mounted on a special
heat tab copper alloy lead frame. This tab consists of the four
center ground pins that are specifically designed to improve
thermal conduction from the die to the circuit board. Figures
16 and 17 show a simple and effective method of utilizing the
printed circuit board medium as a heat dissipater by soldering
these pins to an adequate area of copper foil. This permits the
use of standard layout and mounting practices while having
the ability to halve the junction to air thermal resistance. The
examples are for a symmetrical layout on a single−sided
board with two ounce per square foot of copper.
Undervoltage Lockout
An Undervoltage Lockout comparator has been
incorporated to guarantee that the integrated circuit has
sufficient voltage to be fully functional before the output
stage is enabled. The UVLO comparator monitors the VCC
voltage at Pin 3 and when it exceeds 14.5 V, the reset signal
is removed from the PWM Latch allowing operation of the
Power Switch. To prevent erratic switching as the threshold
is crossed, 5.0 V of hysteresis is provided.
Startup Control
An internal Startup Control circuit with a high voltage
enhancement mode MOSFET is included within the
MC33363B. This circuitry allows for increased converter
efficiency by eliminating the external startup resistor, and its
http://onsemi.com
10
MC33363B
PACKAGE DIMENSIONS
SO−16WB
DW SUFFIX
CASE 751N−01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
−A−
T
16
9
−B−
1
0.010 (0.25)
P
M
B
M
8
J
13X
D
0.010 (0.25)
M
T A
S
B
S
F
R X 45 _
C
−T−
S
K
9X
SEATING
PLANE
M
DIM
A
B
C
D
F
G
J
K
M
P
R
S
T
MILLIMETERS
MIN
MAX
10.15
10.45
7.40
7.60
2.35
2.65
0.35
0.49
0.50
0.90
1.27 BSC
0.25
0.32
0.10
0.25
0_
7_
10.05
10.55
0.25
0.75
2.54 BSC
3.81 BSC
INCHES
MIN
MAX
0.400
0.411
0.292
0.299
0.093
0.104
0.014
0.019
0.020
0.035
0.050 BSC
0.010
0.012
0.004
0.009
0_
7_
0.395
0.415
0.010
0.029
0.100 BSC
0.150 BSC
G
The product described herein (MC33363B), may be covered by one or more of the following U.S. patents: 4,553,084; 5,418,410; 5,477,175. There may be
other patents pending.
SENSEFET is a trademark of Semiconductor Components Industries, LLC (SCILLC)
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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MC33363B/D