ONSEMI NTHS4111P

NTHS4111P
Power MOSFET
−30 V, −6.1 A, Single P−Channel, ChipFETt
Features
•
•
•
•
•
Offers an Ultra Low RDS(on) Solution in the ChipFET Package
ChipFET Package 40% Smaller Footprint than TSOP−6
Low Profile (<1.1 mm) for Extremely Thin Environments
Standard Logic Level Gate Drive
Pb−Free Package is Available
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V(BR)DSS
33 mW @ −10 V
−30 V
−6.1 A
52 mW @ −4.5 V
Applications
•
•
•
•
ID Max
RDS(on) Typ
Notebook Computer Load Switch
Battery and Load Management Applications in Portable Equipment
Charge Control in Battery Chargers
Buck and Boost Converters
S
G
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
−30
V
Gate−to−Source Voltage
VGS
±20
V
ID
−4.4
A
Continuous Drain
Current (Note 1)
Steady
State
TA = 25°C
t ≤ 10 s
TA = 25°C
TA = 25°C
PD
1.3
TA = 25°C
ID
−3.3
Power Dissipation
(Note 1)
Steady
State
Continuous Drain
Current (Note 2)
t ≤ 10 s
Steady
State
Power Dissipation
(Note 2)
TA = 85°C
ChipFET
CASE 1206A
STYLE 1
8
−3.2
−6.1
W
2.5
TA = 85°C
TA = 25°C
D
P−Channel MOSFET
1
A
PIN
CONNECTIONS
−2.3
MARKING
DIAGRAM
0.7
W
D
8
1
D
1
8
IDM
−30
A
D
7
2
D
2
7
TJ,
TSTG
−55 to
150
°C
D
6
3
D
3
Source Current (Body Diode)
IS
−2.1
A
S
5
4
G
4
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
TL
260
°C
Pulsed Drain Current
tp = 10 ms
Operating Junction and Storage Temperature
THERMAL RESISTANCE RATINGS
Rating
Symbol
Max
Unit
Junction−to−Ambient – Steady State (Note 1)
RqJA
95
°C/W
Junction−to−Ambient – t ≤ 10 s (Note 1)
RqJA
50
Junction−to−Ambient – Steady State (Note 2)
RqJA
175
August, 2006 − Rev. 2
6
5
= Specific Device Code
= Date Code
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Package
Shipping†
NTHS4111PT1
ChipFET
3000/Tape & Reel
NTHS4111PT1G
ChipFET
(Pb−free)
3000/Tape & Reel
Device
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface−mounted on FR4 board using 1 in sq pad size
(Cu area = 1.127 in sq [1 oz] including traces).
2. Surface−mounted on FR4 board using the minimum recommended pad size
(Cu area = 0.045 in sq).
© Semiconductor Components Industries, LLC, 2006
TH
M
G
TH M G
G
PD
1
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Publication Order Number:
NTHS4111P/D
NTHS4111P
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = −250 mA
−30
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/TJ
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
IDSS
Gate−to−Source Leakage Current
V
−19
VGS = 0 V,
VDS = −24 V
mV/°C
TJ = 25°C
−1.0
TJ = 125°C
−100
IGSS
VDS = 0 V, VGS = ±20 V
VGS(TH)
VGS = VDS, ID = −250 mA
mA
±100
nA
−3.0
V
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage
Negative Threshold Temperature Coefficient
−1.0
VGS(TH)/TJ
Drain−to−Source On Resistance
Forward Transconductance
RDS(on)
gFS
−1.7
5.0
VGS = −10 V, ID = −4.4 A
mV/°C
33
45
VGS = −4.5 V, ID = −3.4 A
52
75
VDS = −15 V, ID = −4.4 A
7.7
mW
S
CHARGES, CAPACITANCES AND GATE RESISTANCE
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
Total Gate Charge
QG(TOT)
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
1500
pF
28
nC
9.0
18
ns
8.0
16
45
90
26
52
882
VGS = 0 V, f = 1.0 MHz,
VDS = −24 V
143
105
18.2
VGS = −10 V, VDD = −15 V,
ID = −4.4 A
2.95
4.25
SWITCHING CHARACTERISTICS, VGS = −10 V (Note 4)
Turn−On Delay Time
Rise Time
td(ON)
tr
Turn−Off Delay Time
Fall Time
VGS = −10 V, VDD = −15 V,
ID = −1.0 A, RG = 6.0 W
td(OFF)
tf
SWITCHING CHARACTERISTICS, VGS = −4.5 V (Note 4)
Turn−On Delay Time
Rise Time
td(ON)
tr
Turn−Off Delay Time
Fall Time
ns
11
14
VGS = −4.5 V, VDD = −15 V,
ID = −1.0 A, RG = 6.0 W
td(OFF)
32
tf
23
DRAIN − SOURCE DIODE CHARACTERISTICS
Characteristic
Symbol
Forward Diode Voltage
VSD
Reverse Recovery Time
tRR
Charge Time
Discharge Time
Reverse Recovery Charge
ta
tb
Test Condition
VGS = 0 V,
IS = −1.1 A
Typ
Max
Unit
TJ = 25°C
Min
−0.76
−1.2
V
TJ = 125°C
−0.60
54
ns
27
VGS = 0 V
dIS/dt = 100 A/ms, IS = −1.1 A
QRR
10
17
12
3. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
4. Switching characteristics are independent of operating junction temperatures.
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2
nC
NTHS4111P
VGS = −10 V to −5.0 V
12
−4.5 V
−3.6 V
−4.2 V
9.0
8.0
7.0
6.0
5.0
4.0
−4.0 V
−3.8 V
−ID, DRAIN CURRENT (AMPS)
12
11
10
−3.4 V
−3.2 V
−3.0 V
3.0
2.0
1.0
0
0
TJ = 25°C
0.5
1.0
1.5
2.0
2.5
3.0
3.5
9.0
8.0
TJ = 100°C
7.0
6.0
5.0
4.0
3.0
−55°C
25°C
2.0
1.0
1.5
2.0
2.5
3.0
3.5
4.5
4.0
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.25
ID = −4.4 A
TJ = 25°C
0.20
0.15
0.10
0.05
0
VDS = −15 V
11
10
0
1.0
4.0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
−ID, DRAIN CURRENT (AMPS)
TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted)
2
3
4
5
6
7
8
9
10
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
0.100
TJ = 25°C
0.075
VGS = −4.5 V
0.050
VGS = −10 V
0.025
0
1
4
5
6
7
8
9
10
11
12
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
100000
1.5
ID = −4.4 A
VGS = −10 V
VGS = 0 V
−IDSS, LEAKAGE (nA)
1.25
10000
1.00
0.75
0.5
−50
3
−ID, DRAIN CURRENT (AMPS)
Figure 3. RDS(on) vs. VGS
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
2
−25
0
25
50
75
100
125
150
1000
100
10
TJ = 150°C
TJ = 100°C
20
TJ, JUNCTION TEMPERATURE (°C)
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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3
30
NTHS4111P
TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted)
Ciss
20
15
25
30
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
C, CAPACITANCE (pF)
10
TJ = 25°C
8
VDS
10
QGS
4
0
ID = −4.4 A
TJ = 25°C
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Qg, TOTAL GATE CHARGE (nC)
Figure 8. Gate−to−Source and
Drain−to−Source Voltage vs. Total Charge
−IS, SOURCE CURRENT (AMPS)
10 ms
100 ms
1 ms
1.0
10 ms
VGS = −20 V
Single Pulse TC = 25°C
RDS(on) Limit
Thermal Limit
Package Limit
dc
1
10
VGS = 0 V
TJ = 25°C
1
0.1
0.4
100
150°C
100°C
0.5
0.6
25°C
0.7
−55°C
0.8
0.9
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
−VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 9. Maximum Rated Forward Biased
Safe Operating Area
Figure 10. Diode Forward Voltage vs. Current
−VGS(TH), GATE−TO−SOURCE THRESHOLD
VOLTAGE (NORMALIZED)
−ID, DRAIN CURRENT (AMPS)
10
10
0.01
0.1
QGD
2
Figure 7. Capacitance Variation
0.1
VGS
6
−GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
100
20
QT
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
1600
1500
1400 Crss
Ciss
1300
1200
1100
1000
900
800
700
600
500
400
Coss
Crss
300
200
100
VDS = 0 V VGS = 0 V
0
10
0
10
5
5
−VGS −VDS
1.5
1.4
ID = −250 mA
VGS = VDS
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
−50
−25
0
25
50
75
100
125
TJ, JUNCTION TEMPERATURE (°C)
Figure 11. VGS(TH) Variation with Temperature
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4
150
1.0
Rthja(t), EFFECTIVE TRANSIENT THERMAL RESPONSE
NTHS4111P
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
0.01
0.01
Single Pulse
0.001
1E−06
1E−05
1E−04
1E−03
1E−02
1E−01
t, TIME (s)
Figure 12. FET Thermal Response
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5
1E+00
1E+01
1E+02
1E+03
NTHS4111P
PACKAGE DIMENSIONS
ChipFETt
CASE 1206A−03
ISSUE G
D
8
7
q
6
L
5
HE
1
e1
5
6
7
8
4
3
2
1
E
2
3
e
4
b
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE.
4. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL
AND VERTICAL SHALL NOT EXCEED 0.08 MM.
5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS.
6. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD
SURFACE.
c
STYLE 1:
PIN 1. DRAIN
2. DRAIN
3. DRAIN
4. GATE
5. SOURCE
6. DRAIN
7. DRAIN
8. DRAIN
A
0.05 (0.002)
DIM
A
b
c
D
E
e
e1
L
HE
q
MILLIMETERS
NOM
MAX
1.05
1.10
0.30
0.35
0.15
0.20
3.05
3.10
1.65
1.70
0.65 BSC
0.55 BSC
0.28
0.35
0.42
1.80
1.90
2.00
5° NOM
MIN
1.00
0.25
0.10
2.95
1.55
INCHES
NOM
0.041
0.012
0.006
0.120
0.065
0.025 BSC
0.022 BSC
0.011
0.014
0.071
0.075
5° NOM
MIN
0.039
0.010
0.004
0.116
0.061
MAX
0.043
0.014
0.008
0.122
0.067
0.017
0.079
SOLDERING FOOTPRINT*
2.032
0.08
1.727
0.068
0.457
0.018
0.178
0.007
0.711
0.028
mm Ǔ
0.66
SCALE 20:1 ǒ
inches
0.026
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ChipFET is a trademark of Vishay Siliconix.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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6
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For additional information, please contact your local
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NTHS4111P/D