ONSEMI NTGS4111PT1

NTGS4111P
Power MOSFET
−30 V, −4.7 A, Single P−Channel, TSOP−6
Features
•
•
•
•
•
Leading −30 V Trench Process for Low RDS(on)
Low Profile Package Suitable for Portable Applications
Surface Mount TSOP−6 Package Saves Board Space
Improved Efficiency for Battery Applications
Pb−Free Package is Available
http://onsemi.com
V(BR)DSS
ID MAX
RDS(on) TYP
38 mW @ −10 V
−30 V
−4.7 A
68 mW @ −4.5 V
Applications
• Battery Management and Switching
• Load Switching
• Battery Protection
P−Channel
1 2 5 6
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Drain−to−Source Voltage
Gate−to−Source Voltage
Continuous Drain
Current (Note 1)
Steady TA = 25°C
State
TA = 85°C
t≤5s
Symbol
Value
Unit
VDSS
−30
V
VGS
±20
V
ID
−3.7
A
TA = 25°C
MARKING DIAGRAM &
PIN ASSIGNMENT
−4.7
Steady TA = 25°C
State
Continuous Drain
Current (Note 2)
Steady TA = 25°C
State
TA = 85°C
PD
ID
Power Dissipation
(Note 2)
TA = 25°C
PD
t≤5s
W
1.25
Drain Drain Source
6 5 4
2.0
tp = 10 ms
Operating Junction and Storage Temperature
Source Current (Body Diode)
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
−1.9
0.63
W
IDM
−15
A
TJ,
TSTG
−55 to
150
°C
IS
−1.7
A
TL
260
TSOP−6
CASE 318G
STYLE 1
TG
M
°C
Rating
Symbol
Max
Unit
Junction−to−Ambient – Steady State (Note 1)
RqJA
100
°C/W
Junction−to−Ambient – t ≤ 5 s (Note 1)
RqJA
62.5
Junction−to−Ambient – Steady State (Note 2)
RqJA
200
G
1 2 3
Drain Drain Gate
= Specific Device Code
= Date Code*
= Pb−Free Package
ORDERING INFORMATION
NTGS4111PT1
1
TG M G
G
(Note: Microdot may be in either location)
*Date Code orientation may vary depending
upon manufacturing location.
Device
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Surface−mounted on FR4 board using 1 in sq pad size
(Cu area = 1.127 in sq [1 oz] including traces).
2. Surface−mounted on FR4 board using the minimum recommended pad size
(Cu area = 0.006 in sq).
© Semiconductor Components Industries, LLC, 2006
1
A
−2.6
THERMAL RESISTANCE RATINGS
April, 2006 − Rev. 2
4
−2.7
Power Dissipation
(Note 1)
Pulsed Drain Current
3
NTGS4111PT1G
Package
TSOP−6
Shipping †
3000 / Tape & Reel
TSOP−6 3000 / Tape& Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Publication Order Number:
NTGS4111P/D
NTGS4111P
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Symbol
Test Condition
Min
Drain−to−Source Breakdown Voltage
V(BR)DSS
VGS = 0 V, ID = −250 mA
−30
Drain−to−Source Breakdown Voltage
Temperature Coefficient
V(BR)DSS/TJ
Characteristic
Typ
Max
Unit
OFF CHARACTERISTICS
Zero Gate Voltage Drain Current
IDSS
Gate−to−Source Leakage Current
V
−17
VGS = 0 V,
VDS = −24 V
mV/°C
TJ = 25°C
−1.0
TJ = 125°C
−100
IGSS
VDS = 0 V, VGS = ±20 V
VGS(TH)
VGS = VDS, ID = −250 mA
mA
±100
nA
−3.0
V
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage
Negative Threshold Temperature Coefficient
−1.0
VGS(TH)/TJ
Drain−to−Source On Resistance
Forward Transconductance
RDS(on)
gFS
5.0
VGS = −10 V, ID = −3.7 A
mV/°C
mW
38
60
VGS = −4.5 V, ID = −2.7 A
68
110
VDS = −10 V, ID = −3.7 A
6.0
S
750
pF
CHARGES, CAPACITANCES AND GATE RESISTANCE
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
VGS = 0 V, f = 1.0 MHz,
VDS = −15 V
140
CRSS
130
Total Gate Charge
QG(TOT)
15.25
Threshold Gate Charge
QG(TH)
Gate−to−Source Charge
QGS
Gate−to−Drain Charge
QGD
32
nC
ns
0.8
VGS = −10 V, VDD = −15 V,
ID = −3.7 A
2.6
3.4
SWITCHING CHARACTERISTICS, VGS = −10 V (Note 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
td(ON)
9.0
17
tr
9.0
18
38
85
22
45
11
20
15
28
28
56
22
50
Typ
Max
Unit
TJ = 25°C
−0.76
−1.2
V
TJ = 125°C
−0.60
60
ns
VGS = −10 V, VDD = −15 V,
ID = −1.0 A, RG = 6.0 W
td(OFF)
tf
SWITCHING CHARACTERISTICS, VGS = −4.5 V (Note 4)
Turn−On Delay Time
Rise Time
td(ON)
tr
Turn−Off Delay Time
Fall Time
VGS = −4.5 V, VDD = −15 V,
ID = −1.0 A, RG = 6.0 W
td(OFF)
tf
ns
DRAIN − SOURCE DIODE CHARACTERISTICS
Characteristic
Forward Diode Voltage
Reverse Recovery Time
Symbol
VDS
VGS = 0 V,
IS = −1.0 A
tRR
Charge Time
ta
Discharge Time
tb
Reverse Recovery Charge
Test Condition
Min
24
VGS = 0 V
dIS/dt = 100 A/ms, IS = −1.0 A
QRR
9.0
15
12
3. Pulse Test: pulse width v 300 ms, duty cycle v 2%.
4. Switching characteristics are independent of operating junction temperatures.
http://onsemi.com
2
nC
NTGS4111P
TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted)
−ID, DRAIN CURRENT (AMPS)
−4 V
−8 V
−6 V
8
7
−3.8 V
−5.5 V
−5 V
6
−3.6 V
5
4
3
−3.4 V
−3.2 V
2
1
0
−3 V
TJ = 25°C
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
12
−4.5 V −4.2 V
−10V
11
10
9
0.4
0.8
1.2
1.6
2
2.4
2.8
3.2
3.6
9
8
7
6
5
4
25°C
TJ = −55°C
1
1.5
2
2.5
3
3.5
4
4.5
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.2
0.1
0
3
4
5
6
7
8
9
10
−VGS, GATE VOLTAGE (VOLTS)
5
0.1
TJ = 25°C
VGS = −4.5 V
0.05
VGS = −10 V
0
2.0
3.0
4.0
−ID, DRAIN CURRENT (AMPS)
Figure 4. On−Resistance vs. Drain Current and
Gate Voltage
Figure 3. On−Resistance vs. Gate−to−Source
Voltage
1.5
100000
VGS = 0 V
ID = −3.7 A
VGS = −10 V
−IDSS, LEAKAGE CURRENT (nA)
RDS(on), DRAIN−TO−SOURCE
RESISTANCE (NORMALIZED)
100°C
3
2
1
0
4
TJ = 25°C
ID = −3.7 A
2
VDS ≥ −10 V
11
10
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
−ID, DRAIN CURRENT (AMPS)
12
TJ = 150°C
10000
1.0
0.5
−50
1000
TJ = 100°C
100
−25
0
25
50
75
100
125
150
TJ, JUNCTION TEMPERATURE (°C)
10
15
20
25
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
5
http://onsemi.com
3
30
NTGS4111P
TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted)
−VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
C, CAPACITANCE (pF)
12
TJ = 25°C
20
QT
10
Ciss
20
25
30
VDS
8
10
6
QGS
4
ID = −3.7 A
TJ = 25°C
0
0
1
2
0
3 4 5 6 7 8 9 10 11 12 13 14 15 16
Qg, TOTAL GATE CHARGE (nC)
Figure 8. Gate−to−Source Voltage vs. Total
Gate Charge
Figure 7. Capacitance Variation
10
10
100 ms
1 ms
1
VGS = −20 V
SINGLE PULSE
TC = 25°C
0.1
0.01
0.1
10 ms
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
dc
1
10
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
VGS = 0 V
−IS, SOURCE CURRENT (AMPS)
100
−I D, DRAIN CURRENT (AMPS)
QGD
2
−GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
TJ = 150°C
1
0.1
0.3
100
TJ = 100°C
TJ = 25°C
TJ = −55°C
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
−VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 9. Maximum Rated Forward Biased
Safe Operating Area
Rthja(t), EFFECTIVE TRANSIENT THERMAL RESPONSE
VGS
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
1400
Ciss
1300
1200 C
rss
1100
1000
900
800
700
600
500
400
300
Coss
200
100
VDS = 0 V VGS = 0 V
Crss
0
5
5
15
10
0
10
−VGS −VDS
Figure 10. Diode Forward Voltage vs. Current
1
D = 0.5
0.2
0.1
0.1
0.05
0.02
0.01
0.01
0.001
0.0001
1E−07
Single Pulse
1E−06
1E−05
1E−04
1E−03
1E−02
1E−01
t, TIME (s)
Figure 11. FET Thermal Response
http://onsemi.com
4
1E+00
1E+01
1E+02
1E+03
NTGS4111P
PACKAGE DIMENSIONS
TSOP−6
CASE 318G−02
ISSUE P
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS OF
BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
D
6
HE
1
5
4
2
3
E
b
DIM
A
A1
b
c
D
E
e
L
HE
q
e
q
c
A
0.05 (0.002)
L
A1
MIN
0.90
0.01
0.25
0.10
2.90
1.30
0.85
0.20
2.50
0°
MILLIMETERS
NOM
MAX
1.00
1.10
0.06
0.10
0.38
0.50
0.18
0.26
3.00
3.10
1.50
1.70
0.95
1.05
0.40
0.60
2.75
3.00
10°
−
MIN
0.035
0.001
0.010
0.004
0.114
0.051
0.034
0.008
0.099
0°
INCHES
NOM
0.039
0.002
0.014
0.007
0.118
0.059
0.037
0.016
0.108
−
MAX
0.043
0.004
0.020
0.010
0.122
0.067
0.041
0.024
0.118
10°
STYLE 1:
PIN 1. DRAIN
2. DRAIN
3. GATE
4. SOURCE
5. DRAIN
6. DRAIN
SOLDERING FOOTPRINT*
2.4
0.094
1.9
0.075
0.95
0.037
0.95
0.037
0.7
0.028
1.0
0.039
SCALE 10:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer
purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
Literature Distribution Center for ON Semiconductor
USA/Canada
P.O. Box 61312, Phoenix, Arizona 85082−1312 USA
Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center
2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051
Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada
Phone: 81−3−5773−3850
Email: [email protected]
http://onsemi.com
5
ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
For additional information, please contact your
local Sales Representative.
NTGS4111P/D