ONSEMI CS51311GD14

CS51311
Synchronous CPU
Buck Controller for 12 V
and 5.0 V Applications
The CS51311 is a synchronous dual NFET Buck Regulator
Controller. It is designed to power the core logic of the latest high
performance CPUs. It uses the V2™ control method to achieve the
fastest possible transient response and best overall regulation. It
incorporates many additional features required to ensure the proper
operation and protection of the CPU and Power system. The CS51311
provides the industry’s most highly integrated solution, minimizing
external component count, total solution size, and cost.
The CS51311 is specifically designed to power Intel’s Pentium® II
processor and includes the following features: 5−bit DAC with 1.2%
tolerance, Power Good output, overcurrent hiccup mode protection,
VCC monitor, soft start, adaptive voltage positioning, adaptive FET
non−overlap time, and remote sense. The CS51311 will operate over
an 8.4 V to 14 V range and is available in 14 lead narrow body surface
mount package.
Features
• Synchronous Switching Regulator Controller for CPU VCORE
• Dual N−Channel MOSFET Synchronous Buck Design
• V2 Control Topology
• 200 ns Transient Loop Response
• 5−Bit DAC with 1.2% Tolerance
• Hiccup Mode Overcurrent Protection
• 40 ns Gate Rise and Fall Times (3.3 nF Load)
• 65 ns Adaptive FET Non−Overlap Time
• Adaptive Voltage Positioning
• Power Good Output Monitors Regulator Output
• VCC Monitor Provides Undervoltage Lockout
• Enable Through Use of the COMP Pin
http://onsemi.com
14
1
MARKING DIAGRAM
14
CS51311
AWLYWW
1
A
WL, L
YY, Y
WW, W
July, 2006 − Rev. 3
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
PIN CONNECTIONS
VID0
VID1
VID2
VID3
VID4
VFB
VOUT
1
14
COMP
COFF
PWRGD
GATE(L)
GND
GATE(H)
VCC
ORDERING INFORMATION
Device
© Semiconductor Components Industries, LLC, 2006
SO−14
D SUFFIX
CASE 751A
Package
Shipping
CS51311GD14
SO−14
55 Units/Rail
CS51311GDR14
SO−14
2500 Tape & Reel
Publication Order Number:
CS51311/D
CS51311
+5.0 V
+12 V
1.0 μF
1200 μF/10 V × 3
680 pF
10 k
0.01 μF
COFF
0.1 μF
100 Ω
VCC
FS70VSJ−03
COMP
GATE(H)
VID0
GATE(L)
VID1
1.2 μH
3.3 mΩ
FS70VSJ−03
1200 μF/10 V × 5
CS51311
VID2
VFB
VID3
VOUT
VID4
GND
VCC(CORE)
2.0 V @ 19 A
510 Ω
0.1 μF
PWRGD
510 Ω
PWRGD
Figure 1. Application Diagram
ABSOLUTE MAXIMUM RATINGS*
Rating
Operating Junction Temperature, TJ
Lead Temperature Soldering:
Reflow: (SMD styles only) (Note 1)
Storage Temperature Range, TS
ESD Susceptibility
1. 60 second maximum above 183°C.
*The maximum package power dissipation must be observed.
Value
Unit
150
°C
230 peak
°C
−65 to +150
°C
2.0
kV
ABSOLUTE MAXIMUM RATINGS
Pin Name
Pin Symbol
VMAX
VMIN
ISOURCE
ISINK
IC Power Input
VCC
16 V
−0.3 V
N/A
1.5 A Peak, 200 mA DC
Compensation Pin
COMP
6.0 V
−0.3 V
1.0 mA
5.0 mA
Voltage Feedback Input,
Output Voltage Sense Pin,
Voltage ID DAC Inputs
VFB, VOUT, VID0−4
6.0 V
−0.3 V
1.0 mA
1.0 mA
Off−Time Pin
COFF
6.0 V
−0.3 V
1.0 mA
50 mA
High−Side, Low−Side FET Drivers
GATE(H), GATE(L)
16 V
−0.3 V DC
1.5 A Peak, 200 mA DC
1.5 A Peak, 200 mA DC
Power Good Output
PWRGD
6.0 V
−0.3 V
1.0 mA
30 mA
Ground
GND
0V
0V
1.5 A Peak, 200 mA DC
N/A
http://onsemi.com
2
CS51311
ELECTRICAL CHARACTERISTICS (0°C < TA < 70°C; 0°C < TJ < 125°C; 9.0 V < VCC < 14 V;
2.0 V DAC Code (VID4 = VID3 = VID2 = VID1 = 0, VID0 = 1.0) CGATE(H) = CGATE(L) = 3.3 nF, COFF = 390 pF; unless otherwise specified.)
Characteristic
Test Conditions
Voltage Identification DAC
Measure VFB = VCOMP, VCC = 12 V. Note 2
755C 3 TJ 3 1255C
255C 3 TJ 3 755C
VID4
VID3
VID2
VID1
VID0
Min
Typ
Max
±Tol
Min
Typ
Max
±Tol
Unit
1
0
0
0
0
3.483
3.525
3.567
1.2%
3.455
3.525
3.596
2.0%
V
1
0
0
0
1
3.384
3.425
3.466
1.2%
3.357
3.425
3.494
2.0%
V
1
0
0
1
0
3.285
3.325
3.365
1.2%
3.259
3.325
3.392
2.0%
V
1
0
0
1
1
3.186
3.225
3.264
1.2%
3.161
3.225
3.290
2.0%
V
1
0
1
0
0
3.087
3.125
3.163
1.2%
3.063
3.125
3.188
2.0%
V
1
0
1
0
1
2.989
3.025
3.061
1.2%
2.965
3.025
3.086
2.0%
V
1
0
1
1
0
2.890
2.925
2.960
1.2%
2.875
2.925
2.975
1.7%
V
1
0
1
1
1
2.791
2.825
2.859
1.2%
2.777
2.825
2.873
1.7%
V
1
1
0
0
0
2.692
2.725
2.758
1.2%
2.679
2.725
2.771
1.7%
V
1
1
0
0
1
2.594
2.625
2.657
1.2%
2.580
2.625
2.670
1.7%
V
1
1
0
1
0
2.495
2.525
2.555
1.2%
2.482
2.525
2.568
1.7%
V
1
1
0
1
1
2.396
2.425
2.454
1.2%
2.389
2.425
2.461
1.5%
V
1
1
1
0
0
2.297
2.325
2.353
1.2%
2.290
2.325
2.360
1.5%
V
1
1
1
0
1
2.198
2.225
2.252
1.2%
2.192
2.225
2.258
1.5%
V
1
1
1
1
0
2.099
2.125
2.151
1.2%
2.093
2.125
2.157
1.5%
V
0
0
0
0
0
2.050
2.075
2.100
1.2%
2.044
2.075
2.106
1.5%
V
0
0
0
0
1
2.001
2.025
2.049
1.2%
1.995
2.025
2.055
1.5%
V
0
0
0
1
0
1.953
1.975
1.997
1.1%
1.945
1.975
2.005
1.5%
V
0
0
0
1
1
1.904
1.925
1.946
1.1%
1.896
1.925
1.954
1.5%
V
0
0
1
0
0
1.854
1.875
1.896
1.1%
1.847
1.875
1.903
1.5%
V
0
0
1
0
1
1.805
1.825
1.845
1.1%
1.798
1.825
1.852
1.5%
V
0
0
1
1
0
1.755
1.775
1.795
1.1%
1.748
1.775
1.802
1.5%
V
0
0
1
1
1
1.706
1.725
1.744
1.1%
1.699
1.725
1.751
1.5%
V
0
1
0
0
0
1.656
1.675
1.694
1.1%
1.650
1.675
1.700
1.5%
V
0
1
0
0
1
1.607
1.625
1.643
1.1%
1.601
1.625
1.649
1.5%
V
0
1
0
1
0
1.558
1.575
1.593
1.1%
1.551
1.575
1.599
1.5%
V
0
1
0
1
1
1.508
1.525
1.542
1.1%
1.502
1.525
1.548
1.5%
V
0
1
1
0
0
1.459
1.475
1.491
1.1%
1.453
1.475
1.497
1.5%
V
0
1
1
0
1
1.409
1.425
1.441
1.1%
1.404
1.425
1.446
1.5%
V
0
1
1
1
0
1.360
1.375
1.390
1.1%
1.354
1.375
1.396
1.5%
V
0
1
1
1
1
1.310
1.325
1.340
1.1%
1.305
1.325
1.345
1.5%
V
1
1
1
1
1
1.225
1.250
1.275
2.0%
1.225
1.250
1.275
2.0%
V
2. The IC power dissipation in a typical application with VCC = 12 V, switching frequency fSW = 250 kHz, 50 nc MOSFETs and RθJA = 115°C/W
yields an operating junction temperature rise of approximately 52°C, and a junction temperature of 77°C with an ambient temperature
of 25°C.
http://onsemi.com
3
CS51311
ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < 70°C; 0°C < TJ < 125°C; 9.0 V < VCC < 14 V;
2.0 V DAC Code (VID4 = VID3 = VID2 = VID1 = 0, VID0 = 1.0) CGATE(H) = CGATE(L) = 3.3 nF, COFF = 390 pF; unless otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
−
0.01
−
%/V
Voltage Identification DAC (continued)
Line Regulation
9.0 V ≤ VCC ≤ 14 V
Input Threshold
VID4, VID3, VID2, VID1, VID0
1.0
1.25
2.4
V
Input Pull−Up Resistance
VID4, VID3, VID2, VID1, VID0
25
50
100
kΩ
5.48
5.65
5.82
V
−7.0
0.1
7.0
μA
Pull−Up Voltage
−
Error Amplifier
VFB Bias Current
0.2 V ≤ VFB ≤ 3.5 V
COMP Source Current
VCOMP = 1.2 V to 3.6 V, VFB = 1.9 V
15
30
60
μA
COMP Sink Current
VCOMP = 1.2 V, VFB = 2.1 V
30
60
120
μA
Open Loop Gain
CCOMP = 0.1 μF
−
80
−
dB
Unity Gain Bandwidth
CCOMP = 0.1 μF
−
50
−
kHz
PSRR @ 1.0 kHz
CCOMP = 0.1 μF
−
70
−
dB
Transconductance
−
−
32
−
mmho
Output Impedance
−
−
0.5
−
MΩ
GATE(H) and GATE(L)
High Voltage at 100 mA
Measure VCC − GATE(L)/(H)
−
1.2
2.1
V
Low Voltage at 100 mA
Measure GATE(L)/(H)
−
1.0
1.5
V
Rise Time
1.6 V < GATE(H)/(L) < (VCC − 2.5 V)
−
40
80
ns
Fall Time
(VCC − 2.5 V) > GATE(L)/(H) > 1.6 V
−
40
80
ns
GATE(H) to GATE(L) Delay
GATE(H) < 2.0 V, GATE(L) > 2.0 V, VCC = 12 V
30
65
110
ns
GATE(L) to GATE(H) Delay
GATE(L) < 2.0 V, GATE(H) > 2.0 V, VCC = 12 V
30
65
110
ns
GATE Pull−Down
Resistance to GND. Note 3
20
50
115
kΩ
0 V ≤ VOUT ≤ 3.5 V
77
86
101
mV
0.2
0.25
0.3
V
Overcurrent Protection
OVC Comparator Offset Voltage
Discharge Threshold Voltage
−
VOUT Bias Current
0.2 V ≤ VOUT ≤ 3.5 V
−7.0
0.1
7.0
μA
OVC Latch Discharge Current
VCOMP = 1.0 V
100
800
2500
μA
PWM Comparator Offset Voltage
0 V ≤ VFB ≤ 3.5 V
0.99
1.1
1.23
V
Transient Response
VFB = 0 to 3.5 V
−
200
300
ns
1.0
1.6
2.3
μs
PWM Comparator
COFF
Off−Time
−
Charge Current
VCOFF = 1.5 V
−
550
−
μA
Discharge Current
VCOFF = 1.5 V
−
25
−
mA
3. Guaranteed by design, not 100% tested in production.
http://onsemi.com
4
CS51311
ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < 70°C; 0°C < TJ < 125°C; 9.0 V < VCC < 14 V;
2.0 V DAC Code (VID4 = VID3 = VID2 = VID1 = 0, VID0 = 1.0) CGATE(H) = CGATE(L) = 3.3 nF, COFF = 390 pF; unless otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
Power Good Output
PWRGD Sink Current
VFB = 1.7 V, VPWRGD = 1.0 V
0.5
4.0
15
mA
PWRGD Upper Threshold
% of Nominal DAC Code
5.0
8.5
12
%
PWRGD Lower Threshold
% of Nominal DAC Code
−12
−8.5
−5.0
%
PWRGD Output Low Voltage
VFB = 1.7 V, IPWRGD = 500 μA
−
0.2
0.3
V
General Electrical Specifications
VCC Monitor Start Threshold
−
7.9
8.4
8.9
V
VCC Monitor Stop Threshold
−
7.6
8.1
8.6
V
0.15
0.3
0.6
V
−
12
20
mA
Hysteresis
Start−Stop
VCC Supply Current
No Load on GATE(H), GATE(L)
PACKAGE PIN DESCRIPTION
PACKAGE PIN #
SO−14
PIN SYMBOL
FUNCTION
1, 2, 3, 4, 5
VID0−VID4
Voltage ID DAC inputs. These pins are internally pulled up to 5.65 V if left
open. VID4 selects the DAC range. When VID4 is high (logic one), the Error
Amp reference range is 2.125 V to 3.525 V with 100 mV increments. When
VID4 is low (logic zero), the Error Amp reference voltage is 1.325 V to 2.075 V
with 50 mV increments.
6
VFB
7
VOUT
Current limit comparator inverting input.
8
VCC
Input power supply pin for the internal circuitry. Decouple with filter capacitor to
GND.
9
GATE(H)
10
GND
11
GATE(L)
Low side synchronous FET driver pin.
12
PWRGD
Power Good Output. Open collector output drives low when VFB is out of regulation.
13
COFF
14
COMP
Error amp inverting input, PWM comparator non−inverting input, current limit
comparator non−inverting input, PWRGD comparator input.
High side switch FET driver pin.
Ground pin.
Off−Time Capacitor pin. A capacitor from this pin to GND sets the off time for
the regulator.
Error amp output. PWM comparator inverting input. A capacitor on this pin provides error amp compensation.
http://onsemi.com
5
CS51311
COMP
VFB
1.1 V
+
−
−
+
+
−
EA
Current Limit
VOUT
86 mV
+
−
+
−
COFF
−
+
+
−
PWM COMP
Off
Time
Discharge
COMP
R
Q
Fault
Latch
0.25 V
S
VID0
UVLO
VID1
VCC
DAC
VID2
VID3
VID4
GATE(H)
Nonoverlap
Logic
+
−
GATE(L)
+
−
PWRGD
Figure 2. Block Diagram
http://onsemi.com
6
GND
CS51311
TYPICAL PERFORMANCE CHARACTERISTICS
150
150
VCC = 12 V
TA = 25°C
100
75
50
100
75
50
25
0
VCC = 12 V
TA = 25°C
125
Risetime (ns)
25
0
2000 4000
0
6000 8000 10000 12000 14000 16000
0
2000 4000
Load Capacitance (pF)
Figure 3. GATE(H) and GATE(L) Falltime vs. Load
Capacitance
Figure 4. GATE(H) and GATE(L) Risetime vs. Load
Capacitance
0.10
0.10
VCC = 12 V
0.05
Output Error (%)
0.05
0
0
−0.05
−0.05
−0.10
DAC Output Voltage Setting (V)
Figure 5. DAC Output Voltage vs. Temperature,
DAC Code = 00001
Figure 6. Percent Output Error vs. DAC Output
Voltage Setting, VID4 = 0
Output Error (%)
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
−0.05
DAC Output Voltage Setting (V)
Figure 7. Percent Output Error vs. DAC Output
Voltage Setting, VID4 = 1
http://onsemi.com
7
3.525
3.325
3.225
3.025
2.925
2.725
2.625
2.525
2.425
2.325
2.125
−0.25
2.225
−0.20
3.125
VCC = 12 V
TA = 25°C
VID4 = 1
−0.10
−0.15
2.075
2.025
1.975
1.925
1.825
1.875
1.775
Load Capacitance (pF)
1.725
−0.20
120
1.675
100
1.625
80
1.575
60
1.525
40
1.475
20
1.375
0
1.425
−0.15
1.325
−0.15
VCC = 12 V
TA = 25°C
VID4 = 0
−0.10
2.825
DAC Output Voltage Deviation (%)
6000 8000 10000 12000 14000 16000
Load Capacitance (pF)
3.425
Falltime (ns)
125
CS51311
APPLICATIONS INFORMATION
THEORY OF OPERATION
The main purpose of this “slow” feedback loop is to provide
DC accuracy. Noise immunity is significantly improved,
since the error amplifier bandwidth can be rolled off at a low
frequency. Enhanced noise immunity improves remote
sensing of the output voltage, since the noise associated with
long feedback traces can be effectively filtered.
Line and load regulation are drastically improved because
there are two independent voltage loops. A voltage mode
controller relies on a change in the error signal to
compensate for a deviation in either line or load voltage.
This change in the error signal causes the output voltage to
change corresponding to the gain of the error amplifier,
which is normally specified as line and load regulation.
A current mode controller maintains fixed error signal
under deviation in the line voltage, since the slope of the
ramp signal changes, but still relies on a change in the error
signal for a deviation in load. The V2 method of control
maintains a fixed error signal for both line and load
variation, since the ramp signal is affected by both line and
load.
V2 Control Method
The V2 method of control uses a ramp signal that is
generated by the ESR of the output capacitors. This ramp is
proportional to the AC current through the main inductor
and is offset by the value of the DC output voltage. This
control scheme inherently compensates for variation in
either line or load conditions, since the ramp signal is
generated from the output voltage itself. This control
scheme differs from traditional techniques such as voltage
mode, which generates an artificial ramp, and current mode,
which generates a ramp from inductor current.
The V2 control method is illustrated in Figure 8. The
output voltage is used to generate both the error signal and
the ramp signal. Since the ramp signal is simply the output
voltage, it is affected by any change in the output regardless
of the origin of that change. The ramp signal also contains
the DC portion of the output voltage, which allows the
control circuit to drive the main switch to 0% or 100% duty
cycle as required.
Constant Off−Time
To minimize transient response, the CS51311 uses a
Constant Off−Time method to control the rate of output
pulses. During normal operation, the Off−Time of the high
side switch is terminated after a fixed period, set by the COFF
capacitor. Every time the VFB pin exceeds the COMP pin
voltage an Off−Time is initiated. To maintain regulation, the
V2 Control Loop varies switch On−Time. The PWM
comparator monitors the output voltage ramp, and
terminates the switch On−Time.
Constant Off−Time provides a number of advantages.
Switch Duty Cycle can be adjusted from 0 to 100% on a
pulse−by pulse basis when responding to transient
conditions. Both 0% and 100% Duty Cycle operation can be
maintained for extended periods of time in response to Load
or Line transients.
PWM
Comparator
GATE(H)
−
C
+
GATE(L)
Output
Voltage
Feedback
VFB
Ramp Signal
Error
Amplifier
COMP
Error
Signal
E
−
+
Reference
Voltage
Figure 8. V2 Control Diagram
Programmable Output
The CS51311 is designed to provide two methods for
programming the output voltage of the power supply. A five
bit on board digital to analog converter (DAC) is used to
program the output voltage within two different ranges. The
first range is 2.125 V to 3.525 V in 100 mV steps, the second
is 1.325 V to 2.075 V in 50 mV steps, depending on the
digital input code. If all five bits are left open, the CS51311
enters adjust mode. In adjust mode, the designer can choose
any output voltage by using resistor divider feedback to the
VFB pin, as in traditional controllers. The CS51311 is
specifically designed to meet or exceed Intel’s Pentium II
specifications.
A change in line voltage changes the current ramp in the
inductor, affecting the ramp signal, which causes the V2
control scheme to compensate the duty cycle. Since the
change in inductor current modifies the ramp signal, as in
current mode control, the V2 control scheme has the same
advantages in line transient response.
A change in load current will have an affect on the output
voltage, altering the ramp signal. A load step immediately
changes the state of the comparator output, which controls
the main switch. Load transient response is determined only
by the comparator response time and the transition speed of
the main switch. The reaction time to an output load step has
no relation to the crossover frequency of the error signal
loop, as in traditional control methods.
The error signal loop can have a low crossover frequency,
since transient response is handled by the ramp signal loop.
Error Amplifier
An inherent benefit of the V2 control topology is that there
is no large bandwidth requirement on the error amplifier
design. The reaction time to an output load step has no
http://onsemi.com
8
CS51311
capacitor will continue to slowly charge and the regulator
output voltage will follow it, less the 1.1 V PWM offset, until
it achieves the voltage programmed by the DAC’s VID
input. The Error Amp will then source or sink current to the
COMP cap as required to maintain the correct regulator DC
output voltage. Since the rate of increase of the COMP pin
voltage is typically set much slower than the regulator’s slew
capability, inrush current, output voltage, and duty cycle all
gradually increase from zero. (See Figures 9, 10, and 11).
relation to the crossover frequency, since transient response
is handled by the ramp signal loop. The main purpose of this
“slow” feedback loop is to provide DC accuracy. Noise
immunity is significantly improved, since the error
amplifier bandwidth can be rolled off at a low frequency.
Enhanced noise immunity improves remote sensing of the
output voltage, since the noise associated with long
feedback traces can be effectively filtered. The COMP pin
is the output of the error amplifier and a capacitor to GND
compensates the error amplifier loop. Additionally, through
the built−in offset on the PWM Comparator non−inverting
input, the COMP pin provides the hiccup timing for the
Overcurrent Protection, the Soft Start function that
minimizes inrush currents during regulator power−up and
switcher output enable.
Startup
The CS51311 provides a controlled startup of regulator
output voltage and features Programmable Soft Start
implemented through the Error Amp and external
Compensation Capacitor. This feature, combined with
overcurrent protection, prevents stress to the regulator
power components and overshoot of the output voltage
during startup.
As power is applied to the regulator, the CS51311
Undervoltage Lockout circuit (UVL) monitors the IC’s
supply voltage (VCC) which is typically connected to the
+12 V output of the AC−DC power supply. The UVL circuit
prevents the NFET gates from being activated until VCC
exceeds the 8.4 V (typ) threshold. Hysteresis of 300 mV
(typ) is provided for noise immunity. The Error Amp
Capacitor connected to the COMP pin is charged by a 30 μA
current source. This capacitor must be charged to 1.1 V (typ)
so that it exceeds the PWM comparator’s offset before the
V2 PWM control loop permits switching to occur.
When VCC has exceeded 8.4 V and COMP has charged to
1.1 V, the upper Gate driver (GATE(H)) is activated, turning
on the upper FET. This causes current to flow through the
output inductor and into the output capacitors and load
according to the following equation:
I + (VIN * VOUT)
Channel 1 − Regulator Output Voltage (1.0 V/div)
Channel 2 − COMP Pin (1.0 V/div)
Channel 3 − VCC (10 V/div)
Channel 4 − Regulator Input Voltage (5.0 V/div)
Figure 9. Normal Startup (2.0 ms/div)
T
L
GATE(H) and the upper NFET remain on and inductor
current ramps up until the initial pulse is terminated by either
the PWM control loop or the overcurrent protection. This
initial surge of in−rush current minimizes startup time, but
avoids overstressing of the regulator’s power components.
The PWM comparator will terminate the initial pulse if
the regulator output exceeds the voltage on the COMP pin
plus the 1.1 V PWM comparator offset prior to the drop
across the current sense resistor exceeding the current limit
threshold. In this case, the PWM control loop has achieved
regulation and the initial pulse is then followed by a constant
off time as programmed by the COFF capacitor. The COMP
Channel 1 − Regulator Output Voltage (1.0 V/div)
Channel 2 − Inductor Switching Node (5.0 V/div)
Channel 3 − VCC (10 V/div)
Channel 4 − Regulator Input Voltage (5.0 V/div)
Figure 10. Normal Startup Showing Initial Pulse
Followed by Soft Start (20 ms/div)
http://onsemi.com
9
CS51311
Because the start−up circuit depends on the current sense
function, a current sense resistor should always be used.
When driving large capacitive loads, the COMP must
charge slowly enough to avoid tripping the CS51311
overcurrent protection. The following equation can be used
to ensure unconditional startup:
ICHG
I
* ILOAD
t LIM
COUT
CCOMP
where:
ICHG = COMP Source Current (30 μA typical);
CCOMP = COMP Capacitor value (0.1 μF typical);
ILIM = Current Limit Threshold;
ILOAD = Load Current during startup;
COUT = Total Output Capacitance.
Normal Operation
Channel 1 − Regulator Output Voltage (1.0 V/div)
Channel 2 − Inductor Switching Node (5.0 V/div)
Channel 3 − VCC (10 V/div)
Channel 4 − Regulator Input Voltage (5.0 V/div)
During normal operation, Switch Off−Time is constant
and set by the COFF capacitor. Switch On−Time is adjusted
by the V2 Control loop to maintain regulation. This results
in changes in regulator switching frequency, duty cycle, and
output ripple in response to changes in load and line. Output
voltage ripple will be determined by inductor ripple current
and the ESR of the output capacitors
Figure 11. Pulse−By−Pulse Regulation During Soft
Start (2.0 ms/div)
If the voltage across the Current Sense resistor generates a
voltage difference between the VFB and VOUT pins that
exceeds the OVC Comparator Offset Voltage (86 mV typical),
the Fault latch is set. This causes the COMP pin to be quickly
discharged, turning off GATE(H) and the upper NFET since
the voltage on the COMP pin is now less than the 1.1 V PWM
comparator offset. The Fault latch is reset when the voltage on
the COMP decreases below the discharge threshold voltage
(0.25 V typical). The COMP capacitor will again begin to
charge, and when it exceeds the 1.1 V PWM comparator offset,
the regulator output will Soft Start normally (see Figure 12).
Transient Response
The CS51311 V2 Control Loop’s 200 ns reaction time
provides unprecedented transient response to changes in
input voltage or output current. Pulse−by−pulse adjustment
of duty cycle is provided to quickly ramp the inductor
current to the required level. Since the inductor current
cannot be changed instantaneously, regulation is maintained
by the output capacitor(s) during the time required to slew
the inductor current.
Overall load transient response is further improved
through a feature called “Adaptive Voltage Positioning”.
This technique pre−positions the output capacitors voltage
to reduce total output voltage excursions during changes in
load.
Holding tolerance to 1.0% allows the error amplifiers
reference voltage to be targeted +25 mV high without
compromising DC accuracy. A “Droop Resistor,”
implemented through a PC board trace, connects the Error
Amps feedback pin (VFB) to the output capacitors and load
and carries the output current. With no load, there is no DC
drop across this resistor, producing an output voltage
tracking the Error amps, including the +25 mV offset. When
the full load current is delivered, a 50 mV drop is developed
across this resistor. This results in output voltage being
offset −25 mV low.
The result of Adaptive Voltage Positioning is that
additional margin is provided for a load transient before
reaching the output voltage specification limits. When load
current suddenly increases from its minimum level, the
output capacitor is pre−positioned +25 mV. Conversely,
when load current suddenly decreases from its maximum
level, the output capacitor is pre−positioned −25 mV. For
Channel 1 − Regulator Output Voltage (1.0 V/div)
Channel 2 − COMP Pin (1.0 V/div)
Channel 3 − VCC (10 V/div)
Channel 4 − Regulator Input Voltage (5.0 V/div)
Figure 12. Startup with COMP Pre−Charge to 2.0 V
(2.0 ms/div)
http://onsemi.com
10
CS51311
compares the voltage drop through the “Droop” resistor to
an internal reference voltage of 86 mV (typical).
If the voltage drop across the “Droop” resistor exceeds
this threshold, the current sense comparator allows the fault
latch to be set. This causes the regulator to stop switching.
During this overcurrent condition, the CS51311 stays off
for the time it takes the COMP pin capacitor to discharge to
its lower 0.25 V threshold. As soon as the COMP pin reaches
0.25 V, the Fault latch is reset (no overcurrent condition
present) and the COMP pin is charged with a 30 μA current
source to a voltage 1.1 V greater than the VFB voltage. Only
at this point the regulator attempts to restart normally by
delivering short gate pulses to both FETS. The CS51311 will
operate initially with a duty cycle whose value depends on
how low the VFB voltage was during the overcurrent
condition (whether hiccup mode was due to excessive
current or hard short). This protection scheme minimizes
thermal stress to the regulator components, input power
supply, and PC board traces, as the overcurrent condition
persists. Upon removal of the overload, the fault latch is
cleared, allowing normal operation to resume.
best Transient Response, a combination of a number of high
frequency and bulk output capacitors are usually used.
Slope Compensation
The V2 control method uses a ramp signal, generated by
the ESR of the output capacitors, that is proportional to the
ripple current through the inductor. To maintain regulation,
the V2 control loop monitors this ramp signal, through the
PWM comparator, and terminates the switch on−time.
The stringent load transient requirements of modern
microprocessors require the output capacitors to have very
low ESR. The resulting shallow slope presented to the PWM
comparator, due to the very low ESR, can lead to pulse width
jitter and variation caused by both random or synchronous
noise.
Adding slope compensation to the control loop, avoids
erratic operation of the PWM circuit, particularly at lower
duty cycles and higher frequencies, where there is not
enough ramp signal, and provides a more stable switchpoint.
The scheme that prevents that switching noise
prematurely triggers the PWM circuit consists of adding a
positive voltage slope to the output of the Error Amplifier
(COMP pin) during an off−time cycle.
The circuit that implements this function is shown in
Figure 13.
Overvoltage Protection
Overvoltage protection (OVP) is provided as result of the
normal operation of the V2 control topology and requires no
additional external components. The control loop responds
to an overvoltage condition within 200 ns, causing the top
MOSFET to shut off, disconnecting the regulator from its
input voltage. This results in a “crowbar” action to clamp the
output voltage and prevents damage to the load. The
regulator will remain in this state until the overvoltage
condition ceases or the input voltage is pulled low. The
bottom FET and board trace must be properly designed to
implement the OVP function.
14
COMP
CCOMP
R2
CS51311
GATE(L)
11
C1
R1
To Synchronous FET
Power Good Circuit
Figure 13. Small RC Filter Provides the
Proper Voltage Ramp at the Beginning of
Each On−Time Cycle
The Power Good pin (pin 12) is an open−collector signal
consistent with TTL DC specifications. It is externally
pulled up, and is pulled low (below 0.3 V) when the
regulator output voltage typically exceeds ±8.5% of the
nominal output voltage. Maximum output voltage deviation
before Power Good is pulled low is ±12%.
The ramp waveform is generated through a small RC filter
that provides the proper voltage ramp at the beginning of
each on−time cycle. The resistors R1 and R2 in the circuit of
Figure 13 form a voltage divider from the GATE(L) output,
superimposing a small artificial ramp on the output of the
error amplifier. It is important that the series combination
R1/R2 is high enough in resistance not to load down and
negatively affect the slew rate on the GATE(L) pin.
Output Enable
On/off control of the regulator outputs can be
implemented by pulling the COMP pins low. It is required
to pull the COMP pins below the 1.1 V PWM comparator
offset voltage in order to disable switching on the GATE
drivers.
PROTECTION AND MONITORING FEATURES
CS51311−BASED VCC(CORE) BUCK REGULATOR
DESIGN PROCEDURE
Overcurrent Protection
A loss−less hiccup mode current limit protection feature
is provided, requiring only the COMP capacitor to
implement. The CS51311 provides overcurrent protection
by sensing the current through a “Droop” resistor, using an
internal current sense comparator. The comparator
Step 1: Definition of the Design Specifications
In computer motherboard applications the input voltage
comes from the “silver box” power supply. 5.0 V ± 5.0% is
http://onsemi.com
11
CS51311
depending on the load current transition) results from the
total output capacitor ESR.
The maximum allowable ESR can then be determined
according to the formula
used for conversion to output voltage, and 12 V ± 5.0% is
used for the external NFET gate voltage and circuit bias. The
CPU VCC(CORE) tolerance can be affected by any or all of
the following reasons:
1. buck regulator output voltage setpoint accuracy;
2. output voltage change due to discharging or charging
of the bulk decoupling capacitors during a load
current transient;
3. output voltage change due to the ESR and ESL of the
bulk and high frequency decoupling capacitors,
circuit traces, and vias;
4. output voltage ripple and noise.
Budgeting the tolerance is left up to the designer who must
take into account all of the above effects and provide a
VCC(CORE) that will meet the specified tolerance at the
CPU’s inputs.
The designer must also ensure that the regulator
component junction temperatures are kept within the
manufacturer’s specified ratings at full load and maximum
ambient temperature. As computer motherboards become
increasingly complex, regulator size also becomes
important, as there is less space available for the CPU power
supply.
DVESR
ESRMAX +
DIOUT
where ΔVESR = change in output voltage due to ESR
(assigned by the designer).
Once the maximum allowable ESR is determined, the
number of output capacitors can be found by using the
formula
Number of capacitors +
where:
ESRCAP = maximum ESR per capacitor (specified in
manufacturer’s data sheet);
ESRMAX = maximum allowable ESR.
The actual output voltage deviation due to ESR can then
be verified and compared to the value assigned by the
designer:
DVESR + DIOUT
ESRMAX
Similarly, the maximum allowable ESL is calculated from
the following formula:
Step 2: Selection of the Output Capacitors
These components must be selected and placed carefully
to yield optimal results. Capacitors should be chosen to
provide acceptable ripple on the regulator output voltage.
Key specifications for output capacitors are their ESR
(Equivalent Series Resistance), and ESL (Equivalent Series
Inductance). For best transient response, a combination of
low value/high frequency and bulk capacitors placed close
to the load will be required.
In order to determine the number of output capacitors the
maximum voltage transient allowed during load transitions
has to be specified. The output capacitors must hold the
output voltage within these limits since the inductor current
can not change with the required slew rate. The output
capacitors must therefore have a very low ESL and ESR.
The voltage change during the load current transient is:
DVOUT + DIOUT
ESRCAP
ESRMAX
ESLMAX +
DVESL
DI
Dt
where:
ΔI/ΔT = load current slew rate (as high as 20 A/μs);
ΔVESL = change in output voltage due to ESL.
The actual maximum allowable ESL can be determined
by using the equation:
ESLMAX +
ESLCAP
Number of output capacitors
where ESLCAP = maximum ESL per capacitor (it is
estimated that a 10 × 12 mm Aluminum Electrolytic
capacitor has approximately 4.0 nH of package inductance).
The actual output voltage deviation due to the actual
maximum ESL can then be verified:
ǒESL
) ESR ) tTR Ǔ
Dt
COUT
DVESL +
ESLMAX
Dt
DI
The designer now must determine the change in output
voltage due to output capacitor discharge during the
transient:
where:
ΔIOUT / Δt = load current slew rate;
ΔIOUT = load transient;
Δt = load transient duration time;
ESL = Maximum allowable ESL including capacitors,
circuit traces, and vias;
ESR = Maximum allowable ESR including capacitors and
circuit traces;
tTR = output voltage transient response time.
The designer has to independently assign values for the
change in output voltage due to ESR, ESL, and output
capacitor discharging or charging. Empirical data indicates
that most of the output voltage change (droop or spike
DVCAP +
DI DtTR
COUT
where:
ΔtTR = the output voltage transient response time
(assigned by the designer);
ΔVCAP = output voltage deviation due to output capacitor
discharge;
ΔI = Load step.
The total change in output voltage as a result of a load
current transient can be verified by the following formula:
http://onsemi.com
12
CS51311
be kept as low as possible to minimize resistive power loss.
There are a variety of materials and types of magnetic cores
that could be used for this application. Among them are
ferrites, molypermalloy cores (MPP), amorphous and
powdered iron cores. Powdered iron cores are very
commonly used. Powdered iron cores are very suitable due
to their high saturation flux density and have low loss at high
frequencies, a distributed gap and exhibit very low EMI.
The inductor value can be determined by:
DVOUT + DVESR ) DVESL ) DVCAP
Step 3: Selection of the Duty Cycle,
Switching Frequency, Switch On−Time (TON)
and Switch Off−Time (TOFF)
The duty cycle of a buck converter (including parasitic
losses) is given by the formula:
V
) (VHFET ) VL ) VDROOP)
Duty Cycle + D + OUT
VIN ) VLFET * VHFET * VL
where:
VOUT = buck regulator output voltage;
VHFET = high side FET voltage drop due to RDS(ON);
VL = output inductor voltage drop due to inductor wire DC
resistance;
VDROOP = droop (current sense) resistor voltage drop;
VIN = buck regulator input voltage;
VLFET = low side FET voltage drop due to RDS(ON).
L+
V
DIL + OUT
The Switch On−Time (time during which the switching
MOSFET in a synchronous buck topology is conducting) is
determined by:
Duty Cycle
FSW
DIL +
TOFF
DVOUT
ESRMAX
Rearranging we have:
ESRMAX +
Step 3b: Calculation of Switch Off−Time
The Switch Off−Time (time during which the switching
MOSFET is not conducting) can be determined by:
DVOUT
DIL
where
ESRMAX = maximum allowable ESR;
ΔVOUT = 1.0% × VOUT = maximum allowable output
voltage ripple ( budgeted by the designer );
ΔIL = inductor ripple current;
VOUT = output voltage.
The number of output capacitors is determined by:
TOFF + 1.0 * TON
FSW
The COFF capacitor value has to be selected in order to set
the Off−Time, TOFF, above:
Period
L
where:
ΔIL = inductor ripple current;
VOUT = output voltage;
TOFF = switch Off−Time;
L = inductor value.
The designer can now verify if the number of output
capacitors from Step 2 will provide an acceptable output
voltage ripple (1.0% of output voltage is common). The
formula below is used:
where FSW = regulator switching frequency selected by the
designer.
Higher operating frequencies allow the use of smaller
inductor and capacitor values. Nevertheless, it is common to
select lower frequency operation because a higher frequency
results in lower efficiency due to MOSFET gate charge
losses. Additionally, the use of smaller inductors at higher
frequencies results in higher ripple current, higher output
voltage ripple, and lower efficiency at light load currents.
COFF +
tTR
where:
VIN = input voltage;
VOUT = output voltage;
tTR = output voltage transient response time (assigned by
the designer);
ΔI = load transient.
The inductor ripple current can then be determined:
Step3a: Calculation of Switch On−Time
TON +
(VIN * VOUT)
DI
(1.0 * D)
3980
Number of capacitors +
where:
3980 is a characteristic factor of the CS51311;
D = Duty Cycle.
ESRCAP
ESRMAX
where ESRCAP = maximum ESR per capacitor (specified in
manufacturer’s data sheet).
The designer must also verify that the inductor value
yields reasonable inductor peak and valley currents (the
inductor current is a triangular waveform):
Step 4: Selection of the Output Inductor
The inductor should be selected based on its inductance,
current capability, and DC resistance. Increasing the
inductor value will decrease output voltage ripple, but
degrade transient response. There are many factors to
consider in selecting the inductor including cost, efficiency,
EMI and ease of manufacture. The inductor must be able to
handle the peak current at the switching frequency without
saturating, and the copper resistance in the winding should
IL(PEAK) + IOUT )
where:
IL(PEAK) = inductor peak current;
IOUT = load current;
http://onsemi.com
13
DIL
2.0
CS51311
ΔIL = inductor ripple current.
IL(VALLEY) + IOUT *
ESRCIN +
DIL
2.0
where:
ESRCIN = total input capacitor ESR;
ESRCAP = maximum ESR per capacitor (specified in
manufacturer’s data sheets);
NCIN = number of input capacitors.
Once the total ESR of the input capacitors is known, the
input capacitor ripple voltage can be determined using the
formula:
where IL(VALLEY) = inductor valley current.
Given the requirements of an application such as a buck
converter, it is found that a toroid powdered iron core is quite
suitable due to its low cost, low core losses at the switching
frequency, and low EMI.
Step 5: Selection of the Input Capacitors
These components must be selected and placed carefully
to yield optimal results. Capacitors should be chosen to
provide acceptable ripple on the input supply lines. A key
specification for input capacitors is their ripple current
rating. The input capacitor should also be able to handle the
input RMS current IIN(RMS).
The combination of the input capacitors CIN discharges
during the on−time.
The input capacitor discharge current is given by:
VCIN(RMS) + ICIN(RMS)
Ǹ
ȡ
ȧ
Ȣ
ȣ
ȧ
Ȥ
PCIN(RMS) + ICIN(RMS)2
Step 6: Selection of the Input Inductor
where:
ICINDIS(RMS) = input capacitor discharge current;
IL(PEAK) = inductor peak current;
IL(VALLEY) = inductor valley current.
CIN charges during the off−time, the average current
through the capacitor over one switching cycle is zero:
A CPU switching regulator, such as the one in a buck
topology, must not disturb the primary +5.0 V supply. One
method of achieving this is by using an input inductor and
a bypass capacitor. The input inductor isolates the +5.0 V
supply from the noise generated in the switching portion of
the microprocessor buck regulator and also limits the inrush
current into the input capacitors upon power up. The
inductor’s limiting effect on the input current slew rate
becomes increasingly beneficial during load transients. The
worst case is when the CPU load changes from no load to full
load (load step), a condition under which the highest voltage
change across the input capacitors is also seen by the input
inductor. The inductor successfully blocks the ripple current
while placing the transient current requirements on the input
bypass capacitor bank, which has to initially support the
sudden load change.
The minimum inductance value for the input inductor is
therefore:
D
1.0 * D
where:
ICIN(CH) = input capacitor charge current;
ICIN(DIS) = input capacitor discharge current;
D = Duty Cycle.
The total Input RMS current is:
ICIN(RMS) +
ESRCIN
where:
PCIN(RMS) = input capacitor RMS power dissipation;
ICIN(RMS) = total input RMS current;
ESRCIN = total input capacitor ESR.
D
3.0
ICIN(CH) + ICIN(DIS)
ESRCIN
where:
VCIN(RMS) = input capacitor RMS voltage;
ICIN(RMS) = total input RMS current;
ESRCIN = total input capacitor ESR.
The designer must determine the input capacitor power
loss in order to ensure there isn’t excessive power
dissipation through these components. The following
formula is used:
ICINDIS(RMS) +
IL(PEAK)2
) (IL(PEAK) IL(VALLEY))
) IL(VALLEY)2
ESRCAP
NCIN
Ǹ
(ICIN(DIS)2 D)
) (ICIN(CH)2 (1.0 * D))
The number of input capacitors required is then
determined by:
I
NCIN + CIN(RMS)
IRIPPLE
LIN +
DV
(dIńdt)MAX
where:
LIN = input inductor value;
ΔV = voltage seen by the input inductor during a full load
swing;
(dI/dt)MAX = maximum allowable input current slew rate
(0.1 A/μs for a Pentium II power supply).
The designer must select the LC filter pole frequency so
that at least 40 dB attenuation is obtained at the regulator
where:
NCIN = number of input capacitors;
ICIN(RMS) = total input RMS current;
IRIPPLE = input capacitor ripple current rating (specified
in manufacturer’s data sheets).
The total input capacitor ESR needs to be determined in
order to calculate the power dissipation of the input
capacitors:
http://onsemi.com
14
CS51311
switching frequency. The LC filter is a double−pole network
with a slope of −2, a roll−off rate of —40 dB/dec, and a
corner frequency:
fC +
determined by the gate−drive impedance and CISS changes
during the switching cycle. Consequently, computation of
the rise time of the gate voltage by using a specific
gate−drive impedance and input capacitance yields only a
rough estimate. The second consideration is the effect of the
“Miller” capacitance, CRSS, which is referred to as CDG in
the following discussion. For example, when a device is on,
VDS(ON) is fairly small and VGS is about 12 V. CDG is
charged to VDS(ON) − VGS, which is a negative potential if
the drain is considered the positive electrode. When the
drain is “off”, CDG is charged to quite a different potential.
In this case the voltage across CDG is a positive value since
the potential from gate−to−source is near zero volts and VDS
is essentially the drain supply voltage. During turn−on and
turn−off, these large swings in gate−to−drain voltage tax the
current sourcing and sinking capabilities of the gate drive.
In addition to charging and discharging CGS, the gate drive
must also supply the displacement current required by
CDG(IGATE = CDG dVDG/dt). Unless the gate−drive
impedance is very low, the VGS waveform commonly
plateaus during rapid changes in the drain−to−source
voltage.
The most important aspect of FET performance is the
Static Drain−To−Source On−Resistance (RDS(ON)), which
effects regulator efficiency and FET thermal management
requirements. The On−Resistance determines the amount of
current a FET can handle without excessive power
dissipation that may cause overheating and potentially
catastrophic failure. As the drain current rises, especially
above the continuous rating, the On−Resistance also
increases. Its positive temperature coefficient is between
+0.6%/C and +0.85%/C. The higher the On−Resistance the
larger the conduction loss is. Additionally, the FET gate
charge should be low in order to minimize switching losses
and reduce power dissipation.
Both logic level and standard FETs can be used. The
reference designs derive gate drive from the 12 V supply,
which is generally available in most computer systems and
utilizes logic level FETs.
Voltage applied to the FET gates depends on the
application circuit used. Both upper and lower gate driver
outputs are specified to drive to within 1.5 V of ground when
in the low state and to within 2.0 V of their respective bias
supplies when in the high state. In practice, the FET gates
will be driven rail−to−rail due to overshoot caused by the
capacitive load they present to the controller IC.
1.0
2.0p ǸLC
where:
L = input inductor;
C = input capacitor(s).
Step 7: Selection of the Switching FET
FET Basics
The use of the MOSFET as a power switch is propelled by
two reasons: 1) Its very high input impedance; and 2) Its very
fast switching times. The electrical characteristics of a
MOSFET are considered to be those of a perfect switch.
Control and drive circuitry power is therefore reduced.
Because the input impedance is so high, it is voltage driven.
The input of the MOSFET acts as if it were a small capacitor,
which the driving circuit must charge at turn on. The lower
the drive impedance, the higher the rate of rise of VGS, and
the faster the turn−on time. Power dissipation in the
switching MOSFET consists of 1) conduction losses, 2)
leakage losses, 3) turn−on switching losses, 4) turn−off
switching losses, and 5) gate−transitions losses. The latter
three losses are proportional to frequency. For the
conducting power dissipation rms values of current and
resistance are used for true power calculations. The fast
switching speed of the MOSFET makes it indispensable for
high−frequency power supply applications. Not only are
switching power losses minimized, but also the maximum
usable switching frequency is considerably higher.
Switching time is independent of temperature. Also, at
higher frequencies, the use of smaller and lighter
components (transformer, filter choke, filter capacitor)
reduces overall component cost while using less space for
more efficient packaging at lower weight.
The MOSFET has purely capacitive input impedance. No
DC current is required. It is important to keep in mind the
drain current of the FET has a negative temperature
coefficient. Increase in temperature causes higher
on−resistance and greater leakage current. For switching
circuits, VDS(ON) should be low to minimize power
dissipation at a given ID, and VGS should be high to
accomplish this. MOSFET switching times are determined
by device capacitance, stray capacitance, and the impedance
of the gate drive circuit. Thus the gate driving circuit must
have high momentary peak current sourcing and sinking
capability for switching the MOSFET. The input
capacitance, output capacitance and reverse−transfer
capacitance also increase with increased device current
rating.
Two considerations complicate the task of estimating
switching times. First, since the magnitude of the input
capacitance, CISS, varies with VDS, the RC time constant
Step 7a: Selection of the Switching (Upper) FET
The designer must ensure that the total power dissipation
in the FET switch does not cause the power component’s
junction temperature to exceed 150°C.
The maximum RMS current through the switch can be
determined by the following formula:
http://onsemi.com
15
CS51311
Step 7b: Selection of the Synchronous (Lower) FET
IRMS(H) +
Ǹ
ȡ
ȧ
Ȣ
ȣ
ȧ
Ȥ
IL(PEAK)2
) (IL(PEAK) IL(VALLEY))
) IL(VALLEY)2
The switch conduction losses for the lower FET can be
calculated as follows:
PRMSL + IRMS2
D
+ ǒIOUT
3.0
RDS(ON)
where:
PRMS(H) = switching MOSFET conduction losses;
IRMS(H) = maximum switching MOSFET RMS current;
RDS(ON) = FET drain−to−source on−resistance
The upper MOSFET switching losses are caused during
MOSFET switch−on and switch−off and can be determined
by using the following formula:
PSWL + VSD
IOUT
(tRISE ) tFALL)
6.0T
where:
PSWH(ON) = upper MOSFET switch−on losses;
PSWH(OFF) = upper MOSFET switch−off losses;
VIN = input voltage;
IOUT = load current;
tRISE = MOSFET rise time (from FET manufacturer’s
switching characteristics performance curve);
tFALL = MOSFET fall time (from FET manufacturer’s
switching characteristics performance curve);
T = 1/FSW = period.
The total power dissipation in the switching MOSFET can
then be calculated as:
ILOAD
non−overlap time
FSW
PLFET(TOTAL) + PRMSL ) PSWL
where:
PLFET(TOTAL) = Synchronous (lower) FET total losses;
PRMSL = Switch Conduction Losses;
PSWL = Switching losses.
Once the total power dissipation in the synchronous FET
is known the maximum FET switch junction temperature
can be calculated:
TJ + TA ) (PLFET(TOTAL)
PHFET(TOTAL) + PRMSH ) PSWH(ON) ) PSWH(OFF)
RqJA)
where:
TJ = MOSFET junction temperature;
TA = ambient temperature;
PLFET(TOTAL) = total synchronous (lower) FET losses;
RθJA = lower FET junction−to−ambient thermal
resistance.
where:
PHFET(TOTAL) = total switching (upper) MOSFET losses;
PRMSH = upper MOSFET switch conduction Losses;
PSWH(ON) = upper MOSFET switch−on losses;
PSWH(OFF) = upper MOSFET switch−off losses.
Once the total power dissipation in the switching FET is
known, the maximum FET switch junction temperature can
be calculated:
TJ + TA ) (PHFET(TOTAL)
RDS(ON)
where:
PSWL = lower FET switching losses;
VSD = lower FET source−to−drain voltage;
ILOAD = load current
Non−overlap time = GATE(L)−to−GATE(H) or
GATE(H)−to−GATE(L) delay (from CS51311 data sheet
Electrical Characteristics section);
FSW = switching frequency.
The total power dissipation in the synchronous (lower)
MOSFET can then be calculated as:
PSWH + PSWH(ON) ) PSWH(OFF)
V
+ IN
Ǹ(1.0 * D)Ǔ2
where:
PRMSL = lower MOSFET conduction losses;
IOUT = load current;
D = Duty Cycle;
RDS(ON) = lower FET drain−to−source on−resistance.
The synchronous MOSFET has no switching losses,
except for losses in the internal body diode, because it turns
on into near zero voltage conditions. The MOSFET body
diode will conduct during the non−overlap time and the
resulting power dissipation (neglecting reverse recovery
losses) can be calculated as follows:
where:
IRMS(H) = maximum switching MOSFET RMS current;
IL(PEAK) = inductor peak current;
IL(VALLEY) = inductor valley current;
D = Duty Cycle.
Once the RMS current through the switch is known, the
switching MOSFET conduction losses can be calculated:
PRMS(H) + IRMS(H)2
RDS(ON)
Step 8: Control IC Power Dissipation
The power dissipation of the IC varies with the MOSFETs
used, VCC, and the CS51311 operating frequency. The
average MOSFET gate charge current typically dominates
the control IC power dissipation.
The IC power dissipation is determined by the formula:
RqJA)
where:
TJ = FET junction temperature;
TA = ambient temperature;
PHFET(TOTAL) = total switching (upper) FET losses;
RθJA = upper FET junction−to−ambient thermal resistance.
PCONTROLIC + ICCVCC ) PGATE(H) ) PGATE(L)
where:
http://onsemi.com
16
CS51311
PCONTROLIC = control IC power dissipation;
ICC = IC quiescent supply current;
VCC = IC supply voltage;
PGATE(H) = upper MOSFET gate driver (IC) losses;
PGATE(L) = lower MOSFET gate driver (IC) losses.
The upper (switching) MOSFET gate driver (IC) losses
are:
PGATE(H) + QGATE(H)
FSW
stability provided that the RC filter time constant is smaller
than the off−time cycle duration (time during which the
lower MOSFET is conducting).
Step 10: Selection of Current Limit Filter Components
The current limit filter is implemented by a 0.1 μF ceramic
capacitor across and two 510 Ω resistors in series with the
VFB and VOUT current limit comparator input pins. They
provide a time constant τ = RC = 100 μs, which enables the
circuit to filter out noise and be immune to false triggering,
caused by sudden and fast load changes. These load
transients can have slew rates as high as 20 A/μs.
VGATE(H)
where:
PGATE(H) = upper MOSFET gate driver (IC) losses;
QGATE(H) = total upper MOSFET gate charge;
FSW = switching frequency;
VGATE(H) = upper MOSFET gate voltage.
The lower (synchronous) MOSFET gate driver (IC)
losses are:
PGATE(L) + QGATE(L)
FSW
“DROOP” RESISTOR FOR ADAPTIVE VOLTAGE
POSITIONING AND CURRENT LIMIT
Adaptive voltage positioning is used to help keep the
output voltage within specification during load transients.
To implement adaptive voltage positioning a “Droop
Resistor” must be connected between the output inductor
and output capacitors and load. This resistor carries the full
load current and should be chosen so that both DC and AC
tolerance limits are met. An embedded PC trace resistor has
the distinct advantage of near zero cost implementation.
However, this droop resistor can vary due to three reasons:
1) the sheet resistivity variation caused by variation in the
thickness of the PCB layer; 2) the mismatch of L/W; and 3)
temperature variation.
VGATE(L)
where:
PGATE(L) = lower MOSFET gate driver (IC) losses;
QGATE(L) = total lower MOSFET gate charge;
FSW = switching frequency;
VGATE(L) = lower MOSFET gate voltage.
The junction temperature of the control IC is primarily a
function of the PCB layout, since most of the heat is removed
through the traces connected to the pins of the IC.
Step 9: Slope Compensation
1) Sheet Resistivity
Voltage regulators for today’s advanced processors are
expected to meet very stringent load transient requirements.
One of the key factors in achieving tight dynamic voltage
regulation is low ESR at the CPU input supply pins. Low
ESR at the regulator output results in low output voltage
ripple. The consequence is, however, that there’s very little
voltage ramp at the control IC feedback pin (VFB) and
regulator sensitivity to noise and loop instability are two
undesirable effects that can surface. The performance of the
CS51311−based CPU VCC(CORE) regulator is improved
when a fixed amount of slope compensation is added to the
output of the PWM Error Amplifier (COMP pin) during the
regulator Off−Time. Referring to Figure 13, the amount of
voltage ramp at the COMP pin is dependent on the gate
voltage of the lower (synchronous) FET and the value of
resistor divider formed by R1 and R2.
VSLOPECOMP + VGATE(L)
For one ounce copper, the thickness variation is typically
1.26 mil to 1.48 mil. Therefore the error due to sheet
resistivity is:
1.48 * 1.26 +" 8.0%
1.37
2) Mismatch Due to L/W
The variation in L/W is governed by variations due to the
PCB manufacturing process. The error due to L/W
mismatch is typically 1.0%.
3) Thermal Considerations
Due to I2 × R power losses the surface temperature of the
droop resistor will increase causing the resistance to
increase. Also, the ambient temperature variation will
contribute to the increase of the resistance, according to the
formula:
ǒR1 R2
Ǔ ǒ1.0 * e *tt Ǔ
) R2
R + R20[1.0 ) a20(T * 20)]
where:
VSLOPECOMP = amount of slope added;
VGATE(L) = lower MOSFET gate voltage;
R1, R2 = voltage divider resistors;
t = tOFF (switch off−time);
τ = RC constant determined by C1 and the parallel
combination of R1, R2 (Figure 13), neglecting the low
driver output impedance
The artificial voltage ramp created by the slope
compensation scheme results in improved control loop
where:
R20 = resistance at 20°C;
α = 0.00393/°C
T= operating temperature;
R = desired droop resistor value.
For temperature T = 50°C, the % R change = 12%.
Droop Resistor Tolerance
Tolerance due to sheet resistivity variation
Tolerance due to L/W error
http://onsemi.com
17
±8.0%
1.0%
CS51311
Tolerance due to temperature variation
12%
Total tolerance for droop resistor
21%
In order to determine the droop resistor value the nominal
voltage drop across it at full load has to be calculated. This
voltage drop has to be such that the output voltage at full load
is above the minimum DC tolerance spec:
Let’s assume the full CPU load is 16A. The internal
current sense comparator current limit voltage limits are:
77 mV < VTH < 101 mV. Also, there is a 21% total variation
in RSENSE as discussed in the previous section.
We compute the value of the current sensing element
(embedded PCB trace) for the minimum current limit
setpoint:
VDAC(MIN) * VDC(MIN)
VDROOP(TYP) +
1.0 ) RDROOP(TOLERANCE)
Example: for a 450 MHz Pentium II, the DC accuracy
spec is 1.93 < VCC(CORE) < 2.07 V, and the AC accuracy spec
is 1.9 V < VCC(CORE) < 2.1 V. The CS51311 DAC output
voltage is +2.001 V < VDAC < +2.049 V. In order not to
exceed the DC accuracy spec, the voltage drop developed
across the resistor must be calculated as follows:
RSENSE(MIN) + RSENSE(TYP)
0.79
RSENSE(MAX) + RSENSE(TYP)
1.21
V
RSENSE(MAX) + TH(MIN) + 77 mV + 4.8 mW
16 A
ICL(MIN)
We select,
RSENSE(TYP) + 3.3 mW
(VDAC(MIN) * VDC(MIN))
VDROOP(TYP) +
1.0 ) RDROOP(TOLERANCE)
We calculate the range of load currents that will cause the
internal current sense comparator to detect an overload
condition.
+ +2.001 V * 1.93 V + 71 mV
1.21
With the CS51311 DAC accuracy being 1.0%, the internal
error amplifier’s reference voltage is trimmed so that the
output voltage will be 25 mV high at no load. With no load,
there is no DC drop across the resistor, producing an output
voltage tracking the error amplifier output voltage,
including the offset. When the full load current is delivered,
a drop of −50 mV is developed across the resistor. Therefore,
the regulator output is pre−positioned at 25 mV above the
nominal output voltage before a load turn−on. The total
voltage drop due to a load step is ΔV − 25 mV and the
deviation from the nominal output voltage is 25 mV smaller
than it would be if there was no droop resistor. Similarly at
full load the regulator output is pre−positioned at 25 mV
below the nominal voltage before a load turn−off. the total
voltage increase due to a load turn−off is ΔV − 25 mV and
the deviation from the nominal output voltage is 25 mV
smaller than it would be if there was no droop resistor. This
is because the output capacitors are pre−charged to a value
that is either 25 mV above the nominal output voltage before
a load turn−on or, 25 mV below the nominal output voltage
before a load turn−off .
Obviously, the larger the voltage drop across the droop
resistor (the larger the resistance), the worse the DC and load
regulation, but the better the AC transient response.
Nominal Current Limit Setpoint
From the overcurrent detection data in the electrical
characteristics table:
VTH(TYP) + 86 mV
ICL(NOM) +
VTH(TYP)
+ 86 mV + 26 A
3.3 mW
RSENSE(NOM)
Maximum Current Limit Setpoint
From the overcurrent detection data in the electrical
characteristics table:
VTH(MAX) + 101 mV
ICL(MAX) +
+
VTH(MAX)
VTH(MAX)
+
RSENSE(MIN)
RSENSE(NOM) 0.79
101 mV
+ 38.7 A
3.3 mW 0.79
Therefore, the range of load currents that will cause the
internal current sense comparator to detect an overload
condition through a 3.3mΩ embedded PCB trace is: 19.3 A
< ICL < 38.7 A, with 26 A being the nominal overload
condition.
Design Rules for Using a Droop Resistor
The basic equation for laying an embedded resistor is:
Current Limit
RAR + ò
The current limit setpoint has to be higher than the normal
full load current. Attention has to be paid to the current rating
of the external power components as these are the first to fail
during an overload condition. The MOSFET continuous and
pulsed drain current rating at a given case temperature has
to be accounted for when setting the current limit trip point.
Temperature curves on MOSFET manufacturers’ data
sheets allow the designer to determine the MOSFET drain
current at a particular VGS and TJ (junction temperature).
This, in turn, will assist the designer to set a proper current
limit, without causing device breakdown during an overload
condition.
L or R + ò
A
(W
L
t)
where:
A = W × t = cross−sectional area;
ρ = the copper resistivity (μΩ−mil);
L = length (mils);
W = width (mils);
t = thickness (mils).
For most PCBs the copper thickness, t, is 35 μm (1.37
mils) for one ounce copper; ρ = 717.86 μΩ−mil.
For a CPU load of 16 A the resistance needed to create a
50 mV drop at full load is:
http://onsemi.com
18
CS51311
layout techniques such as thermal vias and additional copper
foil area can be used to improve the power handling
capability of surface mount components.
RDROOP + 50 mV + 50 mV + 3.1 mW
16 A
IOUT
The resistivity of the copper will drift with the
temperature according to the following guidelines:
EMI MANAGEMENT
As a consequence of large currents being turned on and off
at high frequency, switching regulators generate noise as a
consequence of their normal operation. When designing for
compliance with EMI/EMC regulations, additional
components may be added to reduce noise emissions. These
components are not required for regulator operation and
experimental results may allow them to be eliminated. The
input filter inductor may not be required because bulk filter
and bypass capacitors, as well as other loads located on the
board will tend to reduce regulator di/dt effects on the circuit
board and input power supply. Placement of the power
component to minimize routing distance will also help to
reduce emissions.
DR + 12% @ TA + +50°C;
DR + 34% @ TA + +100°C;
Droop Resistor Length, Width, and Thickness
The minimum width and thickness of the droop resistor
should primarily be determined on the basis of the
current−carrying capacity required, and the maximum
permissible droop resistor temperature rise. PCB
manufacturer design charts can be used in determining
current−carrying capacity and sizes of etched copper
conductors for various temperature rises above ambient.
For single conductor applications, such as the use of the
droop resistor, PCB design charts show that for a droop
resistor with a required current−carrying capacity of 16 A,
and a 45°C temperature rise above ambient, the
recommended cross section is 275 mil2.
W
LAYOUT GUIDELINES
When laying out the CPU buck regulator on a printed
circuit board, the following checklist should be used to
ensure proper operation of the CS51311.
1. Rapid changes in voltage across parasitic capacitors
and abrupt changes in current in parasitic inductors
are major concerns for a good layout.
2. Keep high currents out of sensitive ground
connections.
3. Avoid ground loops as they pick up noise. Use star or
single point grounding.
4. For high power buck regulators on double−sided
PCBs a single ground plane (usually the bottom) is
recommended.
5. Even though double sided PCBs are usually sufficient
for a good layout, four−layer PCBs are the optimum
approach to reducing susceptibility to noise. Use the
two internal layers as the power and GND planes, the
top layer for power connections and component vias,
and the bottom layer for the noise sensitive traces.
6. Keep the inductor switching node small by placing
the output inductor, switching and synchronous FETs
close together.
7. The MOSFET gate traces to the IC must be as short,
straight, and wide as possible.
8. Use fewer, but larger output capacitors, keep the
capacitors clustered, and use multiple layer traces
with heavy copper to keep the parasitic resistance
low.
9. Place the switching MOSFET as close to the +5.0 V
input capacitors as possible.
10. Place the output capacitors as close to the load as
possible.
11. Place the VFB, VOUT filter resistors (510 Ω) in series
with the VFB and VOUT pins as close as possible to the
pins.
t + 275 mil2
where:
W = droop resistor width;
t = droop resistor thickness.
For 1 oz. copper, t = 1.37 mils, therefore W = 201 mils =
0.201 in.
R+ò
W
L
t
where:
R = droop resistor value;
ρ = 0.71786 mΩ−mil (1 oz. copper);
L = droop resistor length;
W = droop resistor width.
RDROOP + 3.3 mW
3.3 mW + 0.71786 mW−mil
201 mils
L
1.37 mils
Hence, L = 1265 mils = 1.265 in.
In layouts where it is impractical to lay out a droop resistor
in a straight line 1265 mils long, the embedded PCB trace
can be “snaked” to fit within the available space.
THERMAL MANAGEMENT
Thermal Considerations for Power MOSFETs
In order to maintain good reliability, the junction
temperature of the semiconductor components should be
kept to a maximum of 150°C or lower. The thermal
impedance (junction to ambient) required to meet this
requirement can be calculated as follows:
T
* TA
Thermal Impedance + J(MAX)
Power
A heatsink may be added to TO−220 components to
reduce their thermal impedance. A number of PC board
http://onsemi.com
19
CS51311
12. Place the COFF and COMP capacitors as close as
possible to the COFF and COMP pins.
13. Place the current limit filter capacitor between the
VFB and VOUT pins, as close as possible to the pins.
14. Connect the filter components of the following pins:
VFB, VOUT, COFF, and COMP to the GND pin with a
single trace, and connect this local GND trace to the
output capacitor GND.
15. The “Droop” Resistor (embedded PCB trace) has to
be wide enough to carry the full load current.
16. Place the VCC bypass capacitor as close as possible to
the IC.
http://onsemi.com
20
CS51311
PACKAGE DIMENSIONS
SO−14
D SUFFIX
CASE 751A−03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
−A−
14
8
−B−
1
0.25 (0.010)
7
G
D 14 PL
0.25 (0.010)
T B
M
F
M
K
M
B
M
R X 45 _
C
−T−
SEATING
PLANE
P 7 PL
S
A
J
S
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337
0.344
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.228
0.244
0.010
0.019
PACKAGE THERMAL DATA
Parameter
SO−14
Unit
RΘJC
Typical
30
°C/W
RΘJA
Typical
125
°C/W
V2 is a trademark of Switch Power, Inc.
Pentium is a registered trademark of Intel Corporation.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5773−3850
http://onsemi.com
21
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
CS51311/D