CS5171, CS5172, CS5173, CS5174 1.5 A 280 kHz/560 kHz Boost Regulators The CS5171/2/3/4 products are 280 kHz/560 kHz switching regulators with a high efficiency, 1.5 A integrated switch. These parts operate over a wide input voltage range, from 2.7 V to 30 V. The flexibility of the design allows the chips to operate in most power supply configurations, including boost, flyback, forward, inverting, and SEPIC. The ICs utilize current mode architecture, which allows excellent load and line regulation, as well as a practical means for limiting current. Combining high frequency operation with a highly integrated regulator circuit results in an extremely compact power supply solution. The circuit design includes provisions for features such as frequency synchronization, shutdown, and feedback controls for either positive or negative voltage regulation. These parts are pin−to−pin compatible with LT1372/1373. http://onsemi.com SOIC−8 D SUFFIX CASE 751 MARKING DIAGRAM AND PIN CONNECTIONS 1 Part Number Frequency Feedback Voltage Polarity CS5171 280 kHz positive FB negative Test 280 kHz CS5173 560 kHz positive CS5174 560 kHz negative VSW 517xy ALYW G CS5172 SS • © Semiconductor Components Industries, LLC, 2006 October, 2006 − Rev. 22 1 1 VSW VC Test NFB SS AGND CS5172/4 8 517xy ALYW G • • • • • Integrated Power Switch: 1.5 A Guaranteed Wide Input Range: 2.7 V to 30 V High Frequency Allows for Small Components Minimum External Components Easy External Synchronization Built in Overcurrent Protection Frequency Foldback Reduces Component Stress During an Overcurrent Condition Thermal Shutdown with Hysteresis Regulates Either Positive or Negative Output Voltages Shut Down Current: 50 mA Maximum Pin−to−Pin Compatible with LT1372/1373 Wide Temperature Range ♦ Industrial Grade: −40°C to 125°C ♦ Commercial Grade: 0°C to 125°C Pb−Free Packages are Available PGND VCC Features • • • • • • • CS5171/3 8 VC PGND AGND VCC 517xy = Device Code x= 1, 2, 3, or 4 y= E, G A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 20 of this data sheet. Publication Order Number: CS5171/D CS5171, CS5172, CS5173, CS5174 R2 3.72 k 2 C1 0.01 mF 3 D1 FB Test VOUT 8 VSW VC CS5171/3 1 5V MBRS120T3 7 PGND 6 AGND L1 4 SS 5 VCC SS + 22 mH C3 22 mF 3.3 V R3 R1 5k + C2 22 mF 1.28 k Figure 1. Applications Diagram MAXIMUM RATINGS Rating Value Unit Junction Temperature Range, TJ −40 to +150 °C Storage Temperature Range, TSTORAGE −65 to +150 °C 45 165 °C/W °C/W 230 Peak °C 1.2 kV Package Thermal Resistance, Junction−to−Case, RqJC Junction−to−Ambient, RqJA Lead Temperature Soldering: Reflow (Note 1) ESD, Human Body Model Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. 60 second maximum above 183°C. MAXIMUM RATINGS Pin Name Pin Symbol VMAX VMIN ISOURCE ISINK IC Power Input VCC 35 V −0.3 V N/A 200 mA Shutdown/Sync SS 30 V −0.3 V 1.0 mA 1.0 mA Loop Compensation VC 6.0 V −0.3 V 10 mA 10 mA Voltage Feedback Input FB (CS5171/3 only) 10 V −0.3 V 1.0 mA 1.0 mA Negative Feedback Input (transient, 10 ms) NFB (CS5172/4 only) −10 V 10 V 1.0 mA 1.0 mA Test 6.0 V −0.3 V 1.0 mA 1.0 mA Power Ground PGND 0.3 V −0.3 V 4A 10 mA Analog Ground AGND 0V 0V N/A 10 mA VSW 40 V −0.3 V 10 mA 3.0 A Test Pin Switch Input http://onsemi.com 2 CS5171, CS5172, CS5173, CS5174 ELECTRICAL CHARACTERISTICS (2.7 V< VCC < 30 V; Industrial Grade: −40°C < TJ < 125°C; Commercial Grade: 0°C < TJ < 125°C; For all CS5171/2/3/4 specifications unless otherwise stated.) Test Conditions Characteristic Min Typ Max Unit Positive and Negative Error Amplifiers FB Reference Voltage (CS5171/3 only) VC tied to FB; measure at FB 1.246 1.276 1.300 V NFB Reference Voltage (CS5172/4 only) VC = 1.25 V −2.55 −2.45 −2.35 V FB Input Current (CS5171/3 only) FB = VREF −1.0 0.1 1.0 mA NFB Input Current (CS5172/4 only) NFB = NVREF −16 −10 −5.0 mA FB Reference Voltage Line Regulation (CS5171/3 only) VC = FB − 0.01 0.03 %/V NFB Reference Voltage Line Regulation (CS5172/4 only) VC = 1.25 V − 0.01 0.05 %/V Positive Error Amp Transconductance IVC = ± 25 mA 300 550 800 mMho Negative Error Amp Transconductance IVC = ± 5 mA 115 160 225 mMho Positive Error Amp Gain (Note 2) 200 500 − V/V Negative Error Amp Gain (Note 2) 100 180 320 V/V VC Source Current FB = 1.0 V or NFB = −1.9 V, VC = 1.25 V 25 50 90 mA VC Sink Current FB = 1.5 V or NFB = −3.1 V, VC = 1.25 V 200 625 1500 mA VC High Clamp Voltage FB = 1.0 V or NFB = −1.9 V; VC sources 25 mA 1.5 1.7 1.9 V VC Low Clamp Voltage FB = 1.5 V or NFB = −3.1 V, VC sinks 25 mA 0.25 0.50 0.65 V VC Threshold Reduce VC from 1.5 V until switching stops 0.75 1.05 1.30 V CS5171/2, FB = 1 V or NFB = −1.9 V 230 280 310 kHz Reduced Operating Frequency CS5171/2, FB = 0 V or NFB = 0 V 30 52 120 kHz Maximum Duty Cycle CS5171/2 90 94 − % Base Operating Frequency CS5173/4, FB = 1 V or NFB = −1.9 V 460 560 620 kHz Reduced Operating Frequency CS5173/4, FB = 0 V or NFB = 0 V 60 104 160 kHz Maximum Duty Cycle CS5173/4 82 90 − % NFB Frequency Shift Threshold Frequency drops to reduced operating frequency −0.80 −0.65 −0.50 V FB Frequency Shift Threshold Frequency drops to reduced operating frequency 0.36 0.40 0.44 V Sync Range CS5171/2 320 − 500 kHz Sync Range CS5173/4 640 − 1000 kHz Sync Pulse Transition Threshold Rise time = 20 ns 2.5 − − V SS Bias Current SS = 0 V SS = 3.0 V −15 − −3.0 3.0 − 8.0 mA mA 0.50 0.85 1.20 V 12 12 80 36 350 200 ms ms Oscillator Base Operating Frequency Sync/ Shutdown Shutdown Threshold Shutdown Delay − 2.7 V ≤ VCC ≤ 12 V 12 V < VCC ≤ 30 V 2. Guaranteed by design, not 100% tested in production. http://onsemi.com 3 CS5171, CS5172, CS5173, CS5174 ELECTRICAL CHARACTERISTICS (2.7 V< VCC < 30 V; Industrial Grade: −40°C < TJ < 125°C; Commercial Grade: 0°C < TJ < 125°C; For all CS5171/2/3/4 specifications unless otherwise stated.) Characteristic Test Conditions Min Typ Max Unit − − − − 0.8 0.55 0.75 0.09 1.4 − − 0.45 V V V V Power Switch Switch Saturation Voltage ISWITCH = 1.5 A, (Note 3) ISWITCH = 1.0 A, 0°C ≤ TJ ≤ 85°C ISWITCH = 1.0 A, −40°C ≤ TJ ≤ 0°C ISWITCH = 10 mA Switch Current Limit 50% duty cycle, (Note 3) 80% duty cycle, (Note 3) 1.6 1.5 1.9 1.7 2.4 2.2 A A Minimum Pulse Width FB = 0 V or NFB = 0 V, ISW = 4.0 A, (Note 3) 200 250 300 ns DICC/ DIVSW 2.7 V ≤ VCC ≤ 12 V, 10 mA ≤ ISW ≤ 1.0 A 12 V < VCC ≤ 30 V, 10 mA ≤ ISW ≤ 1.0 A 2.7 V ≤ VCC ≤ 12 V, 10 mA ≤ ISW ≤ 1.5 A, (Note 3) 12 V < VCC ≤ 30 V, 10 mA ≤ ISW ≤ 1.5 A, (Note 3) − − − − 10 − 17 − 30 100 30 100 mA/A mA/A mA/A mA/A Switch Leakage VSW = 40 V, VCC = 0V − 2.0 100 mA Operating Current ISW = 0 − 5.5 8.0 mA Shutdown Mode Current VC < 0.8 V, SS = 0 V, 2.7 V ≤ VCC ≤ 12 V VC < 0.8 V, SS = 0 V, 12 V ≤ VCC ≤ 30 V − − 12 − 60 100 mA Minimum Operation Input Voltage VSW switching, maximum ISW = 10 mA − 2.45 2.70 V Thermal Shutdown (Note 3) 150 180 210 °C Thermal Hysteresis (Note 3) − 25 − °C General 3. Guaranteed by design, not 100% tested in production. PACKAGE PIN DESCRIPTION Package Pin # Pin Symbol 1 VC Loop compensation pin. The VC pin is the output of the error amplifier and is used for loop compensation, current limit and soft start. Loop compensation can be implemented by a simple RC network as shown in the application diagram on page 2 as R1 and C1. 2 (CS5171/3 only) FB Positive regulator feedback pin. This pin senses a positive output voltage and is referenced to 1.276 V. When the voltage at this pin falls below 0.4 V, chip switching frequency reduces to 20% of the nominal frequency. 2 (CS5172/4) 3 CS5171/3) Test These pins are connected to internal test logic and should either be left floating or tied to ground. Connection to a voltage between 2 V and 6 V shuts down the internal oscillator and leaves the power switch running. 3 (CS5172/4) NFB Negative feedback pin. This pin senses a negative output voltage and is referenced to −2.5 V. When the voltage at this pin goes above −0.65 V, chip switching frequency reduces to 20% of the nominal frequency. 4 SS Synchronization and shutdown pin. This pin may be used to synchronize the part to nearly twice the base frequency. A TTL low will shut the part down and put it into low current mode. If synchronization is not used, this pin should be either tied high or left floating for normal operation. 5 VCC Input power supply pin. This pin supplies power to the part and should have a bypass capacitor connected to AGND. 6 AGND Analog ground. This pin provides a clean ground for the controller circuitry and should not be in the path of large currents. The output voltage sensing resistors should be connected to this ground pin. This pin is connected to the IC substrate. 7 PGND Power ground. This pin is the ground connection for the emitter of the power switching transistor. Connection to a good ground plane is essential. 8 VSW Function High current switch pin. This pin connects internally to the collector of the power switch. The open voltage across the power switch can be as high as 40 V. To minimize radiation, use a trace as short as practical. http://onsemi.com 4 CS5171, CS5172, CS5173, CS5174 VCC Thermal Shutdown Shutdown 2.0 V Regulator VSW Oscillator Delay Timer S PWM Latch R Q Switch Driver Sync SS Frequency Shift 5:1 ×5 200 k 2.0 V NFB CS5172/4 only 250 k Slope Compensation Negative Error Amp 63 mW + Ramp Summer − PWM Comparator −0.65 V Detector + 0.4 V Detector FB − CS5171/3 only + 1.276 V Positive Error Amp AGND VC Figure 2. Block Diagram http://onsemi.com 5 − PGND CS5171, CS5172, CS5173, CS5174 TYPICAL PERFORMANCE CHARACTERISTICS 7.2 70 7.0 VCC = 12 V ISW = 1.5 A 50 (mA/A) Current (mA) 6.6 6.4 VCC = 30 V 60 VCC = 30 V 6.8 40 30 6.2 VCC = 12 V 20 6.0 5.8 5.6 0 50 Temperature (°C) VCC = 2.7 V 10 VCC = 2.7 V 0 100 0 100 Figure 4. DICC/ DIVSW vs. Temperature Figure 3. ICC (No Switching) vs. Temperature 1.9 1200 1000 −40 °C 800 1.8 85 °C 600 VIN (V) VCE(SAT) (mV) 50 Temperature (°C) 1.7 25 °C 400 1.6 200 0 500 1.5 1000 0 ISW (mA) 285 fOSC (kHz) fOSC (kHz) 280 275 270 265 260 0 50 Temperature (°C) 100 Figure 6. Minimum Input Voltage vs. Temperature Figure 5. VCE(SAT) vs. ISW 255 50 Temperature (°C) 570 565 560 555 550 545 540 535 530 525 520 0 100 50 Temperature (°C) 100 Figure 8. Switching Frequency vs. Temperature (CS5173/4 only) Figure 7. Switching Frequency vs. Temperature (CS5171/2 only) http://onsemi.com 6 CS5171, CS5172, CS5173, CS5174 TYPICAL PERFORMANCE CHARACTERISTICS 100 fOSC (% of Typical) fOSC (% of Typical) VCC = (12 V) VCC = (12 V) 100 −40°C 75 85°C 50 25°C 25 0 350 380 400 VFB (mV) 420 85°C 75 −40°C 50 25 25°C 0 450 −550 −660 VNFB (mV) −725 Figure 10. Switching Frequency vs. VNFB (CS5172/4 only) Figure 9. Switching Frequency vs. VFB (CS5171/3 only) 1.280 VCC = 12 V −2.42 −2.44 1.274 VCC = 2.7 V 1.272 −2.45 VCC = 30 V VCC = 12 V −2.46 1.270 −2.47 1.268 0 50 Temperature (°C) VCC = 2.7 V −2.48 100 0 50 Temperature (°C) 100 Figure 12. Reference Voltage vs. Temperature (CS5172/4 only) Figure 11. Reference Voltage vs. Temperature (CS5171/3 only) 0.20 −7 0.18 −8 −9 0.16 INFB (mA) IFB (mA) VCC = 30 V −2.43 1.276 Voltage (V) Voltage (V) 1.278 VCC = 12 V 0.14 −10 0.12 −11 −12 0.10 0.08 VCC = 2.7 V 0 50 Temperature (°C) −13 −14 100 Figure 13. IFB vs. Temperature (CS5171/3 only) 0 50 Temperature (°C) 100 Figure 14. INFB vs. Temperature (CS5172/ 4 only) http://onsemi.com 7 CS5171, CS5172, CS5173, CS5174 TYPICAL PERFORMANCE CHARACTERISTICS 99 2.60 VCC = 30 V Duty Cycle (%) 98 Current (A) 2.50 2.40 VCC = 2.7 V 2.30 VCC = 12 V 2.20 0 VCC = 12 V 97 96 VCC = 2.7 V 95 94 VCC = 30 V 93 50 Temperature (°C) 0 100 50 Temperature (°C) 100 Figure 16. Maximum Duty Cycle vs. Temperature Figure 15. Current Limit vs. Temperature 1.1 1.7 1.0 VC High Clamp Voltage Voltage (V) Voltage (V) 1.5 1.3 1.1 0.9 0.7 VC Threshold 0.9 0.8 0.7 0.6 0.5 0.4 0 50 Temperature (°C) 0 100 100 50 Temperature (°C) Figure 18. Shutdown Threshold vs. Temperature Figure 17. VC Threshold and High Clamp Voltage vs. Temperature 40 160 25°C VCC = 2.7 V 140 30 85°C 100 ISS (mA) Delay (ms) 120 VCC = 12 V 80 VCC = 30 V 60 50 Temperature (°C) −40°C 10 0 40 0 20 −10 100 1 3 5 VSS (V) Figure 20. ISS vs. VSS Figure 19. Shutdown Delay vs. Temperature http://onsemi.com 8 7 9 CS5171, CS5172, CS5173, CS5174 TYPICAL PERFORMANCE CHARACTERISTICS gm (mmho) ICC (mA) 600 −40°C 40 30 25°C 20 85°C 550 500 10 450 0 10 VIN (V) 50 Temperature (°C) 100 Figure 22. Error Amplifier Transconductance vs. Temperature (CS5171/3 only) Figure 21. ICC vs. VIN During Shutdown 100 190 180 170 160 150 140 130 120 110 100 60 IOUT (mA) gm (mmho) 0 20 −20 −60 0 50 Temperature (°C) 100 −255 −175 −125 −75 −25 VREF − VFB (mV) 0 25 Figure 24. Error Amplifier IOUT vs. VFB (CS5171/3 only) Figure 23. Negative Error Amplifier Transconductance vs. Temperature (CS5172/4 only) 2.6 100 80 60 40 20 0 −20 −40 IOUT (mA) Current (mA) 2.5 −60 2.4 2.3 2.2 2.1 −200 −150 −100 −50 VREF − VNFB (mV) 2.0 50 0 0 50 Temperature (°C) 100 Figure 26. Switch Leakage vs. Temperature Figure 25. Error Amplifier IOUT vs. VNFB (CS5172/4 only) http://onsemi.com 9 CS5171, CS5172, CS5173, CS5174 APPLICATIONS INFORMATION THEORY OF OPERATION The oscillator is trimmed to guarantee an 18% frequency accuracy. The output of the oscillator turns on the power switch at a frequency of 280 kHz (CS5171/2) or 560 kHz (CS5173/4), as shown in Figure 27. The power switch is turned off by the output of the PWM Comparator. A TTL−compatible sync input at the SS pin is capable of syncing up to 1.8 times the base oscillator frequency. As shown in Figure 28, in order to sync to a higher frequency, a positive transition turns on the power switch before the output of the oscillator goes high, thereby resetting the oscillator. The sync operation allows multiple power supplies to operate at the same frequency. A sustained logic low at the SS pin will shut down the IC and reduce the supply current. An additional feature includes frequency shift to 20% of the nominal frequency when either the NFB or FB pins trigger the threshold. During power up, overload, or short circuit conditions, the minimum switch on−time is limited by the PWM comparator minimum pulse width. Extra switch off−time reduces the minimum duty cycle to protect external components and the IC itself. As previously mentioned, this block also produces a ramp for the slope compensation to improve regulator stability. Current Mode Control VCC Oscillator S VC − + Q L R D1 Power Switch VSW PWM Comparator In Out X5 CO Driver RLOAD SUMMER Slope Compensation 63 mW Figure 27. Current Mode Control Scheme The CS517x family incorporates a current mode control scheme, in which the PWM ramp signal is derived from the power switch current. This ramp signal is compared to the output of the error amplifier to control the on−time of the power switch. The oscillator is used as a fixed−frequency clock to ensure a constant operational frequency. The resulting control scheme features several advantages over conventional voltage mode control. First, derived directly from the inductor, the ramp signal responds immediately to line voltage changes. This eliminates the delay caused by the output filter and error amplifier, which is commonly found in voltage mode controllers. The second benefit comes from inherent pulse−by−pulse current limiting by merely clamping the peak switching current. Finally, since current mode commands an output current rather than voltage, the filter offers only a single pole to the feedback loop. This allows both a simpler compensation and a higher gain−bandwidth over a comparable voltage mode circuit. Without discrediting its apparent merits, current mode control comes with its own peculiar problems, mainly, subharmonic oscillation at duty cycles over 50%. The CS517x family solves this problem by adopting a slope compensation scheme in which a fixed ramp generated by the oscillator is added to the current ramp. A proper slope rate is provided to improve circuit stability without sacrificing the advantages of current mode control. Error Amplifier 200 k NFB 250 k 2.0 V + CS5172/4 − negative error−amp 1.276 V + FB VC 1MW 120 pF Voltage Clamp − CS5171/3 C1 0.01 mF R1 5 kW positive error−amp Figure 29. Error Amplifier Equivalent Circuit For CS5172/4, the NFB pin is internally referenced to −2.5 V with approximately a 250 kW input impedance. For CS5171/3, the FB pin is directly connected to the inverting input of the positive error amplifier, whose non−inverting input is fed by the 1.276 V reference. Both amplifiers are transconductance amplifiers with a high output impedance of approximately 1 MW, as shown in Figure 29. The VC pin is connected to the output of the error amplifiers and is internally clamped between 0.5 V and 1.7 V. A typical connection at the VC pin includes a capacitor in series with a resistor to ground, forming a pole/zero for loop compensation. An external shunt can be connected between the VC pin and ground to reduce its clamp voltage. Consequently, the current limit of the internal power transistor current is reduced from its nominal value. Oscillator and Shutdown Sync Current Ramp VSW Figure 28. Timing Diagram of Sync and Shutdown http://onsemi.com 10 CS5171, CS5172, CS5173, CS5174 Switch Driver and Power Switch approximately 1.5 V, the internal power switch briefly turns on. This is a part of the CS517x’s normal operation. The turn−on of the power switch accounts for the initial current swing. When the VC pin voltage rises above the threshold, the internal power switch starts to switch and a voltage pulse can be seen at the VSW pin. Detecting a low output voltage at the FB pin, the built−in frequency shift feature reduces the switching frequency to a fraction of its nominal value, reducing the minimum duty cycle, which is otherwise limited by the minimum on−time of the switch. The peak current during this phase is clamped by the internal current limit. When the FB pin voltage rises above 0.4 V, the frequency increases to its nominal value, and the peak current begins to decrease as the output approaches the regulation voltage. The overshoot of the output voltage is prevented by the active pull−on, by which the sink current of the error amplifier is increased once an overvoltage condition is detected. The overvoltage condition is defined as when the FB pin voltage is 50 mV greater than the reference voltage. The switch driver receives a control signal from the logic section to drive the output power switch. The switch is grounded through emitter resistors (63 mW total) to the PGND pin. PGND is not connected to the IC substrate so that switching noise can be isolated from the analog ground. The peak switching current is clamped by an internal circuit. The clamp current is guaranteed to be greater than 1.5 A and varies with duty cycle due to slope compensation. The power switch can withstand a maximum voltage of 40 V on the collector (VSW pin). The saturation voltage of the switch is typically less than 1 V to minimize power dissipation. Short Circuit Condition When a short circuit condition happens in a boost circuit, the inductor current will increase during the whole switching cycle, causing excessive current to be drawn from the input power supply. Since control ICs don’t have the means to limit load current, an external current limit circuit (such as a fuse or relay) has to be implemented to protect the load, power supply and ICs. In other topologies, the frequency shift built into the IC prevents damage to the chip and external components. This feature reduces the minimum duty cycle and allows the transformer secondary to absorb excess energy before the switch turns back on. COMPONENT SELECTION Frequency Compensation The goal of frequency compensation is to achieve desirable transient response and DC regulation while ensuring the stability of the system. A typical compensation network, as shown in Figure 31, provides a frequency response of two poles and one zero. This frequency response is further illustrated in the Bode plot shown in Figure 32. IL VOUT VC R1 VCC CS5171 C2 VC C1 GND Figure 31. A Typical Compensation Network Figure 30. Startup Waveforms of Circuit Shown in the Application Diagram. Load = 400 mA. The high DC gain in Figure 32 is desirable for achieving DC accuracy over line and load variations. The DC gain of a transconductance error amplifier can be calculated as follows: The CS517x can be activated by either connecting the VCC pin to a voltage source or by enabling the SS pin. Startup waveforms shown in Figure 30 are measured in the boost converter demonstrated in the Application Diagram on the page 2 of this document. Recorded after the input voltage is turned on, this waveform shows the various phases during the power up transition. When the VCC voltage is below the minimum supply voltage, the VSW pin is in high impedance. Therefore, current conducts directly from the input power source to the output through the inductor and diode. Once VCC reaches GainDC + GM RO where: GM = error amplifier transconductance; RO = error amplifier output resistance ≈ 1 MW. The low frequency pole, fP1, is determined by the error amplifier output resistance and C1 as: 1 fP1 + 2pC1R http://onsemi.com 11 O CS5171, CS5172, CS5173, CS5174 The first zero generated by C1 and R1 is: −VOUT 2V 1 fZ1 + 2pC1R1 The phase lead provided by this zero ensures that the loop has at least a 45° phase margin at the crossover frequency. Therefore, this zero should be placed close to the pole generated in the power stage which can be identified at frequency: RP 200 kW R1 NFB R2 + − Negative Error−Amp 1 fP + 2pCORLOAD Figure 33. Negative Error Amplifier and NFB Pin where: CO = equivalent output capacitance of the error amplifier ≈120pF; RLOAD= load resistance. The high frequency pole, fP2, can be placed at the output filter’s ESR zero or at half the switching frequency. Placing the pole at this frequency will cut down on switching noise. The frequency of this pole is determined by the value of C2 and R1: It is shown that if R1 is less than 10 k, the deviation from the design target will be less than 0.1 V. If the tolerances of the negative voltage reference and NFB pin input current are considered, the possible offset of the output VOFFSET varies in the range of: (R1 ) R2) ǒ*0.0.5 R2 Ǔ * (15 mA R1) v VOFFSET 0.0.5 (R1 ) R2) Ǔ * (5 mA vǒ R2 1 fP2 + 2pC2R1 One simple method to ensure adequate phase margin is to design the frequency response with a −20 dB per decade slope, until unity−gain crossover. The crossover frequency should be selected at the midpoint between fZ1 and fP2 where the phase margin is maximized. DC Gain RIN 250 kW R1) VSW Voltage Limit In the boost topology, VSW pin maximum voltage is set by the maximum output voltage plus the output diode forward voltage. The diode forward voltage is typically 0.5 V for Schottky diodes and 0.8 V for ultrafast recovery diodes VSW(MAX) + VOUT(MAX))VF fP1 where: VF = output diode forward voltage. In the flyback topology, peak VSW voltage is governed by: Gain (dB) fZ1 fP2 VSW(MAX) + VCC(MAX))(VOUT)VF) where: N = transformer turns ratio, primary over secondary. When the power switch turns off, there exists a voltage spike superimposed on top of the steady−state voltage. Usually this voltage spike is caused by transformer leakage inductance charging stray capacitance between the VSW and PGND pins. To prevent the voltage at the VSW pin from exceeding the maximum rating, a transient voltage suppressor in series with a diode is paralleled with the primary windings. Another method of clamping switch voltage is to connect a transient voltage suppressor between the VSW pin and ground. Frequency (LOG) Figure 32. Bode Plot of the Compensation Network Shown in Figure 31 Negative Voltage Feedback Since the negative error amplifier has finite input impedance as shown in Figure 33, its induced error has to be considered. If a voltage divider is used to scale down the negative output voltage for the NFB pin, the equation for calculating output voltage is: *VOUT + ) R2) ǒ*2.5 (R1 Ǔ*10 mA R2 N R1 http://onsemi.com 12 CS5171, CS5172, CS5173, CS5174 Magnetic Component Selection IL IIN When choosing a magnetic component, one must consider factors such as peak current, core and ferrite material, output voltage ripple, EMI, temperature range, physical size and cost. In boost circuits, the average inductor current is the product of output current and voltage gain (VOUT/VCC), assuming 100% energy transfer efficiency. In continuous conduction mode, inductor ripple current is VCC + − CIN RESR * VCC) V (V IRIPPLE + CC OUT (f)(L)(VOUT) where: f = 280 kHz for CS5171/2 and 560 kHz for CS5173/4. The peak inductor current is equal to average current plus half of the ripple current, which should not cause inductor saturation. The above equation can also be referenced when selecting the value of the inductor based on the tolerance of the ripple current in the circuits. Small ripple current provides the benefits of small input capacitors and greater output current capability. A core geometry like a rod or barrel is prone to generating high magnetic field radiation, but is relatively cheap and small. Other core geometries, such as toroids, provide a closed magnetic loop to prevent EMI. Figure 35. Boost Circuit Effective Input Filter The situation is different in a flyback circuit. The input current is discontinuous and a significant pulsed current is seen by the input capacitors. Therefore, there are two requirements for capacitors in a flyback regulator: energy storage and filtering. To maintain a stable voltage supply to the chip, a storage capacitor larger than 20 mF with low ESR is required. To reduce the noise generated by the inductor, insert a 1.0 mF ceramic capacitor between VCC and ground as close as possible to the chip. Output Capacitor Selection Input Capacitor Selection In boost circuits, the inductor becomes part of the input filter, as shown in Figure 35. In continuous mode, the input current waveform is triangular and does not contain a large pulsed current, as shown in Figure 34. This reduces the requirements imposed on the input capacitor selection. During continuous conduction mode, the peak to peak inductor ripple current is given in the previous section. As we can see from Figure 34, the product of the inductor current ripple and the input capacitor’s effective series resistance (ESR) determine the VCC ripple. In most applications, input capacitors in the range of 10 mF to 100 mF with an ESR less than 0.3 W work well up to a full 1.5 A switch current. VOUT ripple IL Figure 36. Typical Output Voltage Ripple By examining the waveforms shown in Figure 36, we can see that the output voltage ripple comes from two major sources, namely capacitor ESR and the charging/discharging of the output capacitor. In boost circuits, when the power switch turns off, IL flows into the output capacitor causing an instant DV = IIN × ESR. At the same time, current IL − IOUT charges the capacitor and increases the output voltage gradually. When the power switch is turned on, IL is shunted to ground and IOUT discharges the output capacitor. When the IL ripple is small enough, IL can be treated as a constant and is equal to input current IIN. VCC ripple IIN IL Figure 34. Boost Input Voltage and Current Ripple Waveforms http://onsemi.com 13 CS5171, CS5172, CS5173, CS5174 Unfortunately, such a simple circuit is not generally acceptable if VIN is loosely regulated. Summing up, the output voltage peak−peak ripple can be calculated by: (I * IOUT)(1 * D) VOUT(RIPPLE) + IN (COUT)(f) ) IOUTD ) IIN (COUT)(f) VIN VCC ESR R2 The equation can be expressed more conveniently in terms of VCC, VOUT and IOUT for design purposes as follows: I (V * VCC) VOUT(RIPPLE) + OUT OUT (COUT)(f) VC D1 1 (COUT)(f) R3 (I )(V )(ESR) ) OUT OUT VCC R1 The capacitor RMS ripple current is: C1 IRIPPLE + Ǹ(IIN * IOUT)2(1 * D))(IOUT)2(D) + IOUT C2 * VCC ǸVOUTVCC Figure 37. Current Limiting using a Diode Clamp Although the above equations apply only for boost circuits, similar equations can be derived for flyback circuits. Another solution to the current limiting problem is to externally measure the current through the switch using a sense resistor. Such a circuit is illustrated in Figure 38. Reducing the Current Limit In some applications, the designer may prefer a lower limit on the switch current than 1.5 A. An external shunt can be connected between the VC pin and ground to reduce its clamp voltage. Consequently, the current limit of the internal power transistor current is reduced from its nominal value. The voltage on the VC pin can be evaluated with the equation VCC PGND AGND − + VIN VC R1 VC + ISWREAV Q1 where: RE = .063W, the value of the internal emitter resistor; AV = 5 V/V, the gain of the current sense amplifier. Since RE and AV cannot be changed by the end user, the only available method for limiting switch current below 1.5 A is to clamp the VC pin at a lower voltage. If the maximum switch or inductor current is substituted into the equation above, the desired clamp voltage will result. A simple diode clamp, as shown in Figure 37, clamps the VC voltage to a diode drop above the voltage on resistor R3. R2 C1 C2 C3 RSENSE Output Ground Figure 38. Current Limiting using a Current Sense Resistor The switch current is limited to VBE(Q1) ISWITCH(PEAK) + RSENSE where: VBE(Q1) = the base−emitter voltage drop of Q1, typically 0.65 V. http://onsemi.com 14 CS5171, CS5172, CS5173, CS5174 The improved circuit does not require a regulated voltage to operate properly. Unfortunately, a price must be paid for this convenience in the overall efficiency of the circuit. The designer should note that the input and output grounds are no longer common. Also, the addition of the current sense resistor, RSENSE, results in a considerable power loss which increases with the duty cycle. Resistor R2 and capacitor C3 form a low−pass filter to remove noise. The dashed box contains the normal compensation circuitry to limit the bandwidth of the error amplifier. Resistors R2 and R3 form a voltage divider off of the VSW pin. In normal operation, VSW looks similar to a square wave, and is dependent on the converter topology. Formulas for calculating VSW in the boost and flyback topologies are given in the section “VSW Voltage Limit.” The voltage on VSW charges capacitor C3 when the switch is off, causing the voltage at the VC pin to shift upwards. When the switch turns on, C3 discharges through R3, producing a negative slope at the VC pin. This negative slope provides the slope compensation. The amount of slope compensation added by this circuit is Subharmonic Oscillation Subharmonic oscillation (SHM) is a problem found in current−mode control systems, where instability results when duty cycle exceeds 50%. SHM only occurs in switching regulators with a continuous inductor current. This instability is not harmful to the converter and usually does not affect the output voltage regulation. SHM will increase the radiated EM noise from the converter and can cause, under certain circumstances, the inductor to emit high−frequency audible noise. SHM is an easily remedied problem. The rising slope of the inductor current is supplemented with internal “slope compensation” to prevent any duty cycle instability from carrying through to the next switching cycle. In the CS517x family, slope compensation is added during the entire switch on−time, typically in the amount of 180 mA/ms. In some cases, SHM can rear its ugly head despite the presence of the onboard slope compensation. The simple cure to this problem is more slope compensation to avoid the unwanted oscillation. In that case, an external circuit, shown in Figure 39, can be added to increase the amount of slope compensation used. This circuit requires only a few components and is “tacked on” to the compensation network. VSW ǒ Ǔ ǒ1 * e R3 DI + V SW R )R DT 2 3 *(1*D) R3C3fSW SW Ǔǒ(1 *fD)R Ǔ EAV where: DI/DT = the amount of slope compensation added (A/s); VSW = the voltage at the switch node when the transistor is turned off (V); fSW = the switching frequency, typically 280 kHz (CS5171/3) or 560 kHz (CS5172/4) (Hz); D = the duty cycle; RE = 0.063 W, the value of the internal emitter resistor; AV = 5 V/V, the gain of the current sense amplifier. In selecting appropriate values for the slope compensation network, the designer is advised to choose a convenient capacitor, then select values for R2 and R3 such that the amount of slope compensation added is 100 mA/ms. Then R2 may be increased or decreased as necessary. Of course, the series combination of R2 and R3 should be large enough to avoid drawing excessive current from VSW. Additionally, to ensure that the control loop stability is improved, the time constant formed by the additional components should be chosen such that VSW R3C3 t 1 * D fSW VC R1 Finally, it is worth mentioning that the added slope compensation is a tradeoff between duty cycle stability and transient response. The more slope compensation a designer adds, the slower the transient response will be, due to the external circuitry interfering with the proper operation of the error amplifier. R2 C1 C2 Soft−Start C3 Through the addition of an external circuit, a Soft−Start function can be added to the CS5171/2/3/4 family of components. Soft−Start circuitry prevents the VC pin from slamming high during startup, thereby inhibiting the inductor current from rising at a high slope. R3 Figure 39. Technique for Increasing Slope Compensation http://onsemi.com 15 CS5171, CS5172, CS5173, CS5174 when the switch is turned off. The specifications section of this datasheet reveals that the typical operating current, IQ, due to this circuitry is 5.5 mA. Additional guidance can be found in the graph of operating current vs. temperature. This graph shows that IQ is strongly dependent on input voltage, VIN, and temperature. Then This circuit, shown in Figure 40, requires a minimum number of components and allows the Soft−Start circuitry to activate any time the SS pin is used to restart the converter. VIN VCC SS PBIAS + VINIQ Since the onboard switch is an NPN transistor, the base drive current must be factored in as well. This current is drawn from the VIN pin, in addition to the control circuitry current. The base drive current is listed in the specifications as DICC/DISW, or switch transconductance. As before, the designer will find additional guidance in the graphs. With that information, the designer can calculate SS VC D2 D1 R1 C1 C3 ICC DISW PDRIVER + VINISW C2 D where: ISW = the current through the switch; D = the duty cycle or percentage of switch on−time. ISW and D are dependent on the type of converter. In a boost converter, Figure 40. Soft Start ISW(AVG) ^ ILOAD Resistor R1 and capacitors C1 and C2 form the compensation network. At turn on, the voltage at the VC pin starts to come up, charging capacitor C3 through Schottky diode D2, clamping the voltage at the VC pin such that switching begins when VC reaches the VC threshold, typically 1.05 V (refer to graphs for detail over temperature). D 1 Efficiency V * VIN D ^ OUT VOUT In a flyback converter, V I ISW(AVG) ^ OUT LOAD VIN VC + VF(D2))VC3 D^ Therefore, C3 slows the startup of the circuit by limiting the voltage on the VC pin. The Soft−Start time increases with the size of C3. Diode D1 discharges C3 when SS is low. If the shutdown function is not used with this part, the cathode of D1 should be connected to VIN. 1 Efficiency VOUT N VOUT ) NSP VIN The switch saturation voltage, V(CE)SAT, is the last major source of on−chip power loss. V(CE)SAT is the collector−emitter voltage of the internal NPN transistor when it is driven into saturation by its base drive current. The value for V(CE)SAT can be obtained from the specifications or from the graphs, as “Switch Saturation Voltage.” Thus, Calculating Junction Temperature To ensure safe operation of the CS5171/2/3/4, the designer must calculate the on−chip power dissipation and determine its expected junction temperature. Internal thermal protection circuitry will turn the part off once the junction temperature exceeds 180°C ± 30°. However, repeated operation at such high temperatures will ensure a reduced operating life. Calculation of the junction temperature is an imprecise but simple task. First, the power losses must be quantified. There are three major sources of power loss on the CS517x: • biasing of internal control circuitry, PBIAS • switch driver, PDRIVER • switch saturation, PSAT The internal control circuitry, including the oscillator and linear regulator, requires a small amount of power even PSAT ^ V(CE)SATISW D Finally, the total on−chip power losses are PD + PBIAS)PDRIVER)PSAT Power dissipation in a semiconductor device results in the generation of heat in the junctions at the surface of the chip. This heat is transferred to the surface of the IC package, but a thermal gradient exists due to the resistive properties of the package molding compound. The magnitude of the thermal gradient is expressed in manufacturers’ data sheets as qJA, or junction−to−ambient thermal resistance. The on−chip junction temperature can be calculated if qJA, the air temperature near the surface of the IC, and the on−chip power dissipation are known. http://onsemi.com 16 CS5171, CS5172, CS5173, CS5174 TJ + TA)(PDqJA) transitions that can cause problems. Therefore the following guidelines should be followed in the layout. where: TJ = IC or FET junction temperature (°C); TA = ambient temperature (°C); PD = power dissipated by part in question (W); qJA = junction−to−ambient thermal resistance (°C/W). For the CS517x, qJA=165°C/W. Once the designer has calculated TJ, the question of whether the CS517x can be used in an application is settled. If TJ exceeds 150°C, the absolute maximum allowable junction temperature, the CS517x is not suitable for that application. If TJ approaches 150°C, the designer should consider possible means of reducing the junction temperature. Perhaps another converter topology could be selected to reduce the switch current. Increasing the airflow across the surface of the chip might be considered to reduce TA. 1. 2. 3. Circuit Layout Guidelines In any switching power supply, circuit layout is very important for proper operation. Rapidly switching currents combined with trace inductance generates voltage In boost circuits, high AC current circulates within the loop composed of the diode, output capacitor, and on−chip power transistor. The length of associated traces and leads should be kept as short as possible. In the flyback circuit, high AC current loops exist on both sides of the transformer. On the primary side, the loop consists of the input capacitor, transformer, and on−chip power transistor, while the transformer, rectifier diodes, and output capacitors form another loop on the secondary side. Just as in the boost circuit, all traces and leads containing large AC currents should be kept short. Separate the low current signal grounds from the power grounds. Use single point grounding or ground plane construction for the best results. Locate the voltage feedback resistors as near the IC as possible to keep the sensitive feedback wiring short. Connect feedback resistors to the low current analog ground. R2 4.87 k 2 C1 C4 Test 3 NFB 0.01 mF 4 SS VSW VC SS CS5172/4 1 PGND AGND VOUT −12 V + 22 mF 7 MBRS120T3 6 + L1 VCC D1 8 5 22 mH D2 MBRS120T3 VCC 5.0 V R1 5.0 k R3 1.27 k + C2 22 mF Figure 41. Additional Application Diagram, 5.0 V to −12 V/ 75 mA Inverting Converter http://onsemi.com 17 C3 22 mF CS5171, CS5172, CS5173, CS5174 22 mH 3.3 VIN MBRS120T3 5.0 VO 10 mF 3.6 k VCC (5) PGND (7) GND 22 mF GND VSW (8) AGND (6) CS5171/3 VC (1 ) FB (2) 0.1 mF 1.3 k 200 pF 5.0 k Figure 42. Additional Application Diagram, 3.3 V Input, 5.0 V/ 400 mA Output Boost Converter MBRS140T3 VCC P6KE−15A + 22 mF −12 V T1 1.0 mF + 47 mF GND VCC (5) GND PGND (7) 1N4148 + 1:2 47 mF VSW (8) +12 V AGND (6) MBRS140T3 CS5171/3 VC (1 ) FB (2) 47 nF 10.72 k 1.28 k 4.7 nF 2.0 k Figure 43. Additional Application Diagram, 2.7 to 13 V Input, +12 V/ 200 mA Output Flyback Converter GND VCC (5) VC (1 ) GND 5.0 k 2.2 mF 22 mF CS5171/3 200 pF .01 mF VIN 15 mH VSW (8) AGND (6) 1.1 k Low ESR −5.0 VOUT FB (2) PGND (7) 300 Figure 44. Additional Application Diagram, −9.0 V to −28 V Input, −5.0 V/700 mA Output Inverted Buck Converter http://onsemi.com 18 CS5171, CS5172, CS5173, CS5174 22 mH VCC 22 mF VCC (5) PGND (7) GND VSW (8) AGND (6) 5.0 V + 22 mF CS5171/3 + 22 mH VC (1 ) 37.24 k 22 mF Low ESR FB (2) GND .01 mF 200 pF 5.0 k 12.76 k Figure 45. Additional Application Diagram, 2.7 V to 28 V Input, 5.0 V Output SEPIC Converter R1 R2 1.245 k/0.1 W, 1% 99.755 k/0.1 W, 1% GND C1 D1 C10 .1 m C11 .01 m 3 Test R3 2.0 k 4 SS VSW 8 PGND 7 CS5171/3 1 V C 2 FB AGND VCC .1 m 50 V D1 C3 .1 m 50 V D1 D1 .1 m 50 V D1 D1 D1 100 VO 1N4148 1N4148 6 5 C2 C8 10 m C9 .1 m C7 .1 m 50 V 1N4148 1N4148 1N4148 1N4148 1N4148 C4 .1 m 50 V C5 .1 m 50 V C6 .1 m 50 V GND 4.0 V Figure 46. Additional Application Diagram, 4.0 V Input, 100 V/ 10 mA Output Boost Converter with Output Voltage Multiplier 200 pF D1 C6 C1 0.01 mF 2 3 SS FB Test VSW 8 CS5171 5.0 k 1 V C + R1 4 SS PGND 7 L1 15 mH 22 mF AGND 6 VCC +5.0 V −12 V 5 D2 D3 + C3 22 mF + C5 22 mF C4 0.1 mF GND GND R2 R3 1.28 k 10.72 k +12 V Figure 47. Additional Application Diagram, 5.0 V Input, ± 12 V Output Dual Boost Converter http://onsemi.com 19 CS5171, CS5172, CS5173, CS5174 ORDERING INFORMATION Operating Temperature Range Package Shipping† SOIC−8 98 Units/Rail CS5171ED8G SOIC−8 (Pb−Free) 98 Units/Rail CS5171EDR8 SOIC−8 2500 Tape & Reel SOIC−8 (Pb−Free) 2500 Tape & Reel SOIC−8 98 Units/Rail CS5172ED8G SOIC−8 (Pb−Free) 98 Units/Rail CS5172EDR8 SOIC−8 2500 Tape & Reel SOIC−8 (Pb−Free) 2500 Tape & Reel SOIC−8 98 Units/Rail CS5173ED8G SOIC−8 (Pb−Free) 98 Units/Rail CS5173EDR8 SOIC−8 2500 Tape & Reel SOIC−8 (Pb−Free) 2500 Tape & Reel Device CS5171ED8 CS5171EDR8G CS5172ED8 CS5172EDR8G CS5173ED8 −40°C < TJ < 125°C CS5173EDR8G SOIC−8 98 Units/Rail CS5174ED8G SOIC−8 (Pb−Free) 98 Units/Rail CS5174EDR8 SOIC−8 2500 Tape & Reel SOIC−8 (Pb−Free) 2500 Tape & Reel CS5174ED8 CS5174EDR8G SOIC−8 98 Units/Rail CS5171GD8G SOIC−8 (Pb−Free) 98 Units/Rail CS5171GDR8 SOIC−8 2500 Tape & Reel SOIC−8 (Pb−Free) 2500 Tape & Reel SOIC−8 98 Units/Rail CS5172GD8G SOIC−8 (Pb−Free) 98 Units/Rail CS5172GDR8 SOIC−8 2500 Tape & Reel SOIC−8 (Pb−Free) 2500 Tape & Reel SOIC−8 98 Units/Rail CS5173GD8G SOIC−8 (Pb−Free) 98 Units/Rail CS5173GDR8 SOIC−8 2500 Tape & Reel SOIC−8 (Pb−Free) 2500 Tape & Reel SOIC−8 98 Units/Rail CS5174GD8G SOIC−8 (Pb−Free) 98 Units/Rail CS5174GDR8 SOIC−8 2500 Tape & Reel SOIC−8 (Pb−Free) 2500 Tape & Reel CS5171GD8 CS5171GDR8G CS5172GD8 CS5172GDR8G CS5173GD8 0°C < TJ < 125°C CS5173GDR8G CS5174GD8 CS5174GDR8G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 20 CS5171, CS5172, CS5173, CS5174 PACKAGE DIMENSIONS SOIC−8 D SUFFIX CASE 751−07 ISSUE AH NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. −X− A 8 5 0.25 (0.010) S B 1 M Y M 4 K −Y− G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− 0.10 (0.004) H D 0.25 (0.010) M Z Y S X M J S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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