74VCX16373 Low−Voltage 1.8/2.5/3.3V 16−Bit Transparent Latch With 3.6 V−Tolerant Inputs and Outputs (3−State, Non−Inverting) http://onsemi.com The 74VCX16373 is an advanced performance, non−inverting 16−bit transparent latch. It is designed for very high−speed, very low−power operation in 1.8 V, 2.5 V or 3.3 V systems. The VCX16373 is byte controlled, with each byte functioning identically, but independently. Each byte has separate Output Enable and Latch Enable inputs. These control pins can be tied together for full 16−bit operation. When operating at 2.5 V (or 1.8 V) the part is designed to tolerate voltages it may encounter on either inputs or outputs when interfacing to 3.3 V busses. It is guaranteed to be overvoltage tolerant to 3.6 V. The 74VCX16373 contains 16 D−type latches with 3−state 3.6 V−tolerant outputs. When the Latch Enable (LEn) inputs are HIGH, data on the Dn inputs enters the latches. In this condition, the latches are transparent, (a latch output will change state each time its D input changes). When LE is LOW, the latch stores the information that was present on the D inputs a setup time preceding the HIGH−to−LOW transition of LE. The 3−state outputs are controlled by the Output Enable (OEn) inputs. When OE is LOW, the outputs are enabled. When OE is HIGH, the standard outputs are in the high impedance state, but this does not interfere with new data entering into the latches. Features • Designed for Low Voltage Operation: VCC = 1.65 V − 3.6 V • 3.6 V Tolerant Inputs and Outputs • High Speed Operation: 3.0 ns max for 3.0 V to 3.6 V • • • • • • • 3.9 ns max for 2.3 V to 2.7 V 6.8 ns max for 1.65 V to 1.95 V Static Drive: ±24 mA Drive at 3.0 V ±18 mA Drive at 2.3 V ±6 mA Drive at 1.65 V Supports Live Insertion and Withdrawal IOFF Specification Guarantees High Impedance When VCC = 0 V Near Zero Static Supply Current in All Three Logic States (20 A) Substantially Reduces System Power Requirements Latchup Performance Exceeds ±250 mA @ 125°C ESD Performance: Human Body Model >2000 V; Machine Model >200 V All Devices in Package TSSOP are Inherently Pb−Free* MARKING DIAGRAM 48 48 VCX16373 1 AWLYYWW TSSOP−48 DT SUFFIX CASE 1201 A WL YY WW 1 = Assembly Location = Wafer Lot = Year = Work Week PIN NAMES Pins Function OEn LEn D0−D15 O0−O15 Output Enable Inputs Latch Enable Inputs Inputs Outputs ORDERING INFORMATION Package Shipping† 74VCX16373DT TSSOP (Pb−Free) 39 / Rail 74VCX16373DTR TSSOP (Pb−Free) 2500 / Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Semiconductor Components Industries, LLC, 2004 November, 2004 − Rev. 5 1 Publication Order Number: 74VCX16373/D 74VCX16373 OE1 1 O0 2 48 LE1 47 D0 O1 3 GND 4 O2 5 46 D1 45 GND O3 6 VCC 7 O4 8 O5 9 GND 10 O6 11 O7 12 O8 13 O9 14 GND 15 O10 16 OE1 LE1 D0 44 D2 43 D3 42 VCC 41 D4 40 D5 39 GND D1 D2 38 D6 37 D7 36 D8 35 D9 34 GND 33 D10 O11 17 VCC 18 32 D11 31 VCC O12 19 O13 20 30 D12 29 D13 GND 21 O14 22 28 GND 27 D14 O15 23 OE2 24 26 D15 25 LE2 D3 D4 D5 D6 D7 1 OE2 48 LE2 nLE 47 D nLE 46 D nLE 44 D nLE 43 D nLE 41 D nLE 40 D nLE 38 D nLE 37 D 2 Q 3 Q 5 Q 6 Q 8 Q 9 Q 11 Q 12 Q Figure 1. 48−Lead Pinout (Top View) O0 D8 O1 D9 O2 D10 O3 D11 O4 D12 O5 D13 O6 D14 O7 D15 24 25 36 35 33 32 30 29 27 26 Figure 2. Logic Diagram 1 OE1 48 LE1 25 LE2 24 OE2 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 EN1 EN2 EN3 EN4 1 1∇ 1 2∇ 1 3∇ 1 4∇ 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 Figure 3. IEC Logic Diagram http://onsemi.com 2 O0 O1 O2 O3 O4 O5 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15 nLE D nLE D nLE D nLE D nLE D nLE D nLE D nLE D Q Q Q Q Q Q Q Q 13 14 16 17 19 20 22 23 O8 O9 O10 O11 O12 O13 O14 O15 74VCX16373 TRUTH TABLE Inputs Outputs Inputs Outputs LE1 OE1 D0:7 O0:7 LE2 OE2 D8:15 O8:15 X H X Z X H X Z H L L L H L L L H L H H H L H H L. L X O0 L L X O0 H = High Voltage Level L = Low Voltage Level Z = High Impedance State X = High or Low Voltage Level and Transitions Are Acceptable, for ICC reasons, DO NOT FLOAT Inputs O0 = No Change ABSOLUTE MAXIMUM RATINGS Symbol Parameter VCC DC Supply Voltage VI VO Value Condition Unit −0.5 to +4.6 V DC Input Voltage −0.5 ≤ VI ≤ +4.6 V DC Output Voltage −0.5 ≤ VO ≤ +4.6 Output in 3−State −0.5 ≤ VO ≤ VCC + 0.5 Note 1; Outputs Active −50 VI < GND mA −50 VO < GND mA +50 VO > VCC IIK DC Input Diode Current IOK DC Output Diode Current V IO DC Output Source/Sink Current ±50 mA ICC DC Supply Current Per Supply Pin ±100 mA IGND DC Ground Current Per Ground Pin ±100 mA TSTG Storage Temperature Range −65 to +150 °C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. IO absolute maximum rating must be observed. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Typ Max Unit 1.65 1.2 3.3 3.3 3.6 3.6 V −0.3 3.6 V 0 0 VCC 3.6 V HIGH Level Output Current, VCC = 3.0 V − 3.6 V −24 mA IOL LOW Level Output Current, VCC = 3.0 V − 3.6 V 24 mA IOH HIGH Level Output Current, VCC = 2.3 V − 2.7 V −18 mA IOL LOW Level Output Current, VCC = 2.3 V − 2.7 V 18 mA IOH HIGH Level Output Current, VCC = 1.65 V − 1.95 V −6 mA IOL LOW Level Output Current, VCC = 1.65 V − 1.95 V 6 mA TA Operating Free−Air Temperature −40 +85 °C t/V Input Transition Rise or Fall Rate, VIN from 0.8 V to 2.0 V, VCC = 3.0 V 0 10 ns/V VCC Supply Voltage VI Input Voltage VO Output Voltage IOH Operating Data Retention Only (Active State) (3−State) http://onsemi.com 3 74VCX16373 DC ELECTRICAL CHARACTERISTICS TA = −40°C to +85°C Symbol VIH VIL VOH VOL Characteristic HIGH Level Input Voltage (Note 2) LOW Level Input Voltage (Note 2) HIGH Level Output Voltage LOW Level Output Voltage Condition Min 1.65 V ≤ VCC < 2.3 V 0.65 x VCC 2.3 V ≤ VCC ≤ 2.7 V 1.6 2.7 V < VCC ≤ 3.6 V 2.0 Max V 1.65 V ≤ VCC < 2.3 V 0.35 x VCC 2.3 V ≤ VCC ≤ 2.7 V 0.7 2.7 V < VCC ≤ 3.6 V 0.8 1.65 V ≤ VCC ≤ 3.6 V; IOH = −100 A VCC − 0.2 VCC = 1.65 V; IOH = −6 mA 1.25 VCC = 2.3 V; IOH = −6 mA 2.0 VCC = 2.3 V; IOH = −12 mA 1.8 VCC = 2.3 V; IOH = −18 mA 1.7 VCC = 2.7 V; IOH = −12 mA 2.2 VCC = 3.0 V; IOH = −18 mA 2.4 VCC = 3.0 V; IOH = −24 mA 2.2 Unit V V 1.65 V ≤ VCC ≤ 3.6 V; IOL = 100 A 0.2 VCC = 1.65 V; IOL = 6 mA 0.3 VCC = 2.3 V; IOL = 12 mA 0.4 VCC = 2.3 V; IOL = 18 mA 0.6 VCC = 2.7 V; IOL = 12 mA 0.4 VCC = 3.0 V; IOL = 18 mA 0.4 VCC = 3.0 V; IOL = 24 mA 0.55 V II Input Leakage Current 1.65 V ≤ VCC ≤ 3.6 V; 0 V ≤ VI ≤ 3.6 V ±5.0 A IOZ 3−State Output Current 1.65 V ≤ VCC ≤ 3.6 V; 0 V ≤ VO ≤ 3.6 V; VI = VIH or VIL ±10 A IOFF Power−Off Leakage Current VCC = 0 V; VI or VO = 3.6 V 10 A ICC Quiescent Supply Current (Note 3) 1.65 V ≤ VCC ≤ 3.6 V; VI = GND or VCC 20 A 1.65 V ≤ VCC ≤ 3.6 V; 3.6 V ≤ VI, VO ≤ 3.6 V ±20 A ICC Increase in ICC per Input 2.7 V < VCC ≤ 3.6 V; VIH = VCC − 0.6 V 750 A 2. These values of VI are used to test DC electrical characteristics only. 3. Outputs disabled or 3−state only. http://onsemi.com 4 74VCX16373 AC CHARACTERISTICS (Note 4; tR = tF = 2.0 ns; CL = 30 pF; RL = 500 ) TA = −40°C to +85°C VCC = 3.0 V to 3.6 V Symbol Parameter VCC = 2.3 V to 2.7 V VCC = 1.65 V to 1.95 V Waveform Min Max Min Max Min Max Unit tPLH tPHL Propagation Delay Dn−to−On 1 0.8 0.8 3.0 3.0 1.0 1.0 3.4 3.4 1.5 1.5 6.8 6.8 ns tPLH tPHL Propagation Delay LE−to−On 1 0.8 0.8 3.0 3.0 1.0 1.0 3.9 3.9 1.5 1.5 7.8 7.8 ns tPZH tPZL Output Enable Time to High and Low Level 2 0.8 0.8 3.5 3.5 1.0 1.0 4.6 4.6 1.5 1.5 9.2 9.2 ns tPHZ tPLZ Output Disable Time From High and Low Level 2 0.8 0.8 3.5 3.5 1.0 1.0 3.8 3.8 1.5 1.5 6.8 6.8 ns ts Setup Time, High or Low Dn−to−LE 3 1.5 1.5 2.5 ns th Hold Time, High or Low Dn−to−LE 3 1.0 1.0 1.0 ns tw LE Pulse Width, High 3 1.5 1.5 4.0 ns tOSHL tOSLH Output−to−Output Skew (Note 5) 0.5 0.5 0.5 0.5 0.75 0.75 ns 4. For CL = 50 pF, add approximately 300 ps to the AC maximum specification. 5. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (tOSHL) or LOW−to−HIGH (tOSLH); parameter guaranteed by design. AC CHARACTERISTICS (tR = tF = 2.0 ns; CL = 50 pF; RL = 500 ) TA = −40°C to +85°C VCC = 3.0 V to 3.6 V Symbol Parameter Waveform Min Max VCC = 2.7 V Min Max Unit tPLH tPHL Propagation Delay Dn−to−On 4 1.0 1.0 3.6 3.6 4.3 4.3 ns tPLH tPHL Propagation Delay LE−to−On 4 1.0 1.0 3.9 3.9 4.6 4.6 ns tPZH tPZL Output Enable Time to High and Low Level 5 1.0 1.0 4.7 4.7 5.7 5.7 ns tPHZ tPLZ Output Disable Time From High and Low Level 5 1.0 1.0 4.1 4.1 4.5 4.5 ns tOSHL tOSLH Output−to−Output Skew (Note 6) 0.5 0.5 0.5 0.5 ns 6. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH−to−LOW (tOSHL) or LOW−to−HIGH (tOSLH); parameter guaranteed by design. http://onsemi.com 5 74VCX16373 DYNAMIC SWITCHING CHARACTERISTICS TA = +25°C Symbol VOLP VOLV VOHV Condition Typ Unit VCC = 1.8 V, CL = 30 pF, VIH = VCC, VIL = 0 V 0.25 V VCC = 2.5 V, CL = 30 pF, VIH = VCC, VIL = 0 V 0.6 VCC = 3.3 V, CL = 30 pF, VIH = VCC, VIL = 0 V 0.8 VCC = 1.8 V, CL = 30 pF, VIH = VCC, VIL = 0 V −0.25 VCC = 2.5 V, CL = 30 pF, VIH = VCC, VIL = 0 V −0.6 VCC = 3.3 V, CL = 30 pF, VIH = VCC, VIL = 0 V −0.8 VCC = 1.8 V, CL = 30 pF, VIH = VCC, VIL = 0 V 1.5 VCC = 2.5 V, CL = 30 pF, VIH = VCC, VIL = 0 V 1.9 VCC = 3.3 V, CL = 30 pF, VIH = VCC, VIL = 0 V 2.2 Characteristic Dynamic LOW Peak Voltage ( (Note 7)) Dynamic LOW Valley Voltage (N (Note 7)) Dynamic HIGH Valley Voltage (N (Note 8)) V V 7. Number of outputs defined as “n”. Measured with “n−1” outputs switching from HIGH−to−LOW or LOW−to−HIGH. The remaining output is measured in the LOW state. 8. Number of outputs defined as “n”. Measured with “n−1” outputs switching from HIGH−to−LOW or LOW−to−HIGH. The remaining output is measured in the HIGH state. CAPACITIVE CHARACTERISTICS Condition Typical Unit CIN Symbol Input Capacitance Parameter Note 9 6 pF COUT Output Capacitance Note 9 7 pF CPD Power Dissipation Capacitance Note 9, 10 MHz 20 pF 9. VCC = 1.8 V, 2.5 V or 3.3 V; VI = 0 V or VCC. VIH Dn Vm Vm 0V tPLH tPHL VOH On Vm Vm VOL WAVEFORM 1 − PROPAGATION DELAYS tR = tF = 2.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns Figure 4. AC Waveforms http://onsemi.com 6 74VCX16373 VIH Vm OEn VIH Dn Vm Vm Vm 0V tPZH On 0V ts tPHZ th VIH VOH Vy LEn Vm tw Vm Vm ≈ 0V tPZL On 0V tPLH, tPHL tPLZ VOH ≈ VCC On Vm Vm VOL Vx VOL WAVEFORM 3 − LE to On PROPAGATION DELAYS, LE MINIMUM PULSE WIDTH, Dn to LE SETUP AND HOLD TIMES tR = tF = 2.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns except when noted WAVEFORM 2 − OUTPUT ENABLE AND DISABLE TIMES tR = tF = 2.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns Figure 5. AC Waveforms Table 1. AC WAVEFORMS VCC Symbol 3.3 V ± 0.3 V 2.5 V ± 0.2 V 1.8 V ± 0.15 V VIH 2.7 V VCC VCC Vm 1.5 V VCC/2 VCC/2 Vx VOL + 0.3 V VOL + 0.15 V VOL + 0.15 V Vy VOH − 0.3 V VOH − 0.15 V VOH − 0.15 V VCC PULSE GENERATOR RL DUT RT CL RL Figure 6. Test Circuit Table 2. TEST CIRCUIT TEST SWITCH tPLH, tPHL Open tPZL, tPLZ 6 V at VCC = 3.3 ± 0.3 V; VCC × 2 at VCC = 2.5 ± 0.2 V; 1.8 ± 0.15 V tPZH, tPHZ GND CL = 30 pF or equivalent (Includes jig and probe capacitance) RL = 500 or equivalent RT = ZOUT of pulse generator (typically 50 ) http://onsemi.com 7 6V or VCC × 2 OPEN GND 74VCX16373 VIH Vm Dn Vm 0V tPLH tPHL VOH On Vm Vm VOL WAVEFORM 4 − PROPAGATION DELAYS tR = tF = 2.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns Figure 7. AC Waveforms VIH Dn Vm Vm OEn VIH Vm Vm 0V On 0V ts tPHZ tPZH th VIH VOH Vy LEn Vm tw Vm ≈ 0V Vm 0V tPLH, tPHL tPZL On tPLZ ≈ VCC VOH On Vm Vm VOL Vx VOL WAVEFORM 5 − OUTPUT ENABLE AND DISABLE TIMES tR = tF = 2.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns WAVEFORM 6 − LE to On PROPAGATION DELAYS, LE MINIMUM PULSE WIDTH, Dn to LE SETUP AND HOLD TIMES tR = tF = 2.0n s, 10% to 90%; f = 1 MHz; tW = 500 ns except when noted Figure 8. AC Waveforms Table 3. AC WAVEFORMS VCC Symbol 3.3 V ± 0.3 V 2.7 V VIH 2.7 V 2.7 V Vm 1.5 V 1.5 V Vx VOL + 0.3 V VOL + 0.3 V Vy VOH − 0.3 V VOH − 0.3 V http://onsemi.com 8 74VCX16373 VCC PULSE GENERATOR RL DUT RT CL RL Figure 9. Test Circuit Table 4. TEST CIRCUIT TEST SWITCH tPLH, tPHL Open tPZL, tPLZ 6 V at VCC = 3.3 ± 0.3 V; VCC × 2 at VCC = 2.5 ± 0.2 V; 1.8 ± 0.15 V tPZH, tPHZ GND CL = 50 pF or equivalent (Includes jig and probe capacitance) RL = 500 or equivalent RT = ZOUT of pulse generator (typically 50) http://onsemi.com 9 6V or VCC × 2 OPEN GND 74VCX16373 PACKAGE DIMENSIONS TSSOP DT SUFFIX CASE 1201−01 ISSUE A 48X ÇÇÇ ÉÉÉ ÇÇÇ ÉÉÉ ÇÇÇ K REF 0.12 (0.005) M T U S V S T U S J J1 48 25 0.254 (0.010) M SECTION N−N B −U− L N 1 24 A −V− PIN 1 IDENT. N F DETAIL E D 0.076 (0.003) −T− SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSIONS A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−. K K1 C M 0.25 (0.010) −W− DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 12.40 12.60 6.00 6.20 −−− 1.10 0.05 0.15 0.50 0.75 0.50 BSC 0.37 −−− 0.09 0.20 0.09 0.16 0.17 0.27 0.17 0.23 7.95 8.25 0 8 INCHES MIN MAX 0.488 0.496 0.236 0.244 −−− 0.043 0.002 0.006 0.020 0.030 0.0197 BSC 0.015 −−− 0.004 0.008 0.004 0.006 0.007 0.011 0.007 0.009 0.313 0.325 0 8 DETAIL E G H ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 61312, Phoenix, Arizona 85082−1312 USA Phone: 480−829−7710 or 800−344−3860 Toll Free USA/Canada Fax: 480−829−7709 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder Japan: ON Semiconductor, Japan Customer Focus Center 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 Phone: 81−3−5773−3850 http://onsemi.com 10 For additional information, please contact your local Sales Representative. 74VCX16373/D