ONSEMI NB4N316MDTR2G

NB4N316M
3.3 V AnyLevelt Receiver
to CML Driver/Translator
with Input Hysteresis
2.0 GHz Clock / 2.5 Gb/s Data
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The NB4N316M is a differential Clock or Data receiver and will
accept AnyLevelt input signals: LVPECL, CML, LVCMOS,
LVTTL, or LVDS. These signals will be translated to CML, operating
up to 2.0 GHz or 2.5 Gb/s, respectively. As such, the NB4N316M is
ideal for SONET, GigE, Fiber Channel, Backplane and other Clock or
Data distribution applications. The CML outputs are 16 mA open
collector (see Figure 18) which requires resistor (RL) load path to VTT
termination voltage (see Figure 19). The open collector CML outputs
must be terminated to VTT at power up. The differential outputs
produce Current–Mode Logic (CML) compatible levels when the
receiver is loaded with 50 W or 25 W loads connected to 1.8 V, 2.5 V
or 3.3 V supplies. This simplifies device interface by eliminating a
need for coupling capacitors.
The NB4N316M features an input threshold hysteresis of
approximately 25 mV, providing increased noise immunity and stability.
The device is offered in a small 8−pin TSSOP package (MSOP−8
compatible). Application notes, models, and support documentation
are available at www.onsemi.com.
MARKING
DIAGRAM*
8
1
TSSOP−8
DT SUFFIX
CASE 948R
A
L
Y
W
G
8
1
E316
ALYWG
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
Features
•
•
•
•
•
•
•
•
•
•
•
•
Maximum Input Clock Frequency > 2.0 GHz
Maximum Input Data Rate > 2.5 Gb/s
Typically 1 ps of RMS Clock Jitter
Typically 10 ps of Data Dependent Jitter
550 ps Typical Propagation Delay
150 ps Typical Rise and Fall Times
Differential CML Outputs
25 mV of Receiver Input Threshold Hysteresis
Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V and
VTT = 1.8 V to 3.6 V
Functionally Compatible with Existing 2.5 V / 3.3 V LVEL,
LVEP, EP, and SG Devices
−40°C to +85°C Ambient Operating Temperature
These are Pb−Free Devices*
D
Q
D
Q
Figure 1. Functional Block Diagram
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 3
1
Publication Order Number:
NB4N316M/D
NB4N316M
NC
1
8
VCC
D
2
7
Q
D
3
6
Q
VBB
4
5
VEE
Figure 2. Pinout (Top View) and Logic Diagram
Table 1. Pin Description
Pin
Name
I/O
Description
1
NC
−
2
D
ECL, CML, LVCMOS, LVDS,
LVTTL Input
Noninverted Differential Input. (Note 1)
3
D
ECL, CML, LVCMOS, LVDS,
LVTTL Input
Inverted Differential Input. (Note 1)
4
VBB
−
Internally Generated Reference Voltage Supply.
5
VEE
−
Negative Supply Voltage.
6
Q
CML Output
Inverted Differential Output. Typically Terminated with 50 W Resistor to VTT.
7
Q
CML Output
Noninverted Differential Output. Typically Terminated with 50 W Resistor to VTT.
8
VCC
−
No Connect.
Positive Supply Voltage.
1. In the differential configuration if no signal is applied on D/D input, then the device will be susceptible to self−oscillation.
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NB4N316M
Table 2. ATTRIBUTES
Characteristics
Value
ESD Protection
Human Body Model
Machine Model
Moisture Sensitivity (Note 1)
8−TSSOP
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
> 1000 V
> 70 V
Level 3
UL 94 V−0 @ 0.125 in
225
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Table 3. MAXIMUM RATINGS
Symbol
Rating
Unit
VCC
Positive Power Supply
Parameter
VEE = −0.5 V
Condition 1
Condition 2
4
V
VEE
Negative Power Supply
VCC = +0.5 V
−4
V
VI
Positive Input
Negative Input
VEE = 0 V
VCC = 0 V
4
−4
V
V
VO
Output Voltage
VEE + 600
VCC + 400
mV
mV
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
(Note 2)
0 lfpm
500 lfpm
TSSOP−8
TSSOP−8
190
130
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
1S2P (Note 2)
TSSOP−8
41 to 44
°C/W
Tsol
Wave Solder
< 3 Sec @ 260°C
265
°C
VI = VCC +0.4 V
VI = VEE –0.4 V
Minimum
Maximum
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. JEDEC standard multilayer board − 1S2P (1 signal, 2 power) with 8 filled thermal vias under exposed pad.
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NB4N316M
Table 4. DC CHARACTERISTICS, CLOCK Inputs, CML Outputs VCC = 3.0 V to 3.6 V, VEE = 0 V, TA = −40°C to +85°C
Symbol
ICC
Characteristic
Min
Power Supply Current (Inputs and Outputs Open)
Typ
Max
Unit
20
30
mA
RL = 50 W, VTT = 3.6 V to 2.5 V
VOH
Output HIGH Voltage (Note 3)
VTT − 60
VTT − 10
VTT
mV
VOL
Output LOW Voltage (Note 3)
VTT − 1100
VTT − 800
VTT − 640
mV
|VOD|
Differential Output Voltage Magnitude
640
780
1000
mV
RL = 25 W, VTT = 3.6 V to 2.5 V $5%
VOH
Output HIGH Voltage (Note 3)
VTT − 60
VTT − 10
VTT
mV
VOL
Output LOW Voltage (Note 3)
VTT − 550
VTT − 400
VTT − 320
mV
|VOD|
Differential Output Voltage Magnitude
320
390
500
mV
RL = 50 W, VTT = 1.8 V $5%
VOH
Output HIGH Voltage (Note 3)
VTT − 170
VTT − 10
VTT
mV
VOL
Output LOW Voltage (Note 3)
VTT − 1100
VTT − 800
VTT − 640
mV
|VOD|
Differential Output Voltage Magnitude
570
780
1000
mV
RL = 25 W, VTT = 1.8 V $5%
VOH
Output HIGH Voltage (Note 3)
VTT − 85
VTT − 10
VTT
mV
VOL
Output LOW Voltage (Note 3)
VTT − 500
VTT − 400
VTT − 320
mV
|VOD|
Differential Output Voltage Magnitude
285
390
500
mV
VEE
VCC
mV
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (Figures 14 and 16)
Vth
Input Threshold Reference Voltage Range (Note 5)
VIH
Single−ended Input HIGH Voltage
Vth + 100
VCC + 400
mV
VIL
Single−ended Input LOW Voltage
VEE − 400
Vth − 100
mV
VBB
Internally Generated Reference Voltage Supply (Loaded with −100 mA)
VCC − 1300
mV
VCC − 1500
VCC − 1400
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Figures 15 and 17)
VIHD
Differential Input HIGH Voltage
VEE
VCC + 400
mV
VILD
Differential Input LOW Voltage
VEE − 400
VCC − 100
mV
VCMR
Input Common Mode Range (Differential Configuration)
VEE
VCC
mV
VID(HYST)
Differential Input Voltage Hysteresis (VIHD − VILD)
|VID|
Differential Input Voltage Magnitude (|VIHD − VILD|) (Note 7)
CIN
Input Capacitance (Note 7)
25
100
mV
VCC − VEE
1.5
mV
pF
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. CML outputs require RL receiver termination resistors to VTT for proper operation. Outputs must be connected through RL to VTT at power
up. The output parameters vary 1:1 with VTT. VTT = 1.71 V to 3.6 V.
4. Input parameters vary 1:1 with VCC.
5. Vth is applied to the complementary input when operating in single−ended mode.
6. VCMR (MIN) varies 1:1 with VEE, VCMR max varies 1:1 with VCC.
7. Parameter guaranteed by design and evaluation but not tested in production.
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NB4N316M
Table 5. AC CHARACTERISTICS VCC = 3.0 V to 3.6 V, VEE = 0 V; (Note 8)
−40°C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
VOUTPP
Output Voltage Amplitude (RL = 50 W)
fin ≤ 1 GHz
(See Figure 12)
fin ≤ 1.5 GHz
fin ≤ 2.0 GHz
550
400
200
660
640
400
550
400
200
660
640
400
550
400
200
660
640
400
VOUTPP
Output Voltage Amplitude (RL = 25 W)
fin ≤ 1 GHz
(See Figure 12)
fin ≤ 1.5 GHz
fin ≤ 2.0 GHz
280
280
200
370
360
300
280
280
200
370
360
400
280
280
200
370
360
400
fDATA
Maximum Operating Data Rate
1.5
2.5
1.5
2.5
1.5
2.5
tPLH,
tPHL
Propagation Delay to Output Differential
@ 0.25 GHz
350
550
750
350
550
750
350
550
750
ps
tSKEW
Duty Cycle Skew (Note 9)
Device to Device Skew (Note 13)
2
20
20
100
2
20
20
100
2
20
20
100
ps
tJITTER
RMS Random Clock Jitter RL = 50 W and
RL = 25 W (Note 11)
fin = 750 MHz
fin = 1.5 GHz
fin = 2.0 GHz
Peak−to−Peak Data Dependent Jitter RL = 50 W
fDATA = 1.5 Gb/s
(Note 12)
fDATA = 2.5 Gb/s
Peak−to−Peak Data Dependent Jitter RL = 25 W
fDATA = 1.5 Gb/s
(Note 12)
fDATA = 2.5 Gb/s
1
1
1
3
3
3
1
1
1
3
3
3
1
1
1
3
3
3
15
20
55
85
15
20
55
85
15
20
55
85
5
10
35
35
5
10
35
35
5
10
35
35
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 10)
tr
tf
Output Rise/Fall Times @ 0.25 GHz
(20% − 80%)
200
Q, Q
200
150
300
mV
mV
Gb/s
200
150
300
ps
mV
150
300
ps
OUTPUT VOLTAGE AMPLITUDE (mV)
OUTPUT VOLTAGE AMPLITUDE (mV)
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
8. Measured by forcing VINPP (MIN) from a 50% duty cycle clock source. All output loaded with an external RL = 50 W and RL = 25 W to VTT.
Outputs must be connected through RL to VTT at power up. Input edge rates 150 ps (20% − 80%).
9. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ @ 0.25 GHz.
10. VINPP (MAX) cannot exceed VCC − VEE. Input voltage swing is a single−ended measurement operating in differential mode.
11. Additive RMS jitter with 50% duty cycle clock signal.
12. Additive peak−to−peak data dependent jitter with input NRZ data signal (PRBS 223−1).
13. Device to device skew is measured between outputs under identical transition @ 0.5 GHz.
800
0.8
700
RL = 50 W
600
500
400
RL = 25 W
300
200
100
0
0.5
0.75
1
1.25
1.5
1.75
2
RL = 50 W
0.7
0.6
0.5
0.4
RL = 25 W
0.3
0.2
0.1
0
0.5
0.75
1
1.25
1.5
1.75
INPUT CLOCK FREQUENCY (GHz)
INPUT CLOCK FREQUENCY (GHz)
(VCC − VEE = 3.3 V VTT = 3.3 V @ 255C Vin = 100 mV)
(VCC − VEE = 3.0 V VTT = 1.71 V @255C Vin = 100 mV)
2
Figure 3. Output Voltage Amplitude (VOUTPP) versus Input Clock Frequency (fIN) at Ambient Temperature (Typical)
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NB4N316M
NB4N316M
80
35
70
30
25
50
TIME (ps)
TIME (ps)
60
40
30
−40°C
15
85°C
10
20
5
10
0
0.25
85°C
0.5
0.75
25°C
1
1.25
1.5
1.75
−40°C
0
0.25
2
0.5
0.75
1
25°C
1.25
1.5
1.75
2
INPUT CLOCK FREQUENCY (GHz)
INPUT CLOCK FREQUENCY (GHz)
Figure 4. Data Dependent Jitter vs. Frequency
and Temperature (VCC − VEE = 3.3 V; VTT = 3.3 V
@ 255C; VIN = 100 mV; PRBS 223−1; RL = 50 W)
Figure 5. Data Dependent Jitter vs. Frequency
and Temperature (VCC − VEE = 3.3 V; VTT = 3.3 V
@ 255C; VIN = 100 mV; PRBS 223−1; RL = 25 W)
600
550
600
tPD
TIME (ps)
500
450
400
350
450
400
350
25
300
VEE − 0.5 V
85
V CC * V EE
TEMPERATURE (°C)
Figure 7. Typical Propagation Delay vs. Input
Offset Voltage (VCC − VEE = 3.3 V; VTT = 3.3 V
@ 255C; Vin = 100 mV RL = 50 W)
35
30
25
ICC
20
15
10
5
0
−40
VCC + 0.5 V
2
INPUT OFFSET VOLTAGE (V)
Figure 6. Typical Propagation Delay vs.
Temperature (VCC − VEE = 3.3 V; VTT = 3.3 V
@ 255C; Vin = 100 mV; RL = 50 W)
CURRENT (mA)
300
−40
tPD
550
500
TIME (ps)
20
25
TEMPERATURE (°C)
Figure 8. Supply Current vs. Temperature
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6
85
VOLTAGE (100 mV/div)
VOLTAGE (200 mV/div)
NB4N316M
DDJ = 5 ps
DDJ = 3 ps
TIME (266.8 ps/div)
TIME (266.8 ps/div)
VOLTAGE (100 mV/div)
VOLTAGE (200 mV/div)
Figure 9. Typical Differential Output Waveform at 750 Mb/s
(RL = 50 W Left Plot, RL = 25 W Right Plot, Vin = 100 mV, System DDJ = 24 ps)
DDJ = 12 ps
TIME (133.2 ps/div)
DDJ = 5 ps
TIME (133.2 ps/div)
VOLTAGE (100 mV/div)
VOLTAGE (200 mV/div)
Figure 10. Typical Differential Output Waveform 1.5 Gb/s
(RL = 50 W Left Plot, RL = 25 W Right Plot, Vin = 100 mV, System DDJ = 25 ps)
DDJ = 20 ps
TIME (80 ps/div)
DDJ = 7 ps
TIME (80 ps/div)
Figure 11. Typical Differential Output Waveform 2.5 Gb/s
(RL = 50 W Left Plot, RL = 25 W Right Plot, Vin = 100 mV, System DDJ = 24 ps)
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NB4N316M
D
VINPP = VIH(D) − VIL(D)
D
Q
VOUTPP = VOH(Q) − VOL(Q)
Q
tPHL
tPLH
Figure 12. AC Reference Measurement
Q
Zo = 50 W
D
Receiver
Device
Driver
Device
Q
D
Zo = 50 W
50 W
50 W
VTT
VTT = VCC − 2.0 V
Figure 13. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
D
D
D
D
Vth
Vth
Figure 14. Differential Input Driven
Single−Ended
VCC
Vthmax
Vthmin
GND
VCC
VIHmax
VILmax
D
Vth
Figure 15. Differential Inputs Driven
Differentially
VIHCLKmax
VCMmax
D
VIH
Vth
VIL
VCMR
D
VIHmin
VILmin
VCMmax
GND
Figure 16. Vth Diagram
VILCLKmax
VID = VIHD − VILD
VIHDtyp
VILDtyp
VIHDmin
VILDmin
Figure 17. VCMR Diagram
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NB4N316M
VCC
Input
ESD
D
1.25 kW
RC
1.25 kW
RC
1.25 kW
Input
ESD
1.25 kW
D
Q
Q
IN
IN
Input
ESD
Input
ESD
Internal
Current Source
16 mA
Current Source
VEE
Output
VEE
Input
Figure 18. CML Input and Output Structure
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NB4N316M
VTTA = VCCA
VCCA = 1.8 V 2.5 V or 3.3 V
VCCA = 3.3 V
Z = 50 W
VCCB = 3.3 V
NB4N316M
50 W
Receiver
A
Z = 50 W
NB4N316M
VEE = 0 V
50 W
VTTB = VCCB
50 W
VTTB = VCCB
50 W
Z = 50 W
50 W
50 W
VCCB = 1.8 V 2.5 V or 3.3 V
Z = 50 W
Receiver
B
VEE = 0 V
VTTC = VCCC
VCCC = 1.8 V 2.5 V or 3.3 V
VCCC = 3.3 V
NB4N316M
75 W
Z = 75 W
75 W
Receiver
C
Z = 75 W
VTTD = VCCD
VEE = 0 V
VCCD = 3.3 V
Z = 100 W
NB4N316M
100 W
100 W
VCCD = 1.8 V 2.5 V or 3.3 V
Z = 100 W
Receiver
D
VEE = 0 V
Figure 19. Typical Examples of the Application Interface
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NB4N316M
ORDERING INFORMATION
Package
Shipping †
NB4N316MDTG
TSSOP−8
(Pb−Free)
100 Units / Rail
NB4N316MDTR2G
TSSOP−8
(Pb−Free)
2500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1672/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
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NB4N316M
PACKAGE DIMENSIONS
TSSOP−8
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948R−02
ISSUE A
8x
0.15 (0.006) T U
0.10 (0.004)
S
2X
L/2
L
8
5
1
PIN 1
IDENT
0.15 (0.006) T U
K REF
S
M
T U
V
S
0.25 (0.010)
B
−U−
4
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
S
M
A
−V−
F
DETAIL E
C
0.10 (0.004)
−T− SEATING
PLANE
D
−W−
G
DETAIL E
DIM
A
B
C
D
F
G
K
L
M
MILLIMETERS
MIN
MAX
2.90
3.10
2.90
3.10
0.80
1.10
0.05
0.15
0.40
0.70
0.65 BSC
0.25
0.40
4.90 BSC
0_
6_
INCHES
MIN
MAX
0.114
0.122
0.114
0.122
0.031
0.043
0.002
0.006
0.016
0.028
0.026 BSC
0.010
0.016
0.193 BSC
0_
6_
AnyLevel and ECLinPS are trademarks of Semiconductor Components INdustries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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NB4N316M/D