NB7VQ58M 1.8V / 2.5V / 3.3V Differential 2:1 Clock/Data Multiplexer / Translator with CML Outputs http://onsemi.com w/ Selectable Input Equalizer MARKING DIAGRAM* Multi−Level Inputs w/ Internal Termination 16 1 Description The NB7VQ58M is a high performance differential 2−to−1 Clock or Data multiplexer with a selectable Equalizer receiver. When placed in series with a Clock /Data path operating up to 7 GHz or 10.7 Gb/s, respectively, the NB7VQ58M inputs will compensate the degraded signal transmitted across an FR4 PCB backplane or cable interconnect. Therefore, the serial data rate is increased by reducing Inter−Symbol Interference (ISI) caused by losses in copper interconnect or long cables. The EQualizer ENable pin (EQEN) allows the INn/INn inputs to either flow through or bypass the Equalizer section. Control of the Equalizer function is realized by setting EQEN; When EQEN is set Low, the INn / INn inputs bypass the Equalizer. When EQEN is set High, the INn / INn inputs flow through the Equalizer. The default state at startup is LOW. As such, the NB7VQ58M is ideal for SONET, GigE, Fiber Channel, Backplane and other Clock/Data distribution applications. The differential inputs incorporate internal 50 W termination resistors that are accessed through the VT pin. This feature allows the NB7VQ58M to accept various logic level standards, such as LVPECL, CML or LVDS. The NB7VQ58M produces minimal Clock or Data jitter operating up to 7 GHz or 10.7 Gb/s, respectively. The 16 mA differential CML outputs provide matching internal 50 W terminations and 400 mV output swings when externally terminated with a 50 W resistor to VCC. The NB7VQ58M is offered in a low profile 3mm x 3 mm 16−pin QFN package and is a member of the GigaComm™ family of high performance Clock / Data products. Application notes, models, and support documentation are available at www.onsemi.com. Features • • • • • • • August, 2009 − Rev. 0 QFN−16 MN SUFFIX CASE 485G A L Y W G NB7V Q58M ALYW G G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. SIMPLIFIED BLOCK DIAGRAM VCC EQ ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. Maximum Input Data Rate > 10.7 Gb/s Data Dependent Jitter < 15 ps Maximum Input Clock Frequency > 7 GHz Random Clock Jitter < 0.8 ps RMS Selectable Input Equalization 180 ps Typical Propagation Delay 35 ps Typical Rise and Fall Times © Semiconductor Components Industries, LLC, 2009 1 • Differential CML Outputs, 400 mV Peak−to−Peak, • • • 1 Typical Operating Range: VCC = 1.71 V to 3.6 V with GND = 0V Internal 50 W Input Termination Resistors This is a Pb−Free Device Publication Order Number: NB7VQ58M/D NB7VQ58M Exposed Pad (EP) VT0 GND GND VCC 16 15 14 NB7VQ58M 3 IN1 4 11 GND IN1 10 GND 50 W VT1 50 W 9 5 6 7 0 VT0 50 W IN0 12 Q 2 IN1 IN0 50 W 13 IN0 1 IN0 Multi−Level Inputs LVPECL, LVDS, CML Q SEL 2:1 Mux 1 VCC IN1 8 0 2:1 Mux EQ 75 kW Q Q 1 EQEN (Equalizier Enable) VT1 SEL EQEN VCC 75 kW VCC GND Figure 1. Pin Configuration (Top View) Figure 2. Detailed Block Diagram Table 1. EQualizer ENable FUNCTION Table 2. SELect FUNCTION TRUTH TABLE EQEN Function SEL Q Q 0 INn / INn Inputs By−pass the EQualizer section L D0 D0 1 Inputs flow through the EQualizer H D1 D1 Table 3. PIN DESCRIPTION Pin Name I/O 1 IN0 LVPECL, CML, LVDS Input Noninverted Differential Input (Note 1) 2 IN0 LVPECL, CML, LVDS Input Inverted Differential Input (Note 1) 3 IN1 LVPECL, CML, LVDS Input Noninverted Differential Input (Note 1) 4 IN1 LVPECL, CML, LVDS Input Inverted Differential Input (Note 1) 5 VT1 − 6 SEL LVTTL/LVCMOS Input 7 EQEN LVCMOS Input 8 VCC − Description Internal 50 W Termination Pin for IN1/IN1 SEL Input. Low for IN0 inputs, High for IN1 inputs. (Note 1) Pin will default HIGH when left open (has internal pullup resistor) Equalizer Enable Input; pin will default LOW when left open (has internal pulldown resistor) Positive Supply Voltage (Note 2) 9 Q CML Output 10 GND − Inverted Differential Output Negative Supply Voltage 11 GND − Negative Supply Voltage 12 Q CML Output 13 VCC − Positive Supply Voltage (Note 2) 14 GND − Negative Supply Voltage 15 GND − Negative Supply Voltage 16 VT0 − Internal 50 W Termination Pin for IN0/IN0 − EP − The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die for improved heat transfer out of package. The exposed pad must be attached to a heat−sinking conduit. The pad is electrically connected to the die, and must be electrically and thermally connected to GND on the PC board. Noninverted Differential Output 1. In the differential configuration when the input termination pins (VT0, VT1) are connected to a common termination voltage or left open, and if no signal is applied on IN0/IN0, IN1/IN1 inputs, then the device will be susceptible to self−oscillation. Q/Q outputs have internal 50 W source termination resistors. 2. All VCC and GND pins must be externally connected to a power supply for proper operation. http://onsemi.com 2 NB7VQ58M Table 4. ATTRIBUTES Characteristics Value ESD Protection Human Body Model Machine Model RPU − SEL Input Pull−up Resistor 25 kW Moisture Sensitivity (Note 3) Flammability Rating > 2 kV > 200 V QFN−16 Oxygen Index: 28 to 34 Transistor Count Level 1 UL 94 V−0 @ 0.125 in 312 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 3. For additional information, see Application Note AND8003/D. Table 5. MAXIMUM RATINGS Symbol Parameter Condition 1 Condition 2 Rating Unit VCC Positive Power Supply GND = 0 V 4.0 V VIN Positive Input Voltage GND = 0 V −0.5 to VCC +0.5 V VINPP Differential Input Voltage |INn − INn| 1.89 V IOUT Output Current 34 40 mA IIN Input Current Through RT (50 W Resistor) $40 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) (Note 4) QFN−16 QFN−16 42 35 °C/W qJC Thermal Resistance (Junction−to−Case) (Note 4) QFN−16 4 °C/W Tsol Wave Solder 265 °C Continuous Surge 0 LFPM 500 LFPM Pb−Free Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 4. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad. http://onsemi.com 3 NB7VQ58M Table 6. DC CHARACTERISTICS POSITIVE CML OUTPUT (VCC = 1.71 V to 3.6 V; GND = 0 V; TA = −40°C to 85°C) (Note 5) Characteristic Symbol Min Typ Max Unit 100 150 mA POWER SUPPLY CURRENT ICC Power Supply Current (Inputs and Outputs Open) CML OUTPUTS (Note 6) VOH Output HIGH Voltage VOL Output LOW Voltage VCC = 3.3 V VCC = 2.5 V VCC = 1.8 V VCC – 30 3270 2470 1770 VCC – 5 3295 2495 1795 VCC 3300 2500 1800 mV VCC = 3.3 V VCC = 2.5 V VCC = 1.8 V VCC – 500 2800 2000 1300 VCC – 400 2900 2100 1400 VCC – 300 3000 2200 1500 mV DIFFERENTIAL INPUTS DRIVEN SINGLE−ENDED (Note 7) (Figures 6 & 8) Vth Input Threshold Reference Voltage Range (Note 8) 1050 VCC − 100 mV VIH Single−ended Input HIGH Voltage Vth + 100 VCC mV VIL Single−ended Input LOW Voltage GND Vth − 100 mV VISE Single−ended Input Voltage (VIH − VIL) 200 1200 mV DIFFERENTIAL IN0/IN0, IN1/IN1, INPUTS DRIVEN DIFFERENTIALLY (Figures 7 & 9) (Note 9) VIHD Differential Input HIGH Voltage 1100 VCC mV VILD Differential Input LOW Voltage GND VCC − 100 mV VID Differential Input Voltage (VIHD − VILD) 100 1200 mV VCMR Input Common Mode Range (Differential Configuration, Note 10) (Figure 10) 1050 VCC − 50 mV IIH Input HIGH Current (VTn Open) −150 150 mA IIL Input LOW Current (VTn Open) −150 150 mA CONTROL INPUT (SEL, EQEN) VIH Input HIGH Voltage VCC x 0.65 VCC mV VIL Input LOW Voltage GND VCC x 0.35 mV IIH Input HIGH Current −150 +150 mA IIL Input LOW Current −200 +200 mA TERMINATION RESISTORS RTIN Internal Input Termination Resistor 45 50 55 W RTOUT Internal Output Termination Resistor 45 50 55 W NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Input and output parameters vary 1:1 with VCC. 6. CML outputs loaded with 50 W to VCC for proper operation. 7. Vth, VIH, VIL and VISE parameters must be complied with simultaneously. 8. Vth is applied to the complementary input when operating in single−ended mode. 9. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously. 10. VCMR min varies 1:1 with GND, VCMR max varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 4 NB7VQ58M Table 7. AC CHARACTERISTICS (VCC = 1.71 V to 3.6 V; GND = 0 V; TA = −40°C to 85°C) (Note 11) Characteristic Symbol Min Typ 7 8 GHz 10.7 12 Gbps 25 50 MHz fin ≤ 7 GHz 200 400 mV INn/INn to Q, Q SEL to Q, Q 120 5 180 13 fMAX Maximum Input Clock Frequency VOUTPP ≥ 200 mV fDATAMAX Maximum Operating Data Rate (PRBS23) fSEL Maximum Toggle Frequency, SEL VOUTPP Output Voltage Amplitude EQEN = 0 or 1 (Note 12) (Figures 3 and 11) tPLH, tPHL Propagation Delay to Differential Outputs, @ 1 GHz, measured at differential cross−point EQEN = 0 or 1 tPLH TC Propagation Delay Temperature Coefficient tskew Device − Device skew (tpdmax – tpdmin) tDC Output Clock Duty Cycle (Reference Duty Cycle = 50%) fin v 5.0 GHz fin v 7.0 GHz tJITTER RMS Random Clock Jitter (Note 13) Peak−to−Peak Data Dependent Jitter (Note 14) fin v 7.0 GHz Max Unit 240 22 ps ns 50 45 40 50 ps 50 50 55 60 % 0.2 0.8 ps rms 10 10 ps pk−pk fin v 10.7 Gbps EQEN = 0 (v 3” FR4) EQEN = 1 (12” FR4) FN Phase Noise, fc = 1 GHz 10 kHz 100 kHz 1 MHz 10 MHz 20 MHz 40 MHz t∫FN Integrated Phase Jitter (Figure 4) fc = 1 GHz, 12 kHz − 20 MHz Offset (RMS) −135 −136 −150 −151 −151 −151 dBc 35 fs Crosstalk Induced Jitter (Adjacent Channel) (Note 15) VINPP Input Voltage Swing (Differential Configuration) (Figure 11) (Note 12) tr, tf Output Rise/Fall Times @ 1 GHz (20% − 80%) 100 Q, Q 15 Dfs/°C 35 0.7 ps RMS 1200 mV 50 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 11. Measured using a VINPPmin source, 50% duty cycle clock source. All output loading with external 50 W to VCC. Input edge rates 40 ps (20% − 80%). 12. Input and output voltage swings are single−ended measurements operating in differential mode. 13. Additive RMS jitter with 50% duty cycle clock signal. 14. Additive Peak−to−Peak data dependent jitter with input NRZ data at PRBS23 at 3 Gbps. 15. Crosstalk is measured at the output while applying two similar clock frequencies that are asynchronous with respect to each other at the inputs. −115 −120 450 −125 400 POWER (dBc) VOUTPP, OUTPUT VOLTAGE AMPLITUDE (mV) 500 350 300 −130 −135 −140 −145 250 200 −150 0 1 2 3 4 5 7 8 6 fin, CLOCK INPUT FREQUENCY (GHz) 9 10 −155 1.E+03 Figure 3. Output Voltage Amplitude (VOUTPP) vs. Input Frequency (fin) at Ambient Temperature (Typical) http://onsemi.com 5 1.E+04 1.E+05 1.E+06 1.E+07 FREQUENCY OFFSET (Hz) Figure 4. Typical Phase Noise (VCC = 1.8 V, T = 255C, fc = 1 GHz) 1.E+08 NB7VQ58M VCC INn 50 W I VTn 50 W INn Figure 5. Input Structure IN VIH IN Vth VIL IN IN Vth Figure 6. Differential Input Driven Single−Ended VCC Vthmax Figure 7. Differential Inputs Driven Differentially VIHmax VILmax IN VIH Vth VIL Vth IN VIHD VILD VIHmin Vthmin VILmin GND Figure 8. Vth Diagram VCC VIHDmax VCMRmax Figure 9. VID − Differential Inputs Driven Differentially IN VILDmax IN VCMR IN VCMRmin GND VID = |VIHD(IN) − VILD(IN)| IN VIHDtyp VID = VIHD − VILD VINPP = VIH(IN) − VIL(IN) Q VILDtyp Q VIHDmin VOUTPP = VOH(Q) − VOL(Q) tPHL tPLH VILDmin Figure 10. VCMR Diagram Figure 11. AC Reference Measurement http://onsemi.com 6 NB7VQ58M VCC VT Driver FR4 − 12 Inch Backplane Q NB7VQ58M EQualizer EQEN = 1 IN IN Q DJ1 DJ2 DJ3 Figure 12. Typical NB7VQ58M Equalizer Application and Interconnect with PRBS23 pattern at 6.5 Gbps, EQEN = 1 http://onsemi.com 7 NB7VQ58M VCC VCC VCC NB7VQ58M INx ZO = 50 W 50 W LVDS Driver VT = VCC − 2 V ZO = 50 W NB7VQ58M INx ZO = 50 W 50 W LVPECL Driver VCC VT = Open ZO = 50 W 50 W 50 W INx INx GND GND GND Figure 13. LVPECL Interface VCC Figure 14. LVDS Interface VCC VCC ZO = 50 W CML Driver GND NB7VQ58M INx ZO = 50 W Differential Driver 50 W 50 W VT = VREFAC* ZO = 50 W INx GND NB7VQ58M INx ZO = 50 W 50 W VT = VCC VCC 50 W INx GND GND GND Figure 16. Capacitor−Coupled Differential Interface (VT Connected to External VREFAC) Figure 15. Standard 50 W Load CML Interface *VREFAC Bypassed to Ground with 0.01 mF Capacitor NB7VQ58M Receiver VCC VCC (Receiver) 50 W 50 W Q 50 W 50 W Q 16 mA (see Application Note AND8173) GND Figure 17. Typical CML Output Structure and Termination ORDERING INFORMATION Package Shipping† NB7VQ58MMNG QFN−16 (Pb−Free) 123 Units / Rail NB7VQ58MMNHTBG QFN−16 (Pb−Free) 100 / Tape & Reel NB7VQ58MMNTXG QFN−16 (Pb−Free) 3000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 8 NB7VQ58M PACKAGE DIMENSIONS 16 PIN QFN CASE 485G−01 ISSUE D D ÇÇÇ ÇÇÇ L1 DETAIL A PIN 1 LOCATION ALTERNATE TERMINAL CONSTRUCTIONS E ÉÉ ÉÉ EXPOSED Cu 0.15 C TOP VIEW 0.15 C DETAIL B 0.10 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM MINIMUM SPACING BETWEEN LEAD TIP AND FLAG L L A B ÉÉ ÉÉ ÇÇ A3 MOLD CMPD A1 DIM A A1 A3 b D D2 E E2 e K L L1 DETAIL B (A3) ALTERNATE CONSTRUCTIONS A 16 X SEATING PLANE 0.08 C SIDE VIEW 16X L A1 5 NOTE 5 8 4 16X 0.575 0.022 e EXPOSED PAD 3.25 0.128 0.30 0.012 EXPOSED PAD 9 E2 K 12 1 16 16X 1.50 0.059 3.25 0.128 e 13 b 0.10 C A B 0.05 C SOLDERING FOOTPRINT* C D2 DETAIL A MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.65 1.85 3.00 BSC 1.65 1.85 0.50 BSC 0.18 TYP 0.30 0.50 0.00 0.15 BOTTOM VIEW 0.50 0.02 NOTE 3 0.30 0.012 SCALE 10:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. GigaComm is a trademark of Semiconductor Component Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. 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SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 http://onsemi.com 9 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NB7VQ58M/D