MC74LVX259 8-Bit Addressable Latch/1-of-8 Decoder CMOS Logic Level Shifter with LSTTL–Compatible Inputs The MC74LVX259 is an 8–bit Addressable Latch fabricated with silicon gate CMOS technology. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The LVX259 is designed for general purpose storage applications in digital systems. The device has four modes of operation as shown in the mode selection table.. In the addressable latch mode, the data on Data In is written into the addressed latch. The addressed latch follows the data input with all non–addressed latches remaining in their previous states. In the memory mode, all latches remain in their previous state and are unaffected by the Data or Address inputs. In the one–of–eight decoding or demultiplexing mode, the addressed output follows the state of Data In with all other outputs in the LOW state. In the Reset mode, all outputs are LOW and unaffected by the address and data inputs. When operating the LVX259 as an addressable latch, changing more than one bit of the address could impose a transient wrong address. Therefore, this should only be done while in the memory mode. The MC74LVX259 input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage. This allows the MC74LVX259 to be used to interface 5 V circuits to 3 V circuits. • • • • • • • • • High Speed: tPD = 7.0 ns (Typ) at VCC = 3.3 V Low Power Dissipation: ICC = 2 µA (Max) at TA = 25°C High Noise Immunity: VNIH = VNIL = 28% VCC CMOS–Compatible Outputs: VOH > 0.8 VCC; VOL < 0.1 VCC @Load Power Down Protection Provided on Inputs and Outputs Balanced Propagation Delays Pin and Function Compatible with Other Standard Logic Families Latchup Performance Exceeds 300 mA ESD Performance: HBM > 2000 V; Machine Model > 200 V Semiconductor Components Industries, LLC, 2001 April, 2001 – Rev. 1 1 http://onsemi.com MARKING DIAGRAMS 16 9 LVX259 AWLYYWW SOIC–16 D SUFFIX CASE 751B 1 8 16 9 LVX 259 TSSOP–16 DT SUFFIX CASE 948F AWLYWW 1 8 16 SOIC EIAJ–16 M SUFFIX CASE 966 9 LVX259 ALYW 1 8 A = Assembly Location WL or L = Wafer Lot YY or Y = Year WW or W = Work Week ORDERING INFORMATION Device Package Shipping MC74LVX259D SO–16 48 Units/Rail MC74LVX259DR2 SO–16 2500 Units/Reel MC74LVX259DT TSSOP–16 96 Units/Rail MC74LVX259DTR2 TSSOP–16 2000 Units/Reel MC74LVX259M SO EIAJ–16 MC74LVX259MEL SO EIAJ–16 2000 Units/Reel 48 Units/Rail Publication Order Number: MC74LVX259/D MC74LVX259 A0 1 16 4 VCC A0 A1 2 15 RESET A2 3 14 ENABLE ADDRESS INPUTS A1 4 13 DATA IN Q1 5 12 Q7 Q2 6 11 Q6 Q3 7 10 Q5 8 GND 9 Q0 Q1 2 6 Q2 7 9 10 Q3 Q4 Q5 13 DATA IN 11 12 14 ENABLE Figure 1. Pin Assignment A0 1 A1 2 A2 3 4 0 2 5 1 4 6 2 7 3 8 4 13 ID 14 EN 6 15 R 7 Q6 Q7 Figure 2. Logic Diagram BIN/OCT 1 NONINVERTING OUTPUTS PIN 16 = VCC PIN 8 = GND 15 RESET Q4 5 3 A2 Q0 1 10 5 11 12 A0 1 Q1 A1 2 Q2 A2 3 Q0 DMUX 0 0 0 G 7 2 1 2 Q3 3 Q4 4 13 Q5 ID 14 Q6 15 Q7 5 EN 6 R 7 4 Q0 5 Q1 6 Q2 7 Q3 8 Q4 10 Q5 11 Q6 12 Q7 Figure 3. IEC Logic Symbol MODE SELECTION TABLE Enable Reset LATCH SELECTION TABLE Mode Address Inputs Latch Addressed Addressable Latch C B A H Memory L L L Q0 L 8–Line Demultiplexer L L H Q1 L Reset L H L Q2 L H H Q3 H L L Q4 H L H Q5 H H L Q6 H H H Q7 L H H L H http://onsemi.com 2 MC74LVX259 DATA INPUT 13 D D D D 4 5 6 7 Q0 Q1 Q2 Q3 A0 ADDRESS INPUTS 3 TO 8 DECODER A1 D 9 Q4 A2 D ENABLE Q5 14 D D RESET 10 15 Figure 4. Expanded Logic Diagram http://onsemi.com 3 11 12 Q6 Q7 MC74LVX259 MAXIMUM RATINGS (Note 1.) Value Unit VCC Symbol Positive DC Supply Voltage Parameter –0.5 to +7.0 V VIN Digital Input Voltage –0.5 to +7.0 V VOUT DC Output Voltage –0.5 to VCC +0.5 V IIK Input Diode Current –20 mA IOK Output Diode Current 20 mA IOUT DC Output Current, per Pin 25 mA ICC DC Supply Current, VCC and GND Pins 75 mA PD Power Dissipation in Still Air 200 180 mW TSTG Storage Temperature Range –65 to +150 °C VESD ESD Withstand Voltage Human Body Model (Note 2.) Machine Model (Note 3.) Charged Device Model (Note 4.) >2000 >200 >2000 V ILATCH–UP Latch–Up Performance Above VCC and Below GND at 125°C (Note 5.) 300 mA JA Thermal Resistance, Junction to Ambient 143 164 °C/W SOIC Package TSSOP SOIC Package TSSOP 1. Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. 2. Tested to EIA/JESD22–A114–A 3. Tested to EIA/JESD22–A115–A 4. Tested to JESD22–C101–A 5. Tested to EIA/JESD78 RECOMMENDED OPERATING CONDITIONS Symbol Characteristics Min Max Unit 2.0 3.6 V VCC DC Supply Voltage VIN DC Input Voltage 0 5.5 V VOUT DC Output Voltage 0 VCC V TA Operating Temperature Range, all Package Types –40 85 °C tr, tf Input Rise or Fall Time 0 100 ns/V VCC = 3.3 V + 0.3 V http://onsemi.com 4 MC74LVX259 DC CHARACTERISTICS (Voltages Referenced to GND) VCC Symbol Parameter Condition (V) Min 0.75 VCC 0.7 VCC 0.7 VCC VIH Minimum High–Level Input Voltage 2.0 3.0 3.6 VIL Maximum Low–Level Input Voltage 2.0 3.0 3.6 VOH High–Level Output g V lt Voltage VOL Low–Level Output V lt Voltage –40°C ≤ TA ≤ 85°C TA = 25°C Typ Max Min Max 0.75 VCC 0.7 VCC 0.7 VCC 0.25 VCC 0.3 VCC 0.3 VCC V 0.25 VCC 0.3 VCC 0.3 VCC IOH = –50 µA 2.0 1.9 2.0 1.9 IOH = –50 µA 3.0 2.9 3.0 2.9 IOH = –4 mA 3.0 2.58 IOL = 50 µA 2.0 0.0 0.1 0.1 IOL = 50 µA 3.0 0.0 0.1 0.1 IOL = 4 mA V V 2.48 3.0 0.36 0.44 IIN Input Leakage Current VIN = 5.5 V or GND 0 to 3.6 ±0.1 ±1.0 ICC Maximum Quiescent Supply Current (per package) VIN = VCC or GND 3.6 1.0 Unit 1.0 V µA µA 2.0 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ ÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎ AC ELECTRICAL CHARACTERISTICS Input tr = tf = 3.0 ns –40°C ≤ TA ≤ 85°C TA = 25°C Symbol tPLH, tPHL tPLH, tPHL tPLH, tPHL tPHL CIN Parameter Test Conditions Min Typ Max Min Max Unit ns Maximum Propagation Delay, Data to Output (Figures 5 and 9) VCC = 2.7 V CL = 15pF CL = 50pF 6.3 9.0 9.0 14.0 1.0 1.0 12.0 15.0 VCC = 3.3 V ± 0.3 V CL = 15pF CL = 50pF 5.6 8.0 8.0 12.0 1.0 1.0 11.0 14.0 Maximum Propagation Delay, Address Select to Output (Figures 6 and 9) VCC = 2.7 V CL = 15pF CL = 50pF 6.3 9.0 9.0 14.0 1.0 1.0 12.0 15.0 VCC = 3.3 V ± 0.3 V CL = 15pF CL = 50pF 5.6 8.0 8.0 12.0 1.0 1.0 11.0 14.0 Maximum Propagation Delay, Enable to Output (Figures NO TAG and 9) VCC = 2.7 V CL = 15pF CL = 50pF 6.3 9.0 9.0 14.0 1.0 1.0 12.0 15.0 VCC = 3.3 V ± 0.3 V CL = 15pF CL = 50pF 5.6 8.0 9.0 12.0 1.0 1.0 11.0 14.0 Maximum Propogation Delay, Reset to Output (Figures 7 and 9) VCC = 2.7 V CL = 15pF CL = 50pF 6.3 9.0 9.0 14.0 1.0 1.0 12.0 15.0 VCC = 3.3 V ± 0.3 V CL = 15pF CL = 50pF 5.6 8.0 9.0 12.0 1.0 1.0 11.0 14.0 6 10 Maximum Input Capacitance 10 ns ns ns pF Typical @ 25°C, VCC = 3.3 V 30 CPD Power Dissipation Capacitance (Note 6.) pF 6. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no–load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC. http://onsemi.com 5 MC74LVX259 ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎ ÎÎÎÎ Î ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ Î ÎÎ ÎÎÎ Î ÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎ TIMING REQUIREMENTS Input tr = tf = 3.0 ns TA = ≤ 85°C TA = 25°C Symbol tw Parameter Minimum Pulse Width, Reset or Enable (Figure 8) tsu Minimum Setup Time, Address or Data to Enable (Figure 8) th Minimum Hold Time, Enable to Address or Data (Figure 7 or 8) tr, tf Maximum Input, Rise and Fall Times (Figure 5) Test Conditions Min VCC = 2.7 V 4.5 Typ Max Min 5.0 VCC = 3.3 V ± 0.3 V 4.5 5.0 VCC = 2.7 V 4.0 4.0 VCC = 3.3 V ± 0.3 V 3.0 3.0 VCC = 2.7 V 2.0 2.0 VCC = 3.3 V ± 0.3 V 2.0 2.0 Max Unit ns ns ns VCC = 2.7 V 400 300 VCC = 3.3 V ± 0.3 V 300 300 ns VCC DATA IN tf tr VCC 50% DATA IN GND ADDRESS SELECT VCC 50% GND GND tPLH tPHL VCC 50% GND 50% tPHL OUTPUT Q tPHL OUTPUT Q 50% Figure 5. Switching Waveform Figure 6. Switching Waveform VCC VCC GND DATA IN tw tw 50% 50% VCC RESET 50% tPHL GND tw VCC ENABLE tPHL DATA IN 50% GND GN D tPHL OUTPUT Q OUTPUT Q 50% Figure 7. Switching Waveform Figure 8. Switching Waveform TEST POINT DATA IN OR ADDRESS SELECT VCC OUTPUT 50% th(H) tsu th(H) tsu ENABLE GND DEVICE UNDER TEST CL * VCC 50% GND *Includes all probe and jig capacitance Figure 9. Switching Waveform Figure 10. Test Circuit http://onsemi.com 6 MC74LVX259 P0 K t 10 PITCHES CUMULATIVE TOLERANCE ON TAPE ±0.2 mm (±0.008”) P2 D TOP COVER TAPE E A0 SEE NOTE 7. + K0 B1 + B0 SEE NOTE 7. F P EMBOSSMENT FOR MACHINE REFERENCE ONLY INCLUDING DRAFT AND RADII CONCENTRIC AROUND B0 W + USER DIRECTION OF FEED CENTER LINES OF CAVITY D1 FOR COMPONENTS 2.0 mm × 1.2 mm AND LARGER *TOP COVER TAPE THICKNESS (t1) 0.10 mm (0.004”) MAX. R MIN. BENDING RADIUS 10° TAPE AND COMPONENTS SHALL PASS AROUND RADIUS “R” WITHOUT DAMAGE EMBOSSED CARRIER EMBOSSMENT 100 mm (3.937”) MAXIMUM COMPONENT ROTATION 1 mm MAX TYPICAL COMPONENT CAVITY CENTER LINE TAPE 1 mm (0.039”) MAX TYPICAL COMPONENT CENTER LINE 250 mm (9.843”) CAMBER (TOP VIEW) ALLOWABLE CAMBER TO BE 1 mm/100 mm NONACCUMULATIVE OVER 250 mm 7. A0, B0, and K0 are determined by component size. The clearance between the components and the cavity must be within 0.05 mm min to 0.50 mm max. The component cannot rotate more than 10° within the determined cavity Figure 11. Carrier Tape Specifications http://onsemi.com 7 MC74LVX259 EMBOSSED CARRIER DIMENSIONS (See Notes 8. and 9.) Tape Size B1 Max 8 mm 4.35 mm (0.179”) 12 mm 8.2 mm (0.323”) 16 mm 24 mm D D1 E F K P P0 P2 R T W 1.5 mm + 0.1 –0.0 (0.059” ( 0 004 +0.004 –0.0) 1.0 mm Min (0.179”) 1.75 mm ±0.1 (0.069 ±0.004”)) 3.5 mm ±0.5 (1.38 ±0.002”) 2.4 mm Max (0.094”) 4.0 mm ±0.10 (0.157 ±0.004”) 4.0 mm ±0.1 (0.157 ±0.004”)) 2.0 mm ±0.1 (0.079 ±0.004”)) 25 mm (0.98”) 0.6 mm (0.024) 8.3 mm (0.327) 5.5 mm ±0.5 (0.217 ±0.002”) 6.4 mm Max (0.252”) 4.0 mm ±0.10 (0.157 ±0.004”) 8.0 mm ±0.10 (0.315 ±0.004”) 12.1 mm (0.476”) 7.5 mm ±0.10 (0.295 ±0.004”) 7.9 mm Max (0.311”) 4.0 mm ±0.10 (0.157 ±0.004”) 8.0 mm ±0.10 (0.315 ±0.004”) 12.0 mm ±0.10 (0.472 ±0.004”) 16.3 mm (0.642) 20.1 mm (0.791”) 11.5 mm ±0.10 (0.453 ±0.004”) 11.9 mm Max (0.468”) 16.0 mm ±0.10 (0.63 ±0.004”) 24.3 mm (0.957) 1.5 mm Min (0.060) 30 mm (1.18”) 12.0 mm ±0.3 (0.470 ±0.012”) 8. Metric Dimensions Govern–English are in parentheses for reference only. 9. A0, B0, and K0 are determined by component size. The clearance between the components and the cavity must be within 0.05 mm min to 0.50 mm max. The component cannot rotate more than 10° within the determined cavity http://onsemi.com 8 MC74LVX259 t MAX 1.5 mm MIN (0.06”) A 13.0 mm ±0.2 mm (0.512” ±0.008”) 20.2 mm MIN (0.795”) 50 mm MIN (1.969”) FULL RADIUS G Figure 12. Reel Dimensions REEL DIMENSIONS Tape Size T&R Suffix A Max G t Max 8 mm T1, T2 178 mm (7”) 8.4 mm, +1.5 mm, –0.0 (0.33” + 0.059”, –0.00) 14.4 mm (0.56”) 8 mm T3, T4 330 mm (13”) 8.4 mm, +1.5 mm, –0.0 (0.33” + 0.059”, –0.00) 14.4 mm (0.56”) 12 mm R2 330 mm (13”) 12.4 mm, +2.0 mm, –0.0 (0.49” + 0.079”, –0.00) 18.4 mm (0.72”) 16 mm R2 360 mm (14.173”) 16.4 mm, +2.0 mm, –0.0 (0.646” + 0.078”, –0.00) 22.4 mm (0.882”) 24 mm R2 360 mm (14.173”) 24.4 mm, +2.0 mm, –0.0 (0.961” + 0.078”, –0.00) 30.4 mm (1.197”) DIRECTION OF FEED BARCODE LABEL POCKET Figure 13. Reel Winding Direction http://onsemi.com 9 HOLE MC74LVX259 CAVITY TAPE TAPE TRAILER (Connected to Reel Hub) NO COMPONENTS 160 mm MIN TOP TAPE TAPE LEADER NO COMPONENTS 400 mm MIN COMPONENTS DIRECTION OF FEED Figure 14. Tape Ends for Finished Goods User Direction of Feed Figure 15. TSSOP and SOIC R2 Reel Configuration/Orientation TAPE UTILIZATION BY PACKAGE Tape Size SOIC TSSOP QFN 8 mm SC88A / SOT–353 SC88/SOT–363 5–, 6–Lead 12 mm 8–Lead 8–, 14–, 16–Lead 8–, 14–, 16–Lead 16 mm 14–, 16–Lead 20–, 24–Lead 20–, 24–Lead 24 mm 18–, 20–, 24–, 28–Lead 48–, 56–Lead 48–, 56–Lead http://onsemi.com 10 MC74LVX259 PACKAGE DIMENSIONS SOIC–16 D SUFFIX CASE 751B–05 ISSUE J –A– 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 –B– 1 P 8 PL 0.25 (0.010) 8 M B S G R K DIM A B C D F G J K M P R F X 45 C –T– SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A S MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019 TSSOP–16 DT SUFFIX CASE 948F–01 ISSUE O 16X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S S K ÉÉ ÇÇÇ ÇÇÇ ÉÉ K1 2X L/2 16 9 J1 B –U– L SECTION N–N J PIN 1 IDENT. 8 1 N 0.15 (0.006) T U S 0.25 (0.010) A –V– M N NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. F DETAIL E –W– C 0.10 (0.004) –T– SEATING PLANE H D DETAIL E G http://onsemi.com 11 DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0 8 INCHES MIN MAX 0.193 0.200 0.169 0.177 --0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0 8