ONSEMI MC10EP16VADR2

MC10EP16VA, MC100EP16VA
3.3V / 5VECL Differential
Receiver/Driver with High
Gain
The EP16VA is a world–class differential receiver/driver. The
device is functionally equivalent to the EP16 and LVEP16 devices but
with high gain output. QHG and QHG outputs have a DC gain several
times larger than the DC gain of an EP16.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 F capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
Under open input conditions (pulled to VEE) internal input clamps
will force the QHG output LOW.
Special considerations are required for differential inputs under No
Signal conditions to prevent instability.
The 100 Series contains temperature compensation.
•
•
•
•
•
•
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MARKING DIAGRAMS*
1
SO–8
D SUFFIX
CASE 751
Gain > 200
20 mV Minimum Input Voltage Swing
HEP64
ALYW
8
PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = –3.0 V to –5.5 V
Open Input Default State
KP64
ALYW
HP64
ALYW
1
1
1
H = MC10
K = MC100
A = Assembly Location
Maximum Frequency > 3 GHz Typical
KEP64
ALYW
1
1
8
8
TSSOP–8
DT SUFFIX
CASE 948R
270 ps Typical Propagation Delay
8
8
8
L = Wafer Lot
Y = Year
W = Work Week
*For additional information, see Application Note
AND8002/D
•
• VBB Output
ORDERING INFORMATION
Package
Shipping
MC10EP16VAD
Device
SO–8
98 Units/Rail
MC10EP16VADR2
SO–8
2500 Tape & Reel
MC100EP16VAD
SO–8
98 Units/Rail
MC100EP16VADR2
SO–8
2500 Tape & Reel
MC10EP16VADT
TSSOP–8
100 Units/Rail
MC10EP16VADTR2
TSSOP–8 2500 Tape & Reel
MC100EP16VADT
TSSOP–8
100 Units/Rail
MC100EP16VADTR2 TSSOP–8 2500 Tape & Reel
 Semiconductor Components Industries, LLC, 2002
September, 2002 – Rev. 4
1
Publication Order Number:
MC10EP16VA/D
MC10EP16VA, MC100EP16VA
NC
1
8
VCC
PIN DESCRIPTION
D
D
VBB
2
7
QHG
QHG
6
3
4
FUNCTION
D*, D*
ECL Data Inputs
QHG, QHG
ECL High Gain Data Outputs
VBB
Reference Voltage Output
VCC
Positive Supply
VEE
Negative Supply
NC
No Connect
* Pins will default LOW when left open.
VEE
5
PIN
Figure 1. 8–Lead Pinout (Top View) and Logic Diagram
ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 k
Internal Input Pullup Resistor
ESD Protection
N/A
Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
Flammability Rating
Level 1
Oxygen Index: 28 to 34
UL–94 V–0 @ 0.125 in
Transistor Count
167
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
MAXIMUM RATINGS (Note 2)
Parameter
Symbol
Condition 1
Condition 2
Rating
Units
VCC
PECL Mode Power Supply
VEE = 0 V
6
V
VEE
NECL Mode Power Supply
VCC = 0 V
–6
V
VI
PECL
C Mode
ode Input
u Voltage
o age
VEE = 0 V
VI VCC
6
V
NECL Mode Input Voltage
VCC = 0 V
VI VEE
–6
V
Output Current
Continuous
50
mA
Surge
100
mA
± 0.5
mA
–40 to +85
°C
Iout
IBB
VBB Sink/Source
TA
Operating Temperature Range
Tstg
Storage Temperature Range
θJA
Thermal Resistance (Junction–to–Ambient)
θJC
Thermal Resistance (Junction–to–Case)
θJA
Thermal Resistance (Junction–to–Ambient)
–65 to +150
°C
190
°C/W
8 SOIC
130
°C/W
8 SOIC
41 to 44
°C/W
8 TSSOP
185
°C/W
8 TSSOP
140
°C/W
8 TSSOP
41 to 44
°C/W
265
°C
0 LFPM
8 SOIC
500 LFPM
std bd
0 LFPM
500 LFPM
θJC
Thermal Resistance (Junction–to–Case)
std bd
Tsol
Wave Solder
<2 to 3 sec @ 248°C
2. Maximum Ratings are those values beyond which device damage may occur.
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2
MC10EP16VA, MC100EP16VA
10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3)
–40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
20
28
31
22
30
38
24
32
40
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 4)
2165
2240
2415
2230
2355
2480
2290
2415
2540
mV
VOL
Output LOW Voltage (Note 4)
1365
1490
1615
1430
1555
1680
1490
1615
1740
mV
VIH
Input HIGH Voltage (Single–Ended)
2090
2415
2155
2480
2215
2540
mV
VIL
Input LOW Voltage (Single–Ended)
1365
1690
1460
1755
1490
1815
mV
VBB
Output Voltage Reference
1750
1950
1825
2025
1850
2050
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 5)
3.3
2.0
3.3
2.0
3.3
V
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
1850
2.0
1925
150
1950
150
0.5
0.5
µA
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to –2.2 V.
4. All loading with 50 to VCC–2.0 volts.
5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6)
–40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
20
28
31
22
30
38
24
32
40
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 7)
3865
3940
4115
3930
4055
4180
3990
4115
4240
mV
VOL
Output LOW Voltage (Note 7)
3065
3190
3315
3130
3255
3380
3190
3315
3440
mV
VIH
Input HIGH Voltage (Single–Ended)
3790
4115
3855
4180
3915
4240
mV
VIL
Input LOW Voltage (Single–Ended)
3065
3390
3130
3455
3190
3515
mV
VBB
Output Voltage Reference
3450
3650
3525
3725
3550
3750
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 8)
5.0
2.0
5.0
2.0
5.0
V
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
3550
2.0
3625
150
3650
150
0.5
0.5
µA
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to –0.5 V.
7. All loading with 50 to VCC–2.0 volts.
8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
10EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = –5.5 V to –3.0 V (Note 9)
–40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
20
28
31
22
30
38
24
32
40
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 10)
–1135
–1060
–885
–1070
–945
–820
–1010
–885
–760
mV
VOL
Output LOW Voltage (Note 10)
–1935
–1810
–1685
–1870
–1745
–1620
–1810
–1685
–1560
mV
VIH
Input HIGH Voltage (Single–Ended)
–1210
–885
–1145
–820
–1085
–760
mV
VIL
Input LOW Voltage (Single–Ended)
–1935
–1610
–1870
–1545
–1810
–1485
mV
VBB
Output Voltage Reference
–1550
–1350
–1475
–1275
–1450
–1250
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 11)
0.0
V
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
–1450
VEE+2.0
0.0
VEE+2.0
150
0.5
–1375
0.0
VEE+2.0
150
0.5
–1350
0.5
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
9. Input and output parameters vary 1:1 with VCC.
10. All loading with 50 to VCC–2.0 volts.
11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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3
MC10EP16VA, MC100EP16VA
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 12)
–40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
20
28
36
22
30
38
24
32
40
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 13)
2155
2280
2405
2155
2280
2405
2155
2280
2405
mV
VOL
Output LOW Voltage (Note 13)
1355
1480
1605
1355
1480
1605
1355
1480
1605
mV
VIH
Input HIGH Voltage (Single–Ended)
2075
2420
2075
2420
2075
2420
mV
VIL
Input LOW Voltage (Single–Ended)
1355
1675
1355
1675
1355
1675
mV
VBB
Output Voltage Reference
1550
1950
1725
1925
1700
1900
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 14)
3.3
2.0
3.3
2.0
3.3
V
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
1850
2.0
1825
150
1800
150
0.5
0.5
µA
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
12. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to –2.2 V.
13. All loading with 50 to VCC–2.0 volts.
14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 15)
–40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
20
28
36
22
30
38
24
32
40
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 16)
3855
3980
4105
3855
3980
4105
3855
3980
4105
mV
VOL
Output LOW Voltage (Note 16)
3055
3180
3305
3055
3180
3305
3055
3180
3305
mV
VIH
Input HIGH Voltage (Single–Ended)
3775
4120
3775
4120
3775
4120
mV
VIL
Input LOW Voltage (Single–Ended)
3055
3375
3055
3375
3055
3375
mV
VBB
Output Voltage Reference
3450
3650
3425
3625
3400
3600
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 17)
5.0
2.0
5.0
2.0
5.0
V
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
3550
2.0
3525
150
3500
150
0.5
0.5
µA
0.5
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
15. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to –0.5 V.
16. All loading with 50 to VCC–2.0 volts.
17. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = –5.5 V to –3.0 V (Note 18)
–40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
20
28
36
22
30
38
24
32
40
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 19)
–1145
–1020
–895
–1145
–1020
–895
–1145
–1020
–895
mV
VOL
Output LOW Voltage (Note 19)
–1945
–1820
–1695
–1945
–1820
–1695
–1945
–1820
–1695
mV
VIH
Input HIGH Voltage (Single–Ended)
–1225
–880
–1225
–880
–1225
–880
mV
VIL
Input LOW Voltage (Single–Ended)
–1945
–1625
–1945
–1625
–1945
–1625
mV
VBB
Output Voltage Reference
–1550
–1350
–1575
–1375
–1600
–1400
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Differential) (Note 20)
0.0
V
IIH
Input HIGH Current
150
µA
IIL
Input LOW Current
–1450
VEE+2.0
0.0
VEE+2.0
150
0.5
–1475
0.0
VEE+2.0
150
0.5
–1500
0.5
µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
18. Input and output parameters vary 1:1 with VCC.
19. All loading with 50 to VCC–2.0 volts.
20. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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4
MC10EP16VA, MC100EP16VA
AC CHARACTERISTICS VCC = 0 V; VEE = –3.0 V to –5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 21)
–40°C
Symbol
Characteristic
fmax
Maximum Frequency
(See Figure 2 Fmax/JITTER)
tPLH,
tPHL
Propagation Delay to
Output Differential
tSKEW
Min
Typ
25°C
Max
Min
Typ
>3
200
Max
Min
>3
260
320
Duty Cycle Skew (Note 22)
5.0
tJITTER
Cycle–to–Cycle Jitter
(See Figure 2 Fmax/JITTER)
VPP
Input Voltage Swing (Differential)
(See Figure 3)
tr
tf
Output Rise/Fall Times
(20% – 80%)
Q, Q
85°C
220
Typ
Max
>3
270
340
20
5.0
0.2
<1
20
800
1200
70
110
170
250
Unit
GHz
320
390
ps
20
5.0
20
ps
0.2
<1
0.2
<1
ps
20
800
1200
20
800
1200
mV
80
110
180
80
120
200
ps
900
9
800
8
700
7
600
6
500
5
400
4
300
3
200
2
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉ
ÉÉ
(JITTER)
1
100
0
0
1000
2000
3000
4000
5000
FREQUENCY (MHz)
Figure 2. Fmax/Jitter
800
700
VOUTpp (mV)
600
500
400
300
200
100
0
20
15
10
5
VINpp (mV)
Figure 3. Gain vs. Input Voltage (50 MHz)
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5
JITTEROUT ps (RMS)
VOUTpp (mV)
21. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 to VCC–2.0 V.
22. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays
are measured from the cross point of the inputs to the cross point of the outputs.
0
MC10EP16VA, MC100EP16VA
Q
D
Receiver
Device
Driver
Device
Q
D
50 50 V TT
V TT = V CC – 2.0 V
Figure 4. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 – Termination of ECL Logic Devices.)
Resource Reference of Application Notes
AN1404
–
ECLinPS Circuit Performance at Non–Standard VIH Levels
AN1405
–
ECL Clock Distribution Techniques
AN1406
–
Designing with PECL (ECL at +5.0 V)
AN1504
–
Metastability and the ECLinPS Family
AN1568
–
Interfacing Between LVDS and ECL
AN1650
–
Using Wire–OR Ties in ECLinPS Designs
AN1672
–
The ECL Translator Guide
AND8001
–
Odd Number Counters Design
AND8002
–
Marking and Date Codes
AND8009
–
ECLinPS Plus Spice I/O Model Kit
AND8020
–
Termination of ECL Logic Devices
For an updated list of Application Notes, please see our website at http://onsemi.com.
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6
MC10EP16VA, MC100EP16VA
PACKAGE DIMENSIONS
SO–8
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751–07
ISSUE AA
–X–
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. 751-01 THRU 751-06 ARE OBSOLETE. NEW
STANDAARD IS 751-07
A
8
5
0.25 (0.010)
S
B
1
Y
M
M
4
K
–Y–
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 SEATING
PLANE
–Z–
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
X
S
J
S
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0
8
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0
8
0.010
0.020
0.228
0.244
TSSOP–8
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948R–02
ISSUE A
8x
0.15 (0.006) T U
K REF
0.10 (0.004)
S
2X
L/2
8
1
PIN 1
IDENT
S
T U
V
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE -W-.
S
5
0.25 (0.010)
B
–U–
L
0.15 (0.006) T U
M
M
4
A
–V–
F
DETAIL E
C
0.10 (0.004)
–T– SEATING
PLANE
D
–W–
G
DETAIL E
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7
DIM
A
B
C
D
F
G
K
L
M
MILLIMETERS
MIN
MAX
2.90
3.10
2.90
3.10
0.80
1.10
0.05
0.15
0.40
0.70
0.65 BSC
0.25
0.40
4.90 BSC
0
6
INCHES
MIN
MAX
0.114
0.122
0.114
0.122
0.031
0.043
0.002
0.006
0.016
0.028
0.026 BSC
0.010
0.016
0.193 BSC
0
6
MC10EP16VA, MC100EP16VA
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make
changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death
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and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
Literature Fulfillment:
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For additional information, please contact your local
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http://onsemi.com
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