Revised May 2005
74AC16244 • 74ACT16244
16-Bit Buffer/Line Driver with 3-STATE Outputs
General Description
Features
The AC16244 and ACT16244 contain sixteen non-inverting
buffers with 3-STATE outputs designed to be employed as
a memory and address driver, clock driver, or bus oriented
transmitter/receiver. The device is nibble controlled. Each
nibble has separate 3-STATE control inputs which can be
shorted together for full 16-bit operation.
■ Separate control logic for each byte and nibble
■ 16-bit version of the AC244/ACT244
■ Outputs source/sink 24 mA
■ ACT16244 has TTL-compatible inputs
Ordering Code:
Order Number
Package Number
Package Description
74AC16244SSC
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74ACT16244SSC
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74ACT16244MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagram
Pin Descriptions
Pin Names
Description
OEn
Output Enable Input (Active LOW)
I0 - I15
Inputs
O0 - 015
Outputs
FACT¥ is a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS500295
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74AC16244 • 74ACT16244 16-Bit Buffer/Line Driver with 3-STATE Outputs
August 1999
74AC16244 • 74ACT16244
Functional Description
3-STATE outputs are controlled by an Output Enable (OEn)
input for each nibble. When OEn is LOW, the outputs are in
2-state mode. When OEn is HIGH, the outputs are in the
high impedance mode, but this does not interfere with
entering new data into the inputs.
The AC16244 and ACT16244 contain sixteen non-inverting
buffers with 3-STATE standard outputs. The device is nibble (4 bits) controlled with each nibble functioning identically, but independent of the other. The control pins can be
shorted together to obtain full 16-bit operation. The
Truth Tables
Inputs
Outputs
Inputs
Outputs
OE1
I0–I3
O0–O3
OE2
I4–I7
O4–O7
L
L
L
L
L
L
L
H
H
L
H
H
H
X
Z
H
X
Z
Inputs
OE3
Outputs
I8–I11
Inputs
O8–O11
OE4
Outputs
I12–I15
O12–O15
L
L
L
L
L
L
L
H
H
L
H
H
H
X
Z
H
X
Z
X
Z
L LOW Voltage Level
H HIGH Voltage Level
Logic Diagram
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2
Immaterial
High Impedance
Recommended Operating
Conditions
0.5V to 7.0V
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI
VI
0.5V
VCC 0.5V
Supply Voltage (VCC)
20 mA
20 mA
DC Output Diode Current (IOK)
20 mA
20 mA
VO
0.5V to VCC 0.5V
DC Output Voltage (VO)
DC Output Source/Sink Current (IO)
r50 mA
VO
0.5V
VCC 0.5V
Storage Temperature
4.5V to 5.5V
Input Voltage (VI)
0V to VCC
Output Voltage (VO)
0V to VCC
40qC to 85qC
Operating Temperature (TA)
AC Devices
VIN from 30% to 70%
r50 mA
140qC
65qC to 150qC
Junction Temperature
2.0V to 6.0V
ACT
Minimum Input Edge Rate ('V/'t)
DC VCC or Ground Current
per Output Pin
AC
VCC @ 3.3V, 4.5V, 5.5V
125 mV/ns
Minimum Input Edge Rate ('V/'t)
ACT Devices
VIN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without exception to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT¥ circuits outside databook specifications.
DC Electrical Characteristics for AC
Symbol
VIH
VIL
VOH
VOL
IOZ
Parameter
Minimum HIGH Input Voltage
Maximum LOW Input Voltage
Minimum HIGH Output Voltage
Maximum LOW Output Voltage
Maximum 3-STATE Leakage Current
VCC
TA
25qC
TA
40qC to 85qC
(V)
Typ
Guaranteed Limits
3.0
1.5
2.1
2.1
4.5
2.25
3.15
3.15
3.85
5.5
2.75
3.85
3.0
1.5
0.9
0.9
4.5
2.25
1.35
1.35
5.5
2.75
1.65
1.65
3.0
2.99
2.9
2.9
4.5
4.49
4.4
4.4
5.5
5.49
5.4
5.4
3.0
2.56
2.46
4.5
3.86
3.76
5.5
4.86
4.76
3.0
0.002
0.1
0.1
4.5
0.001
0.1
0.1
5.5
0.001
0.1
0.1
3.0
0.36
0.44
4.5
0.36
0.44
5.5
0.36
0.44
5.5
0.50
r 5.0
Units
Conditions
VOUT
V
VOUT
or VCC 0.1V
V
IOUT
V
V
V
PA
50 PA
IOH
-12 mA
IOH
24 mA
IOH
24 mA (Note 2)
50 PA
IOUT
IOL
12 mA
IOL
24 mA
IOL
24 mA (Note 2)
VI (OE)
5.5
r 0.1
r 1.0
8.0
PA
VI
VIL, VIH
VCC, GND
VO
Maximum Input Leakage Current (Note 3)
0.1V
V
VI
IIN
0.1V
or VCC 0.1V
VCC, GND
VCC, GND
ICC
Max Quiescent Supply Current (Note 3)
5.5
80.0
PA
VIN
IOLD
Minimum Dynamic
5.5
75
mA
VOLD
1.65V Max
IOHD
Output Current (Note 4)
5.5
75
mA
VOHD
3.85V Min
VCC or GND
Note 2: All outputs loaded; thresholds associated with output under test.
Note 3: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
Note 4: Maximum test duration 2.0 millisecond; one output loaded at a time.
3
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74AC16244 • 74ACT16244
Absolute Maximum Ratings(Note 1)
74AC16244 • 74ACT16244
DC Electrical Characteristics for ACT
Symbol
VIH
VIL
VOH
VOL
Parameter
Minimum HIGH Input Voltage
Maximum LOW Input Voltage
Minimum HIGH Output Voltage
Maximum LOW Output Voltage
25qC
TA
40qC to 85qC
VCC
TA
(V)
Typ
4.5
1.5
2.0
2.0
5.5
1.5
2.0
2.0
4.5
1.5
0.8
0.8
5.5
1.5
0.8
0.8
4.5
4.49
4.4
4.4
5.5
5.49
5.4
5.4
Guaranteed Limits
4.5
3.86
3.76
5.5
4.86
4.76
4.5
0.001
0.1
0.1
5.5
0.001
0.1
0.1
4.5
0.36
0.44
5.5
0.36
0.44
Units
V
V
V
V
Conditions
VOUT
0.1V
or VCC 0.1V
VOUT
0.1V
or VCC 0.1V
IOUT
50 PA
VIN
VIL or VIH
IOH
24 mA
IOH
24 mA (Note 5)
50 PA
V
IOUT
VIN
VIL or VIH
V
IOH
24 mA
IOH
24 mA (Note 5)
IOZ
Maximum 3-STATE Leakage Current
5.5
r 0.5
r 5.0
PA
VI
IIN
Maximum Input Leakage Current
5.5
r 0.1
r 1.0
PA
VI
VCC, GND
ICCT
Maximum ICC/Input
5.5
1.5
mA
VI
VCC 2.1V
ICC
Max Quiescent Supply Current
5.5
8.0
80.0
PA
VIN
IOLD
Minimum Dynamic
75
mA
VOLD
1.65V Max
IOHD
Output Current (Note 6)
75
mA
VOHD
3.85V Min
VIL, VIH
VO
0.6
5.5
Note 5: All outputs loaded; thresholds associated with output under test.
Note 6: Maximum test duration 2.0 millisecond; one output loaded at a time.
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4
VCC, GND
VCC or GND
Symbol
tPLH
tPHL
tPZH
tPZL
Parameter
25qC
CL
50 pF
TA
40qC to 85qC
CL
50 pF
Min
Typ
Max
Min
Max
Propagation Delay
3.3
2.0
6.3
9.4
2.0
10.8
Data to Output
5.0
1.6
4.6
6.5
1.6
7.1
Propagation Delay
3.3
2.4
5.7
10.7
2.4
11.8
Data to Output
5.0
2.0
4.3
7.0
2.0
7.9
Output Enable Time
3.3
2.2
6.2
10
2.2
11.5
5.0
1.7
4.6
6.7
1.7
7.5
3.3
2.9
6.4
13.0
2.9
14.6
5.0
2.2
4.7
8.1
2.2
9.0
3.3
3.1
5.5
8.4
3.1
9.1
5.0
1.9
3.9
7.8
1.9
8.4
3.3
2.4
4.7
8.1
2.4
8.8
5.0
1.7
3.6
7.2
1.7
7.6
Output Disable Time
tPLZ
TA
(V)
(Note 7)
Output Enable Time
tPHZ
VCC
Output Disable Time
Units
ns
ns
ns
ns
ns
ns
Note 7: Voltage Range 5.0 is 5.0V r 0.5V.
Voltage Range 3.3 is 3.3V r 0.3V.
AC Electrical Characteristics for ACT
Symbol
Parameter
VCC
TA
25qC
(V)
CL
50 pF
(Note 8)
tPLH
Propagation Delay
tPHL
Data to Output
tPZH
Output Enable
tPZL
Time
tPHZ
Output Disable
tPLZ
Time
5.0
5.0
5.0
TA
40qC to 85qC
CL
50 pF
Min
Typ
Max
Min
Max
3.0
5.2
7.3
3.0
7.8
2.5
4.8
6.8
2.5
7.3
2.5
5.0
7.4
2.5
7.9
2.7
4.6
7.5
2.7
8.0
2.3
5.0
7.9
2.3
8.2
2.0
4.6
7.4
2.0
7.9
Units
ns
ns
ns
Note 8: Voltage Range 5.0 is 5.0V r 0.5V.
Capacitance
Symbol
Parameter
CIN
Input Pin Capacitance
COUT
Output Pin Capacitance
CPD
Power Dissipation Capacitance
Typ
Units
4.5
pF
VCC
5.0V
12
pF
VCC
5.0V
pF
VCC
5.0V
74AC16244
35
74ACT16244
30
5
Conditions
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74AC16244 • 74ACT16244
AC Electrical Characteristics for AC
74AC16244 • 74ACT16244
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
Package Number MS48A
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6
74AC16244 • 74ACT16244 16-Bit Buffer/Line Driver with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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