Revised August 2000 74AC821 • 74ACT821 10-Bit D-Type Flip-Flop with 3-STATE Outputs General Description Features The AC/ACT821 is a 10-bit D-type flip-flop with 3-STATE outputs arranged in a broadside pinout. ■ 3-STATE outputs for bus interfacing ■ Noninverting outputs ■ Outputs source/sink 24 mA ■ TTL compatible inputs Ordering Code: Order Number Package Number 74AC821SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74AC821SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 74ACT821SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74ACT821MTC MTC24 74ACT821SPC N24C Package Description 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. (SPC not available in Tape and Reel.) Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names Description D0–D9 Data Inputs O0–O9 Data Outputs OE Output Enable Input CP Clock Input FACT is a trademark of Fairchild Semiconductor Corporation. © 2000 Fairchild Semiconductor Corporation DS010139 www.fairchildsemi.com 74AC821 • 74ACT821 10-Bit D-Type Flip-Flop with 3-STATE Outputs November 1988 74AC821 • 74ACT821 Functional Description With OE LOW the contents of the flip-flops are available at the outputs. When OE is HIGH the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. The AC/ACT821 consists of ten D-type edge-triggered flipflops. The buffered Clock (CP) and buffered Output Enable (OE) are common to all flip-flops. The flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH CP transition. Function Table Inputs Internal Outputs Q O Function OE H H L L H = HIGH Voltage Level L = LOW Voltage Level Z = HIGH Impedance = LOW-to-HIGH Clock Transition CP D L L Z H H Z High Z High Z L L L Load H H H Load Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Recommended Operating Conditions − 0.5V to + 7.0V Supply Voltage (VCC) DC Input Diode Current (IIK) VI = − 0.5V − 20 mA VI = VCC + 0.5V + 20 mA Supply Voltage (VCC) − 0.5V to VCC + 0.5V DC Input Voltage (VI) VO = VCC + 0.5V + 20 mA 0V to VCC − 40°C to + 85°C Minimum Input Edge Rate (∆V/∆t) AC Devices DC Output Source VIN from 30% to 70% of VCC ± 50 mA VCC @ 3.3V, 4.5V, 5.5V 125 mV/ns Minimum Input Edge Rate (∆V/∆t) DC VCC or Ground Current ± 50 mA per Output Pin (ICC or IGND) Storage Temperature (TSTG) 0V to VCC Operating Temperature (TA) − 0.5V to VCC + 0.5V or Sink Current (IO) 4.5V to 5.5V Output Voltage (VO) − 20 mA DC Output Voltage (VO) 2.0V to 6.0V ACT Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V AC ACT Devices − 65°C to + 150°C VIN from 0.8V to 2.0V Junction Temperature (TJ) VCC @ 4.5V, 5.5V 140°C PDIP 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. DC Electrical Characteristics for AC Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL VOH VCC TA = +25°C (V) Typ 3.0 1.5 TA = −40°C to +85°C Guaranteed Limits 2.1 Units 4.5 2.25 3.15 3.15 5.5 2.75 3.85 3.85 Maximum LOW Level 3.0 1.5 0.9 0.9 Input Voltage 4.5 2.25 1.35 1.35 5.5 2.75 1.65 1.65 Minimum HIGH Level 3.0 2.99 2.9 2.9 Output Voltage 4.5 4.49 4.4 4.4 5.5 5.49 5.4 5.4 3.0 2.56 2.46 4.5 3.86 3.76 5.5 4.86 4.76 Conditions VOUT = 0.1V 2.1 V or VCC − 0.1V VOUT = 0.1V V or VCC − 0.1V V IOUT = − 50 µA VIN = VIL or VIH VOL IOH = − 12 mA V IOH = − 24 mA IOH = − 24 mA (Note 2) Maximum LOW Level 3.0 0.002 0.1 0.1 Output Voltage 4.5 0.001 0.1 0.1 5.5 0.001 0.1 0.1 3.0 0.36 0.44 4.5 0.36 0.44 5.5 0.36 0.44 5.5 ± 0.1 ± 1.0 µA VI = VCC, GND 5.5 ±0.5 ±5.0 µA VI = VCC, GND V IOUT = 50 µA VIN = VIL or VIH IIN (Note 4) Maximum Input Leakage Current IOZ Maximum 3-STATE Current IOL = 12 mA V IOL = 24 mA IOL = 24 mA (Note 2) VI (OE) = V IL, VIH VO = VCC, GND IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max IOHD Output Current (Note 3) 5.5 −75 mA VOHD = 3.85V Min ICC (Note 4) Maximum Quiescent Supply Current 5.5 80.0 µA VIN = VCC or GND 8.0 Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. 3 www.fairchildsemi.com 74AC821 • 74ACT821 Absolute Maximum Ratings(Note 1) 74AC821 • 74ACT821 DC Electrical Characteristics for ACT Symbol Parameter VIL VOH TA = −40°C to +85°C (V) Typ 4.5 1.5 Input Voltage 5.5 1.5 2.0 2.0 Maximum LOW Level 4.5 1.5 0.8 0.8 Input Voltage 5.5 1.5 0.8 0.8 Minimum HIGH Level 4.5 4.49 4.4 4.4 Output Voltage 5.5 5.49 5.4 5.4 3.86 3.76 Minimum HIGH Level VIH TA = +25°C VCC Guaranteed Limits 2.0 2.0 Units V V Conditions VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V or VCC − 0.1V V IOUT = − 50 µA V IOH = − 24 mA VIN = VIL or VIH 4.5 5.5 VOL IOH = − 24 mA (Note 5) 4.86 4.76 Maximum LOW Level 4.5 0.001 0.1 0.1 Output Voltage 5.5 0.001 0.1 0.1 4.5 0.36 0.44 5.5 0.36 0.44 5.5 ±0.1 ±1.0 µA 5.5 ±0.5 ±5.0 µA V IOUT = 50 µA V IOL = 24 mA VIN = VIL or VIH IIN Maximum Input (Note 4) Leakage Current IOZ Maximum 3-STATE Current ICCT Maximum IOL = 24 mA (Note 5) VI = VCC, GND VI = VIL, VIH VO = VCC, GND 1.5 mA VI = VCC − 2.1V IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max IOHD Output Current (Note 6) 5.5 −75 mA ICC Maximum Quiescent 5.5 ICC/Input Supply Current 0.6 5.5 8.0 80.0 µA VOHD = 3.85V Min VIN = VCC or GND Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: Maximum test duration 2.0 ms, one output loaded at a time. AC Electrical Characteristics for AC Symbol Parameter VCC TA = +25°C (V) CL = 50 pF (Note 7) fMAX tPLH tPHL tPZH tPZL tPHZ tPLZ Min Typ TA = −40°C to +85°C CL = 50 pF Max Min Maximum Clock 3.3 110 145 100 Frequency 5.0 120 160 110 Propagation Delay 3.3 3.0 8.0 13.0 3.0 15.0 CP to On 5.0 2.0 6.0 9.5 2.0 10.5 Propagation Delay 3.3 3.0 8.0 13.0 3.0 15.0 CP to On 5.0 2.0 5.5 9.5 2.0 10.5 Output Enable Time 3.3 2.5 6.0 11.0 2.5 12.0 OE to On 5.0 1.5 4.5 8.0 1.5 9.0 Output Enable Time 3.3 2.5 6.5 11.0 2.5 12.0 OE to On 5.0 1.5 5.0 8.0 1.5 9.0 Output Disable Time 3.3 2.5 6.5 10.5 2.5 11.0 OE to On 5.0 1.5 5.0 8.0 1.5 8.5 Output Disable Time 3.3 2.5 6.0 10.5 2.5 11.0 OE to On 5.0 1.5 4.5 8.0 1.5 8.5 Note 7: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V www.fairchildsemi.com 4 Units Max MHz ns ns ns ns ns ns Symbol tS tH tW VCC TA = +25°C (V) CL = 50 pF Parameter TA = −40°C to +85°C CL = 50 pF (Note 8) Typ Setup Time, HIGH or LOW 3.3 −1.0 1.5 1.5 Dn to CP 5.0 −1.0 1.5 1.5 Hold Time, HIGH or LOW 3.3 −1.0 3.5 4.0 Dn to CP 5.0 −1.0 3.5 4.0 CP Pulse Width 3.3 3.5 5.0 5.5 HIGH or LOW 5.0 2.5 4.0 4.0 Units Guaranteed Minimum ns ns ns Note 8: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V AC Electrical Characteristics for ACT Symbol fMAX Parameter Maximum Clock Frequency tPLH Propagation Delay CP to On tPHL Propagation Delay CP to On tPZH Output Enable Time OE to On tPZL Output Enable Time OE to On tPHZ Output Disable Time OE to On tPLZ Output Disable Time OE to On VCC TA = +25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF Max Min Units (Note 9) Min Typ Max 5.0 120 150 5.0 2.0 6.0 9.5 1.5 10.5 ns 5.0 2.5 6.0 9.5 2.0 10.5 ns 5.0 2.5 7.0 10.5 2.0 11.5 ns 5.0 2.5 7.0 10.5 2.0 12.0 ns 5.0 1.5 7.5 12.0 1.0 13.0 ns 5.0 1.5 7.0 10.5 1.0 11.5 ns 110 MHz Note 9: Voltage Range 5.0 is 5.0V ± 0.5V AC Operating Requirements for ACT Symbol Parameter Setup Time, HIGH or LOW tS Dn to CP tH Hold Time, HIGH or LOW Dn to CP tW CP Pulse Width HIGH or LOW VCC TA = +25°C (V) CL = 50 pF TA = −40°C to +85°C CL = 50 pF Units (Note 10) Typ Guaranteed Minimum 5.0 2.5 2.0 2.5 ns 5.0 −0.5 2.0 2.5 ns 5.0 3.0 4.5 5.5 ns Note 10: Voltage Range 5.0 is 5.0V ± 0.5V Capacitance Typ Units CIN Symbol Input Capacitance Parameter 4.5 pF VCC = OPEN CPD Power Dissipation Capacitance 35.0 pF VCC = 5.0V 5 Conditions www.fairchildsemi.com 74AC821 • 74ACT821 AC Operating Requirements for AC 74AC821 • 74ACT821 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M24B www.fairchildsemi.com 6 74AC821 • 74ACT821 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC24 7 www.fairchildsemi.com 74AC821 • 74ACT821 10-Bit D-Type Flip-Flop with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N24C Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 8