NCV8184
Micropower 70 mA
Low Dropout Tracking
Regulator/Line Driver
The NCV8184 is a monolithic integrated low dropout tracking
voltage regulator designed to provide an adjustable buffered output
voltage that closely tracks (±3.0 mV) the reference input.
The part can be used in automotive applications with remote
sensors, or any situation where it is necessary to isolate the output of
your regulator.
The NCV8184 also enables the user to bestow a quick upgrade to
their module when added current is needed, and the existing regulator
cannot provide.
The versatility of this part also enables it to be used as a high−side
driver.
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1
DPAK 5−LEAD
DT SUFFIX
CASE 175AA
1
PIN CONNECTIONS AND
MARKING DIAGRAMS
Features
• 70 mA Source Capability
• Output Tracks within ±3.0 mV
• Low Input Voltage Tracking Performance
•
1
VOUT
(Works Down to VREF = 2.1 V)
Low Dropout (0.35 V Typ. @ 50 mA)
Low Quiescent Current
Thermal Shutdown
Wide Operating Range
Internally Fused Leads in SOIC−8 Package
NCV Prefix, for Automotive and Other Applications Requiring Site
and Change Control
Pb−Free Packages are Available
VOUT
VIN
Current Limit &
Saturation Sense
GND
GND
VIN
8184
ALYW
G
•
•
•
•
•
•
SOIC−8
D SUFFIX
CASE 751
GND
GND
Adj
VREF/ENABLE
Pin
8184G
ALYWW
1. VIN
2. VOUT
3. GND
4. Adj
5. VREF/ENABLE
Tab,
1
8184
A
L
Y
W, WW
G or G
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
Adj
−
VREF/ENABLE
+
GND
BIAS
Thermal
Shutdown
Device
Package
Shipping†
NCV8184D
SOIC−8
98 Units / Tube
NCV8184DG
SOIC−8
(Pb−Free)
98 Units / Tube
NCV8184DR2
SOIC−8
2500/Tape & Reel
NCV8184DR2G
SOIC−8
(Pb−Free)
2500/Tape & Reel
NCV8184DTRK
DPAK
2500/Tape & Reel
DPAK
(Pb−Free)
2500/Tape & Reel
NCV8184DTRKG
Figure 1. Block Diagram
© Semiconductor Components Industries, LLC, 2006
May, 2006 − Rev. 18
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
1
Publication Order Number:
NCV8184/D
NCV8184
MAXIMUM RATINGS
Rating
Value
Unit
Storage Temperature
−65 to 150
°C
Supply Voltage Range (continuous)
−15 to 42
V
Supply Voltage Operating Range
4.0 to 42
V
42
V
Voltage Range (VOUT, Adj)
−3.0 to 42
V
Voltage Range (VREF/ENABLE)
−0.3 to 42
V
Maximum Junction Temperature
150
°C
2.5
200
1000
kV
V
V
240 peak
260 peak (Pb−Free)
(Note 2)
°C
Peak Transient Voltage (VIN = 14 V, Load Dump Transient = 28 V)
ESD Capability
Human Body Model
Machine Model
Charge Device Model
Lead Temperature Soldering:
Reflow: (SMD styles only) (Note 1)
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. 60 second maximum above 183°C.
2. −5°C / +0°C Allowable Conditions, applies to both Pb and Pb−Free devices.
THERMAL CHARACTERISTICS See Package Thermal Data Section (Page 8)
ELECTRICAL CHARACTERISTICS (VIN = 14 V; VREF/ENABLE > 2.1 V; −40°C < TJ < +150°C; COUT = 1.0 mF;
IOUT = 1.0 mA; Adj = VOUT; COUT−ESR = 1.0 W, unless otherwise specified.)
Parameter
Test Conditions
Min
Typ
Max
Unit
−3.0
−
3.0
mV
Regular Output
VREF/ENABLE − VOUT
VOUT Tracking Error
5.7 V ≤ VIN ≤ 26 V, 100 mA ≤ IOUT ≤ 60 mA
2.1 V ≤ VREF/ENABLE ≤ (VIN − 600 mV)
Dropout Voltage (VIN − VOUT)
IOUT = 100 mA
IOUT = 5.0 mA
IOUT = 60 mA
−
−
−
100
250
350
150
500
600
mV
mV
mV
Line Regulation
5.7 V ≤ VIN ≤ 26 V, VREF/ENABLE = 5.0 V
−
−
3.0
mV
Load Regulation
100 mA ≤ IOUT ≤ 60 mA, VREF/ENABLE = 5.0 V
−
−
3.0
mV
Adj Input Bias Current
VREF/ENABLE = 5.0 V
−
0.2
6.0
mA
Current Limit
VIN = 14 V, VREF/ENABLE = 5.0 V, VOUT = 90% of Adj
70
−
400
mA
Quiescent Current (IIN − IOUT)
VIN = 12 V, IOUT = 60 mA
VIN = 12 V, IOUT = 100 mA
VIN = 12 V, VREF/ENABLE = 0 V
−
−
−
5.0
50
−
7.0
70
20
mA
mA
mA
Ripple Rejection
f = 120 Hz, IOUT = 60 mA, 6.0 V ≤ VIN ≤ 26 V
60
−
−
dB
Thermal Shutdown
Guaranteed by Design
150
180
210
°C
0.8
−
2.1
V
−
0.2
3.0
mA
VREF/ENABLE
Enable Voltage
−
Input Bias Current
VREF/ENABLE = 5.0 V
PACKAGE PIN DESCRIPTION
Package Lead Number
SOIC−8
DPAK, 5−LEAD
Lead Symbol
8
1
VIN
1
2
VOUT
Regulated output.
2, 3, 6, 7
Tab, 3
GND
Ground.
4
4
Adj
5
5
VREF/ENABLE
Function
Battery supply input voltage.
Adjust lead, noninverting input.
Reference voltage and ENABLE input.
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2
NCV8184
0.4
1.0
0.3
0.8
TRACKING ERROR (mV)
TRACKING ERROR (mV)
TYPICAL PERFORMANCE CHARACTERISTICS
0.2
0.1
0.0
−0.1
−0.2
0.6
0.4
−40°C
0.2
+25°C
0.0
−0.2
+125°C
−0.4
−0.3
−40
−20
0
20
40
60
80
TEMPERATURE (°C)
100
−0.6
120
0
Figure 2. Tracking Error vs. Temperature
50
70
4.0
3.5
Stable Region
40
3.0
35
Unstable Region
Unstable Region
30
ESR (W)
ESR (W)
60
Figure 3. Tracking Error vs. Output Current
VOUT = 5.0 V
45
20
30
40
50
OUTPUT CURRENT (mA)
10
25
20
2.5
2.0
1.5
15
Data is for 0.1 mF only. Capacitor
values 0.5 mF and above do not
exhibit instability with low ESR.
0.5
5
0
1.0
C2 = 10 mF
10
C2 = 0.1 mF
0
10
Stable Region
50
20
30
40
OUTPUT CURRENT (mA)
60
0.0
70
0
10
C2 = 0.1 mF
VOUT = 5.0 V
20
30
40
50
OUTPUT CURRENT (mA)
60
70
Figure 5. Output Stability with 0.1 mF at Low ESR
Figure 4. Output Stability with Capacitor Change
2.5
12
QUIESCENT CURRENT (mA)
QUIESCENT CURRENT (mA)
VREF / ENABLE = 5.0 V
10
+125°C
8
+25°C
6
−40°C
4
2
2
IOUT = 20 mA
1.5
1
0.5
IOUT = 1 mA
0
0
10
20
30
40
50
OUTPUT CURRENT (mA)
60
0
70
0
Figure 6. Quiescent Current vs. Output Current
5
10
15
INPUT VOLTAGE (V)
20
Figure 7. Quiescent Current vs. Input Voltage
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3
25
NCV8184
TYPICAL PERFORMANCE CHARACTERISTICS
6
OUTPUT VOLTAGE VOUT (V)
DROPOUT VOLTAGE (V)
0.5
+125°C
0.4
+25°C
0.3
0.2
−40°C
0.1
5
4
+25°C
3
+125°C
2
1
−40°C
0.0
0
10
20
30
40
50
OUTPUT CURRENT (mA)
60
0
70
0
Figure 8. Dropout Voltage vs. Output Current
10
15
20
INPUT VOLTAGE VIN (V)
25
30
0.7
REFERENCE CURRENT (mA)
6
5
4
3
2
1
0
1
2
3
4
5
REFERENCE VOLTAGE (V)
6
0.6
0.5
0.4
0.3
0.2
0.1
0.0
7
0
1
2
3
4
5
REFERENCE VOLTAGE (V)
120
115
110
105
100
95
90
85
80
0
1
6
Figure 11. Reference Current vs. Reference
Voltage
Figure 10. Output Voltage vs. Reference Voltage
THERMAL RESISTANCE, JUNCTION
TO AMBIENT, RqJA, (°C/W)
OUTPUT VOLTAGE (V)
5
Figure 9. Output Voltage vs. Input Voltage
7
0
VREF/ENABLE = 5.0 V
2
3
4
COPPER AREA (in2)
5
Figure 12. SOIC−8, qJA as a Function of the
Pad Copper Area (2.0 oz. Cu Thickness),
Board Material = 0.0625 G−10/R−4
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4
6
7
NCV8184
CIRCUIT DESCRIPTION
By pulling the VREF/ENABLE lead below 0.8 V, (see
Figure 16 or Figure 17), the IC is disabled and enters a sleep
state where the device draws less than 20 mA from supply.
When the VREF/ENABLE lead is greater than 2.1 V, VOUT
tracks the VREF/ENABLE lead normally.
The output is capable of supplying 70 mA to the load
while configured as a similar (Figure 13), lower (Figure 15),
or higher (Figure 14) voltage as the reference lead. The Adj
lead acts as the inverting terminal of the op amp and the
VREF lead as the non−inverting.
The device can also be configured as a high−side driver as
displayed in Figure 18.
GND
C1*
1.0 mF
GND
GND
VREF/
ENABLE
Adj
VOUT, 70 mA
Loads
VOUT
C2**
GND
10 mF
RF
GND
B+
VIN
RA
Figure 13. Tracking Regulator at the Same Voltage
Adj
B+
VIN
C2**
10 mF
C1*
1.0 mF
GND
VOUT
GND
GND
GND
R1
VREF/
ENABLE
GND
GND
VREF
C3***
10 nF
Figure 14. Tracking Regulator at Higher Voltages
VOUT, 70 mA
NCV8184
GND
C1*
1.0 mF
R
VOUT + VREF(1 ) E)
RA
VOUT + VREF
VOUT, 70 mA
Loads
VOUT
C2**
GND
10 mF
B+
VIN
VREF/
ENABLE
Adj
5.0 V
C3***
10 nF
C3***
10 nF
Adj
VREF
R2
NCV8184
VOUT, 70 mA
Loads
VOUT
C2**
GND
10 mF
NCV8184
Output Voltage
NCV8184
ENABLE Function
B+
VIN
C1*
1.0 mF
GND
GND
R
VREF/
ENABLE
C3***
10 nF
VREF
from MCU
VOUT + VREF( R2 )
R1 ) R2
Figure 15. Tracking Regulator at Lower Voltages
NCV8501
VREF (5.0 V)
70 mA
70 mA
VOUT
To Load 10 mF
(e.g. sensor)
GND
GND
Adj
NCV8184
100 nF
GND
VIN
GND
mC
C1*
1.0 mF
GND
Adj
GND
VREF/
ENABLE
VOUT
I/O
C3***
10 nF
NCV8184
VIN
6.0 V−40 V
Figure 16. Tracking Regulator with ENABLE Circuit
B+
VIN
GND
GND
VREF/
ENABLE
C3***
10 nF
VOUT + B ) * VSAT
Figure 17. Alternative ENABLE Circuit
Figure 18. High−Side Driver
* C1 is required if the regulator is far from the power source filter.
** C2 is required for stability.
*** C3 is recommended for EMC susceptibility
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5
MCU
NCV8184
APPLICATION NOTES
VOUT Short to Battery
Figure 20. In this case the NCV8184 supply input voltage is
set at 7.0 V when a short to battery (14 V typical) occurs on
VOUT which normally runs at 5.0 V. The current into the
device (ammeter in Figure 20) will draw additional current
as displayed in Figure 21.
The NCV8184 will survive a short to battery when hooked
up the conventional way as shown in Figure 19. No damage
to the part will occur. The part also endures a short to battery
when powered by an isolated supply at a lower voltage as in
Short to battery
C2**
10 mF
B+
VIN
VOUT
NCV8184
VOUT 70 mA
Loads
GND
GND
C1*
1.0 mF
GND
GND
VREF/
ENABLE
Adj
+ Automotive Battery
− typically 14 V
5.0 V
+
5.0 V
−
C3***
10 nF
VOUT = VREF
Figure 19.
Short to battery
A
Loads
VOUT
B+
70 mA
VIN
VOUT
C2**
10 mF
GND
GND
Adj
* C1 is required if the regulator is far from the power source filter.
** C2 is required for stability.
*** C3 is recommended for EMC susceptibility.
NCV8184
Automotive Battery
typically 14 V
C1*
7V
1.0 mF
GND
+
−
GND
VREF/
ENABLE
VOUT = VREF
C3***
10 nF
5.0 V
+
5.0 V
−
Figure 20.
18
Switched Application
16
The NCV8184 has been designed for use in systems where
the reference voltage on the VREF/ENABLE pin is
continuously on. Typically, the current into the
VREF/ENABLE pin will be less than 1.0 mA when the
voltage on the VIN pin (usually the ignition line) has been
switched out (VIN can be at high impedance or at ground.)
Reference Figure 22.
12
10
8
6
Ignition
Switch
VOUT
4
VIN
VOUT
2
C2
10 mF
0
5 6 7 8 9 10 1112 1314 15 1617 1819 20 2122 2324 25 26
VOUT VOLTAGE (V)
GND
GND
Figure 21. VOUT Short to Battery
Adj
NCV8184
CURRENT (mA)
14
GND
6
VBAT
GND
VREF/
ENABLE
Figure 22.
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C1
1.0 mF
< 1.0 mA
VREF
5.0 V
NCV8184
External Capacitors
The value of RqJA can then be compared with those in the
Package Thermal Data Section of the data sheet. Those
packages with RqJA’s less than the calculated value in
equation 2 will keep the die temperature below 150°C.
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external heat
sink will be required.
The output capacitor for the NCV8184 is required for
stability. Without it, the regulator output will oscillate.
Actual size and type may vary depending upon the
application load and temperature range. Capacitor effective
series resistance (ESR) is also a factor in the IC stability.
Worst−case is determined at the minimum ambient
temperature and maximum load expected.
The output capacitor can be increased in size to any
desired value above the minimum. One possible purpose of
this would be to maintain the output voltage during brief
conditions of negative input transients that might be
characteristic of a particular system.
The capacitor must also be rated at all ambient
temperatures expected in the system. To maintain regulator
stability down to −40°C, a capacitor rated at that temperature
must be used.
More information on capacitor selection for SMART
REGULATOR®s is available in the SMART REGULATOR
application note, “Compensation for Linear Regulators,”
document number SR003AN/D, available through our
website at http://www.onsemi.com.
IIN
VIN
VOUT
IQ
Figure 23. Single Output Regulator with Key
Performance Parameters Labeled
Heatsinks
A heatsink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
Each material in the heat flow path between the IC and the
outside environment will have a thermal resistance. Like
series electrical resistances, these resistances are summed to
determine the value of RqJA:
The maximum power dissipation for a single output
regulator (Figure 23) is:
PD(max) + {VIN(max) * VOUT(min)} IOUT(max)
(eq. 1)
RqJA + RqJC ) RqCS ) RqSA
where:
VIN(max) is the maximum input voltage,
VOUT(min) is the minimum output voltage,
IOUT(max) is the maximum output current, for the
application,and
IQ is the quiescent current the regulator consumes at
IOUT(max).
Once the value of PD(max) is known, the maximum
permissible value of RqJA can be calculated:
RqJA + 150°C * TA
PD
IOUT
Control
Features
Calculating Power Dissipation in a Single Output
Linear Regulator
) VIN(max)IQ
SMART
REGULATOR®
(eq. 3)
where:
RqJC = the junction−to−case thermal resistance,
RqCS = the case−to−heatsink thermal resistance, and
RqSA = the heatsink−to−ambient thermal resistance.
RqJC appears in the package section of the data sheet. Like
RqJA, it is a function of package type. RqCS and RqSA are
functions of the package type, heatsink and the interface
between them. These values appear in heat sink data sheets
of heatsink manufacturers.
(eq. 2)
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7
NCV8184
PACKAGE THERMAL DATA
Test Conditions
Typical Value
Parameter
SOIC−8 Package
Units
Min−Pad Board (Figure 24)
1.0 in Pad Board (Figure 25)
Junction−to−Case top (Y−JT, YJT)
39
32
°C/W
Junction−to−Pin 8 (Y−JL8, YJL8)
63
58
°C/W
98
°C/W
Junction−to−Ambient (RqJA, qJA)
DPAK 5−Pin Package
121
0.5
in2
Spreader Board (Figure 26)
1.0
in2
Spreader Board (Figure 27)
Junction−to−Board (Y−JB, YJB)
15
15
°C/W
Junction−to−Pin 3 (tab) (Y−JL3, YJL3)
16
16
°C/W
Junction−to−Ambient (RqJA, qJA)
100
69
°C/W
Figure 24. 2.0 oz. copper, 40 mil traces
Figure 25. 1.0 oz. copper,
approx. 1/8 in2 per lead, 1.0 in2 total
Figure 26. 1.0 oz. copper, 0.3 in2 drain pad,
0.5 in2 including traces
Figure 27. 2.0 oz. copper, 0.5 in2 drain
pad, 1.0 in2 including traces
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8
NCV8184
Table 1. SOIC−8 Thermal RC Network Models*
Board Type
Min−Pad
(SPICE Deck Format)
1.0 inch Pad
Min−Pad
Cauer Network
1.0 inch Pad
Foster Network
Min
1.0 inch
Units
Tau
Tau
Units
C_C1
Junction
Gnd
7.06879E−7
7.06879E−7
W−s/C
2.99E−7
2.99E−7
sec
C_C2
node1
Gnd
3.34499E−6
3.34499E−6
W−s/C
4.40E−6
4.40E−6
sec
C_C3
node2
Gnd
1.00350E−5
1.00350E−5
W−s/C
4.48E−5
4.48E−5
sec
C_C4
node3
Gnd
3.68358E−5
3.68358E−5
W−s/C
2.46E−4
2.46E−4
sec
C_C5
node4
Gnd
4.29554E−4
4.29554E−4
W−s/C
4.72E−3
4.72E−3
sec
C_C6
node5
Gnd
7.20791E−3
7.20791E−3
W−s/C
7.18E−2
7.25E−2
sec
C_C7
node6
Gnd
3.52182E−2
3.76156E−2
W−s/C
1.61E+0
1.31E+0
sec
C_C8
node7
Gnd
7.16622E−1
1.33747E+0
W−s/C
2.08E+1
1.62E+1
sec
C_C9
node8
Gnd
6.57830E+0
3.97588E+0
W−s/C
1.33E+2
1.08E+2
sec
Min
1.0 inch
R’s
R’s
R_R1
Junction
node1
5.17805E−1
5.1780E−1
°C/W
0.34137
0.34137
°C/W
R_R2
node1
node2
1.55341E+0
1.5534E+0
°C/W
0.83581
0.83581
°C/W
R_R3
node2
node3
4.66024E+0
4.6602E+0
°C/W
2.36526
2.36526
°C/W
R_R4
node3
node4
4.98386E+0
4.9838E+0
°C/W
6.76959
6.76960
°C/W
R_R5
node4
node5
1.04570E+1
1.0457E+1
°C/W
10.39190
10.39200
°C/W
R_R6
node5
node6
1.14509E+1
1.1450E+1
°C/W
8.68648
8.81855
°C/W
R_R7
node6
node7
3.94880E+1
2.9500E+1
°C/W
38.62760
31.37390
°C/W
R_R8
node7
node8
3.10554E+1
1.6877E+1
°C/W
27.65780
8.93175
°C/W
R_R9
node8
node9
1.77562E+1
1.8812E+1
°C/W
26.24690
28.98470
°C/W
100 mm2
653 mm2
Table 2. DPAK 5−Lead Thermal RC Network Models*
Drain Copper Area (1 oz thick)
(SPICE Deck Format)
100 mm2
653 mm2
Cauer Network
Foster Network
100 mm2
653 mm2
Units
Tau
Tau
Units
C_C1
Junction
Gnd
1.51E−06
1.51E−06
W−s/C
1.00E−06
1.00E−06
sec
C_C2
node1
Gnd
6.00E−06
5.91E−06
W−s/C
1.00E−05
1.00E−05
sec
C_C3
node2
Gnd
1.90E−05
1.81E−05
W−s/C
1.00E−04
1.00E−04
sec
C_C4
node3
Gnd
1.05E−04
9.59E−05
W−s/C
7.00E−04
6.00E−04
sec
C_C5
node4
Gnd
2.98E−03
3.21E−03
W−s/C
1.03E−02
1.03E−02
sec
C_C6
node5
Gnd
2.37E−02
7.87E−02
W−s/C
1.71E−01
1.71E−01
sec
C_C7
node6
Gnd
4.95E−02
7.88E−02
W−s/C
1.17E+00
1.17E+00
sec
C_C8
node7
Gnd
2.32E−01
1.03E+00
W−s/C
7.63E+00
7.63E+00
sec
C_C9
node8
Gnd
6.95E−01
1.58E+00
W−s/C
3.93E+01
3.93E+01
sec
C_C10
node9
Gnd
6.91E+00
1.16E+01
W−s/C
1.42E+02
1.42E+02
sec
100 mm2
653 mm2
R’s
R’s
R_R1
Junction
node1
0.845
0.850
°C/W
0.507
0.507
°C/W
R_R2
node1
node2
1.886
1.933
°C/W
1.096
1.096
°C/W
R_R3
node2
node3
4.758
5.070
°C/W
3.467
3.467
°C/W
R_R4
node3
node4
5.336
4.862
°C/W
7.168
7.168
°C/W
R_R5
node4
node5
3.735
3.201
°C/W
3.394
3.394
°C/W
R_R6
node5
node6
10.537
5.293
°C/W
4.000
0.720
°C/W
R_R7
node6
node7
19.583
6.828
°C/W
15.000
8.912
°C/W
R_R8
node7
node8
38.068
13.172
°C/W
20.000
3.636
°C/W
R_R9
node8
node9
43.000
16.466
°C/W
50.000
15.161
°C/W
R_R10
node9
gnd
16.884
8.868
°C/W
40.000
22.480
°C/W
*Bold face items in the tables above represent the package without the external thermal system.
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9
NCV8184
tools, whereas Foster networks may be more easily
implemented using mathematical tools (for instance, in a
spreadsheet program), according to the following formula:
The Cauer networks generally have physical significance
and may be divided between nodes to separate thermal
behavior due to one portion of the network from another.
The Foster networks, though when sorted by time constant
(as above) bear a rough correlation with the Cauer networks,
are really only convenient mathematical models. Cauer
networks can be easily implemented using circuit simulating
R(t) +
n
Ri ǒ1−e−tńtaui Ǔ
S
i+1
Copper Area (in2)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
160
150
140
qJA (°C/W)
130
120
110
1.0 oz. Cu
100
90
2.0 oz. Cu
80
70
60
50
0
100
200
300
400
Copper Area
500
600
700
(mm2)
Figure 28. DPAK 5−Lead, qJA as a Function of the Pad Copper Area Including Traces,
Board Material 0.62” Thick FR4
100
RqJA 1.0 in. pad (°C/W)
50% Duty Cycle
20%
10
10%
5%
2%
1%
1
0.000001
Non−Normalized Response
0.00001
0.0001
0.001
0.1
0.01
Pulse Width (s)
1
10
Figure 29. SOIC−8 Thermal Duty Cycle Curves on 1.0 in. Spreader Test Board
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10
100
1000
NCV8184
Rq (°C/W)
EFFECTIVE THERMAL RESISTANCE
100
50% Duty Cycle
20%
10 10%
5%
2%
Notes:
PDM
1 1%
t1
Single Pulse
t2
t1
Duty Cycle, D = t
2
(1.0 in pad PCB) Die Size = 2.08 x 1.55 x 0.40 5.0% Active Area
0.1
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
t1 (s)
Figure 30. DPAK 5−Lead Thermal Duty Cycle Curves on 1.0 in. Spreader Test Board
1000
Die Size = 2.08 x 1.55 x 0.40 5.0% Active Area
min pad (Cu Area = 100 mm2)
Rq (°C/W)
100
1.0 in pad (Cu Area = 653 mm2)
10
1
0.1
0.000001
0.00001
0.0001
0.001
0.01
0.1
1
10
100
Time (s)
Figure 31. DPAK 5−Lead Thermal Transient Response on Typical Test Boards
R1
Junction
C1
R2
C2
R3
Rn
Cn
C3
Ambient
(thermal ground)
Time constants are not simple RC products.
Amplitudes of mathematical solution are not the resistance values.
Figure 32. Grounded Capacitor Thermal Network (“Cauer” Ladder)
Junction
R1
R2
R3
Rn
C1
C2
C3
Cn
Each rung is exactly characterized by its RC−product time constant;
Amplitudes are the resistances
Ambient
(thermal ground)
Figure 33. Non−Grounded Capacitor Thermal Ladder (“Foster” Ladder)
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11
1000
NCV8184
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AH
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
−X−
A
8
5
0.25 (0.010)
S
B
1
M
Y
M
4
K
−Y−
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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12
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
NCV8184
PACKAGE DIMENSIONS
DPAK 5, CENTER LEAD CROP
CASE 175AA−01
ISSUE A
−T−
C
B
V
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
SEATING
PLANE
E
R
R1
Z
A
S
DIM
A
B
C
D
E
F
G
H
J
K
L
R
R1
S
U
V
Z
1 2 3 4 5
U
K
F
J
L
H
D
G
5 PL
0.13 (0.005)
M
T
INCHES
MIN
MAX
0.235 0.245
0.250 0.265
0.086 0.094
0.020 0.028
0.018 0.023
0.024 0.032
0.180 BSC
0.034 0.040
0.018 0.023
0.102 0.114
0.045 BSC
0.170 0.190
0.185 0.210
0.025 0.040
0.020
−−−
0.035 0.050
0.155 0.170
MILLIMETERS
MIN
MAX
5.97
6.22
6.35
6.73
2.19
2.38
0.51
0.71
0.46
0.58
0.61
0.81
4.56 BSC
0.87
1.01
0.46
0.58
2.60
2.89
1.14 BSC
4.32
4.83
4.70
5.33
0.63
1.01
0.51
−−−
0.89
1.27
3.93
4.32
SOLDERING FOOTPRINT*
6.4
0.252
2.2
0.086
0.34 5.36
0.013 0.217
5.8
0.228
10.6
0.417
SCALE 4:1
mm Ǔ
ǒinches
0.8
0.031
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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NCV8184/D