ETC CS8182/D

CS8182
Micropower 200 mA
Low Dropout Tracking
Regulator/Line Driver
The CS8182 is a monolithic integrated low dropout tracking
regulator designed to provide adjustable buffered output voltage that
closely tracks (±10 mV) the reference input. The output delivers up to
200 mA while being able to be configured higher, lower or equal to the
reference voltages.
The output has been designed to operate over a wide range (2.8 V to
45 V) while still maintaining excellent DC characteristics. Because of
the CS8182’s high voltage capability, the part will fit into today’s new
42 V automotive systems. The CS8182 is protected from reverse
battery, short circuit and thermal runaway conditions. The device also
can withstand 45 V load dump transients and –50 V reverse polarity
input voltage transients. This makes it suitable for use in automotive
environments.
The VREF/ENABLE lead serves two purposes. It is used to provide
the input voltage as a reference for the output and it also can be pulled
low to place the device in sleep mode where it nominally draws less
than 30 µA from the supply.
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8
1
SO–8
DF SUFFIX
CASE 751
1
5
D2PAK 5–PIN
DPS SUFFIX
CASE 936A
PIN CONNECTIONS AND
MARKING DIAGRAMS
VOUT
GND
GND
Adj
Tab
GND
Pin 1. VIN
2. VOUT
3. GND
4. Adj
5. VREF
1
VOUT
ESD
A
WL, L
YY, Y
WW, W
Current Limit &
SAT Sense
= Assembly Location
= Wafer Lot
= Year
= Work Week
Adj
–
ESD
ORDERING INFORMATION*
+
VREF/ENABLE
ESD
+
GND
Thermal
Shutdown
VIN
GND
GND
VREF/ENABLE
CS8182
AWLYWW
VIN
ENABLE
1
8182
ALYW
Features
• 200 mA Source Capability
• Output Tracks within ±10 mV Worst Case
• Low Dropout (0.35 V typ. @ 200 mA)
• Low Quiescent Current
• Thermal Shutdown
• Short Circuit Protection
• Wide Operating Range
• Internally Fused Leads in SO–8 Package
–
Device
Package
CS8182YDF8
SO–8
95 Units/Rail
CS8182YDFR8
SO–8
2500 Tape & Reel
CS8182YDPS5
D2PAK 5–PIN
50 Units/Rail
CS8182YDPSR5 D2PAK 5–PIN
2.0 V
Shipping
750 Tape & Reel
* Consult your local sales representative for
SO–8 with exposed pads package option.
Figure 1. Block Diagram
 Semiconductor Components Industries, LLC, 2001
April, 2001 – Rev. 13
1
Publication Order Number:
CS8182/D
CS8182
ABSOLUTE MAXIMUM RATINGS*
Rating
Value
Unit
Storage Temperature
–65 to 150
°C
Supply Voltage Range (continuous)
–15 to 45
V
Supply Voltage Range (normal, continuous)
3.4 to 45
V
45
V
–10 to 45
V
Maximum Junction Temperature
150
°C
ESD Capability (Human Body Model)
2.0
kV
230 peak
°C
Peak Transient Voltage (VIN = 14 V, Load Dump Transient = 31 V)
Voltage Range (Adj, VOUT, VREF/ENABLE)
Lead Temperature Soldering:
Reflow: (SMD styles only) (Note 1.)
1. 60 second maximum above 183°C.
*The maximum package power dissipation must be observed.
ELECTRICAL CHARACTERISTICS (VIN = 14 V; VREF/ENABLE > 2.75 V; –40°C < TJ < +125°C; COUT ≥ 10µF;
0.1 Ω < COUT–ESR < 1.0 Ω @ 10 kHz, unless otherwise specified.)
Parameter
Test Conditions
Min
Typ
Max
Unit
–10
–5.0
–
–
10
5
mV
mV
Regular Output
VREF – VOUT
VOUT Tracking Error
4.5 V ≤ VIN ≤ 26 V, 100 µA ≤ IOUT ≤ 200 mA, Note 2.
VIN = 12 V, IOUT = 30 mA, VREF = 5.0 V, Note 2.
Dropout Voltage (VIN – VOUT)
IOUT = 100 µA
IOUT = 30 mA
IOUT = 200 mA
–
–
–
100
–
350
150
500
600
mV
mV
mV
Line Regulation
4.5 V ≤ VIN ≤ 26 V, Note 2.
–
–
10
mV
Load Regulation
100 µA ≤ IOUT ≤ 200 mA, Note 2.
–
–
10
mV
Adj Lead Current
Loop in Regulation
–
0.2
1.0
µA
Current Limit
VIN = 14 V, VREF = 5.0 V, VOUT = 90% of VREF, Note 2.
225
–
700
mA
Quiescent Current (IIN – IOUT)
VIN = 12 V, IOUT = 200 mA
VIN = 12 V, IOUT = 100 µA
VIN = 12 V, VREF/ENABLE = 0 V
–
–
–
15
75
30
25
150
55
mA
µA
µA
Reverse Current
VOUT = 5.0 V, VIN = 0 V
–
0.2
1.5
mA
Ripple Rejection
f = 120 Hz, IOUT = 200 mA, 4.5 V ≤ VIN ≤ 26 V
60
–
–
dB
Thermal Shutdown
GBD
150
180
210
°C
0.80
2.00
2.75
V
–
0.2
1.0
µA
VREF/ENABLE
Enable Voltage
Input Bias Current
–
VREF/ENABLE
2. VOUT connected to Adj lead.
PACKAGE PIN DESCRIPTION
Package Lead Number
SO–8
D2PAK 5–PIN
Lead Symbol
8
1
VIN
1
2
VOUT
Regulated output.
2, 3, 6, 7
3
GND
Ground.
4
4
Adj
5
5
VREF/ENABLE
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2
Function
Input voltage.
Adjust lead.
Reference voltage and ENABLE input.
CS8182
CIRCUIT DESCRIPTION
ENABLE Function
Output Voltage
By pulling the VREF/ENABLE lead below 2.0 V typically,
(see Figure 5 or Figure 6), the IC is disabled and enters a
sleep state where the device draws less than 55 µA from
supply. When the VREF/ENABLE lead is greater than 2.75 V,
VOUT tracks the VREF/ENABLE lead normally.
The output is capable of supplying 200 mA to the load
while configured as a similiar (Figure 2), lower (Figure 4),
or higher (Figure 3) voltage as the reference lead. The Adj
lead acts as the inverting terminal of the op amp and the
VREF lead as the non–inverting.
The device can also be configured as a high–side driver as
displayed in Figure 7.
GND
GND
RA
Adj
VOUT, 200 mA
B+
VIN
CS8182
VREF
Figure 3. Tracking Regulator at Higher Voltages
Figure 2. Tracking Regulator at the Same Voltage
GND
GND
R
VOUT VREF(1 E)
RA
VOUT VREF
VOUT, 200 mA
Loads
VOUT
C2**
GND
10 µF
GND
C1*
1.0 µF
VREF/
ENABLE
Adj
5.0 V
VREF/
ENABLE
Adj
B+
VIN
CS8182
C1*
1.0 µF
C2**
10 µF
C1*
1.0 µF
GND
VOUT
GND
GND
GND
R1
R2
GND
C1*
1.0 µF
GND
R
VREF/
ENABLE
Adj
VREF
VREF/
ENABLE
B+
VIN
CS8182
GND
VOUT, 200 mA
Loads
VOUT
C2**
GND
10 µF
RF
GND
B+
VIN
CS8182
VOUT, 200 mA
Loads
VOUT
C2**
GND
10 µF
VREF
from MCU
VOUT VREF( R2 )
R1 R2
Figure 4. Tracking Regulator at Lower Voltages
CS8101
VREF (5.0 V)
200 mA
100 nF
5.0 V
GND
GND
GND
Adj
GND
VIN
CS8182
VOUT
To Load 10 µF
(e.g. sensor)
VOUT
GND
C1*
1.0 µF
µC
GND
VREF/
ENABLE
Adj
VIN
CS8182
VIN
6.0 V–40 V
Figure 5. Tracking Regulator with ENABLE Circuit
GND
GND
VREF/
ENABLE
VOUT B VSAT
I/O
Figure 6. Alternative ENABLE Circuit
Figure 7. High–Side Driver
* C1 is required if the regulator is far from the power source filter.
** C2 is required for stability.
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3
B+
MCU
CS8182
APPLICATION NOTES
External Capacitors
The value of RΘJA can then be compared with those in the
package section of the data sheet. Those packages with
RΘJA’s less than the calculated value in equation 2 will keep
the die temperature below 150°C.
In some cases, none of the packages will be sufficient to
dissipate the heat generated by the IC, and an external heat
sink will be required.
The output capacitor for the CS8182 is required for
stability. Without it, the regulator output will oscillate.
Actual size and type may vary depending upon the
application load and temperature range. Capacitor effective
series resistance (ESR) is also a factor in the IC stability.
Worst–case is determined at the minimum ambient
temperature and maximum load expected.
The output capacitor can be increased in size to any
desired value above the minimum. One possible purpose of
this would be to maintain the output voltage during brief
conditions of negative input transients that might be
characteristic of a particular system.
The capacitor must also be rated at all ambient
temperatures expected in the system. To maintain regulator
stability down to –40°C, a capacitor rated at that temperature
must be used.
More information on capacitor selection for SMART
REGULATORs is available in the SMART REGULATOR
application note, “Compensation for Linear Regulators,”
document number SR003AN/D, available through the
Literature Distribution Center or via our website at
http://www.onsemi.com.
IIN
VIN
VOUT
IQ
Figure 8. Single Output Regulator with Key
Performance Parameters Labeled
Heatsinks
A heatsink effectively increases the surface area of the
package to improve the flow of heat away from the IC and
into the surrounding air.
Each material in the heat flow path between the IC and the
outside environment will have a thermal resistance. Like
series electrical resistances, these resistances are summed to
determine the value of RΘJA:
The maximum power dissipation for a single output
regulator (Figure 8) is:
PD(max) {VIN(max) VOUT(min)} IOUT(max)
(1)
RJA RJC RCS RSA
where:
VIN(max) is the maximum input voltage,
VOUT(min) is the minimum output voltage,
IOUT(max) is the maximum output current, for the
application,and
IQ is the quiescent current the regulator consumes at
IOUT(max).
Once the value of PD(max) is known, the maximum
permissible value of RΘJA can be calculated:
RJA 150°C TA
PD
IOUT
Control
Features
Calculating Power Dissipation in a Single Output
Linear Regulator
VIN(max)IQ
SMART
REGULATOR
(3)
where:
RΘJC = the junction–to–case thermal resistance,
RΘCS = the case–to–heatsink thermal resistance, and
RΘSA = the heatsink–to–ambient thermal resistance.
RΘJC appears in the package section of the data sheet. Like
RΘJA, it is a function of package type. RΘCS and RΘSA are
functions of the package type, heatsink and the interface
between them. These values appear in heat sink data sheets
of heat sink manufacturers.
(2)
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CS8182
PACKAGE DIMENSIONS
SO–8
DF SUFFIX
CASE 751–06
ISSUE T
D
A
8
5
0.25
H
E
1
M
B
M
4
h
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS ARE IN MILLIMETER.
3. DIMENSION D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
C
X 45 e
A
C
SEATING
PLANE
L
0.10
A1
B
0.25
M
C B
A
S
S
DIM
A
A1
B
C
D
E
e
H
h
L
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.35
0.49
0.19
0.25
4.80
5.00
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0
7
D2PAK 5–PIN
D SUFFIX
CASE 936A–02
ISSUE A
–T–
OPTIONAL
CHAMFER
A
TERMINAL 6
E
U
S
K
B
V
H
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. TAB CONTOUR OPTIONAL WITHIN
DIMENSIONS A AND K.
4. DIMENSIONS U AND V ESTABLISH A MINIMUM
MOUNTING SURFACE FOR TERMINAL 6.
5. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH OR GATE PROTRUSIONS. MOLD
FLASH AND GATE PROTRUSIONS NOT TO
EXCEED 0.025 (0.635) MAXIMUM.
1 2 3 4 5
M
D
0.010 (0.254)
M
T
L
P
N
G
R
C
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5
DIM
A
B
C
D
E
G
H
K
L
M
N
P
R
S
U
V
INCHES
MIN
MAX
0.386
0.403
0.356
0.368
0.170
0.180
0.026
0.036
0.045
0.055
0.067 BSC
0.539
0.579
0.050 REF
0.000
0.010
0.088
0.102
0.018
0.026
0.058
0.078
5 REF
0.116 REF
0.200 MIN
0.250 MIN
MILLIMETERS
MIN
MAX
9.804 10.236
9.042
9.347
4.318
4.572
0.660
0.914
1.143
1.397
1.702 BSC
13.691 14.707
1.270 REF
0.000
0.254
2.235
2.591
0.457
0.660
1.473
1.981
5 REF
2.946 REF
5.080 MIN
6.350 MIN
CS8182
PACKAGE THERMAL DATA
Parameter
SO–8
D2PAK 5–PIN
Unit
RΘJC
Typical
45
4.0
°C/W
RΘJA
Typical
165
10–50*
°C/W
* Depending on thermal properties of substrate. RΘJA = RΘJC + RΘCA
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CS8182
Notes
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7
CS8182
SMART REGULATOR is a registered trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
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CS8182/D