MC10EL34, MC100EL34 5VECL ÷2, ÷4, ÷8 Clock Generation Chip Description The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip−flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon startup, the internal flip-flops will attain a random state; the master reset (MR) input allows for the synchronization of the internal dividers, as well as multiple EL34s in a system. The 100 Series contains temperature compensation. Features • • • • • • • 50 ps Output-to-Output Skew Synchronous Enable/Disable Master Reset for Synchronization PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.7 V Internal Input 75 kW Pulldown Resistors on CLK(s), EN, and MR Pb−Free Packages are Available* http://onsemi.com 16 1 SO−16 D SUFFIX CASE 751B MARKING DIAGRAMS* 16 16 10EL34G AWLYWW 1 100EL34G AWLYWW 1 A WL YY WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. © Semiconductor Components Industries, LLC, 2006 November, 2006 − Rev. 10 1 Publication Order Number: MC10EL34/D MC10EL34, MC100EL34 VCC EN NC CLK 16 15 14 D Q 13 CLK VBB 12 MR VEE 10 9 11 Table 1. FUNCTION TABLE R ÷2 Q R ÷4 Q R 2 3 4 5 6 7 8 Q0 Q0 VCC Q1 Q1 VCC Q2 Q2 EN* MR* Function Z ZZ X L H X L L H Divide Hold Q0−3 Reset Q0−3 *Pins will default low when left open. Z = Low-to-High Transition ZZ = High-to-Low Transition ÷8 Q R 1 CLK* Table 2. PIN DESCRIPTION Pin *All VCC pins are tied together on the die. Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. Figure 1. Logic Diagram and Pinout Assignment Function CLK, CLK ECL Diff Clock Inputs EN ECL Sync Enable MR ECL Master Reset Q0, Q0 ECL Diff ÷2 Outputs Q1, Q1 ECL Diff ÷4 Outputs Q2, Q2 ECL Diff ÷8 Outputs VBB Reference Voltage Output VCC Positive Supply VEE Negative Supply NC No Connect Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 KW Internal Input Pullup Resistor ESD Protection N/A Human Body Model Machine Model Charge Device Model Moisture Sensitivity (Note 1) Flammability Rating > 1 KV > 100 V > 2 KV Level 1 Oxygen Index: 28 to 34 Transistor Count UL 94 V−0 @ 0.125 in 191 Devices Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D. http://onsemi.com 2 MC10EL34, MC100EL34 Table 4. MAXIMUM RATINGS Rating Unit VCC Symbol PECL Mode Power Supply Parameter VEE = 0 V Condition 1 8 V VEE NECL Mode Power Supply VCC = 0 V −8 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 −6 V V Iout Output Current Continuous Surge 50 100 mA mA IBB VBB Sink/Source ± 0.5 mA TA Operating Temperature Range −40 to +85 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm SO−16 SO−16 130 75 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board SO−16 33 to 36 °C/W Tsol Wave Solder <2 to 3 sec @ 248°C <2 to 3 sec @ 260°C 265 265 °C Pb Pb−Free Condition 2 VI v VCC VI w VEE Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 5. 10EL SERIES PECL DC CHARACTERISTICS VCC = 5.0 V; VEE = 0 V (Note 2) −40°C Symbol Characteristic Min Typ 25°C Max Min Typ 85°C Max Unit 39 mA 4185 4280 mV 3227 3405 mV 3940 4280 mV 3520 3050 3555 mV 3.65 3.75 3.69 3.81 V 3.0 4.6 3.0 4.6 V 150 mA 39 Max Min IEE Power Supply Current VOH Output HIGH Voltage (Note 3) 3920 4010 4110 4020 4105 4190 4090 VOL Output LOW Voltage (Note 3) 3050 3200 3350 3050 3210 3370 3050 VIH Input HIGH Voltage (Single−Ended) 3770 4110 3870 4190 VIL Input LOW Voltage (Single−Ended) 3050 3500 3050 VBB Output Voltage Reference 3.57 3.7 VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 4) 3.0 4.6 IIH Input HIGH Current IIL Input LOW Current 150 0.5 Typ 39 150 0.5 0.3 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Input and output parameters vary 1:1 with VCC. VEE can vary +0.06 V / −0.5 V. 3. Outputs are terminated through a 50 W resistor to VCC − 2.0 V. 4. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1 V. http://onsemi.com 3 MC10EL34, MC100EL34 Table 6. 10EL SERIES NECL DC CHARACTERISTICS VCC = 0 V; VEE = −5.0 V (Note 5) −40°C Symbol Characteristic Min Typ 25°C Max Min Typ 39 85°C Max Min Typ 39 Max Unit 39 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 6) −1080 −990 −890 −980 −895 −810 −910 −815 −720 mV VOL Output LOW Voltage (Note 6) −1950 −1800 −1650 −1950 −1790 −1630 −1950 −1773 −1595 mV VIH Input HIGH Voltage (Single−Ended) −1230 −890 −1130 −810 −1060 −720 mV VIL Input LOW Voltage (Single−Ended) −1950 −1500 −1950 −1480 −1950 −1445 mV VBB Output Voltage Reference −1.43 −1.30 −1.35 −1.25 −1.31 −1.19 V VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 7) −2.0 −0.4 −2.0 −0.4 −2.0 −0.4 V IIH Input HIGH Current 150 mA IIL Input LOW Current 150 0.5 150 0.5 0.3 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Input and output parameters vary 1:1 with VCC. VEE can vary +0.06 V / −0.5 V. 6. Outputs are terminated through a 50 W resistor to VCC − 2.0 V. 7. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1 V. Table 7. 100EL SERIES PECL DC CHARACTERISTICS VCC = 5.0 V; VEE = 0 V (Note 8) −40°C Symbol Characteristic Min Typ 25°C Max Min Typ 39 85°C Max Min Typ 39 Max Unit 42 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 9) 3915 3995 4120 3975 4045 4120 3975 4050 4120 mV VOL Output LOW Voltage (Note 9) 3170 3305 3445 3190 3295 3380 3190 3295 3380 mV VIH Input HIGH Voltage (Single−Ended) 3835 4120 3835 4120 3835 4120 mV VIL Input LOW Voltage (Single−Ended) 3190 3525 3190 3525 3190 3525 mV VBB Output Voltage Reference 3.62 3.74 3.62 3.74 3.62 3.74 V VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 10) 2.2 4.6 2.2 4.6 2.2 4.6 V IIH Input HIGH Current 150 mA IIL Input LOW Current 150 0.5 150 0.5 0.5 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 8. Input and output parameters vary 1:1 with VCC. VEE can vary +0.8 V / −0.5 V. 9. Outputs are terminated through a 50 W resistor to VCC − 2.0 V. 10. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1 V. http://onsemi.com 4 MC10EL34, MC100EL34 Table 8. 100EL SERIES NECL DC CHARACTERISTICS VCC = 0 V; VEE = −5.0 V (Note 11) −40°C Symbol Characteristic Min Typ 25°C Max Min Typ 39 85°C Max Min Typ 39 Max Unit 42 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 12) −1085 −1005 −880 −1025 −955 −880 −1025 −955 −880 mV VOL Output LOW Voltage (Note 12) −1830 −1695 −1555 −1810 −1705 −1620 −1810 −1705 −1620 mV VIH Input HIGH Voltage (Single−Ended) −1165 −880 −1165 −880 −1165 −880 mV VIL Input LOW Voltage (Single−Ended) −1810 −1475 −1810 −1475 −1810 −1475 mV VBB Output Voltage Reference −1.38 −1.26 −1.38 −1.26 −1.38 −1.26 V VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 13) −2.8 −0.4 −2.8 −0.4 −2.8 −0.4 V IIH Input HIGH Current 150 mA IIL Input LOW Current 150 150 0.5 0.5 0.5 mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 11. Input and output parameters vary 1:1 with VCC. VEE can vary +0.8 V / −0.5 V. 12. Outputs are terminated through a 50 W resistor to VCC − 2.0 V. 13. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1 V. Table 9. AC CHARACTERISTICS VCC = 5.0 V; VEE = 0.0 V or VCC = 0.0 V; VEE = −5.0 V (Note 14) −40°C Min fmax Maximum Toggle Frequency 1.1 tPLH tPHL Propagation Delay to Output 960 900 750 tSKEW Within-Device Skew (Note 15) 100 100 100 ps tJITTER Cycle−to−Cycle Jitter 1.0 1.0 1.0 ps tS Setup Time EN 400 400 400 ps tH Hold Time EN 250 250 250 ps tRR Set/Reset Recovery 400 VPP Input Swing (Note 16) 150 1000 150 1000 150 1000 mV tr tf Output Rise/Fall Times Q (20% − 80%) 225 475 225 475 225 475 ps CLK to Q0 CLK to Q1,2 MR to Q Max Min Typ 85°C Characteristic Symbol Typ 25°C Max 1.1 1200 1140 1060 200 Typ Max 1.1 960 900 750 400 Min 1200 1140 1060 200 GHz 970 910 790 400 Unit 1210 1150 1090 200 ps ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 14. 10 Series: VEE can vary +0.06 V / −0.5 V. 100 Series: VEE can vary +0.8 V / −0.5 V. 15. Within-device skew is defined as identical transitions on similar paths through a device. 16. VPPmin is minimum input swing for which AC parameters guaranteed. The device has a DC gain of ≈40. http://onsemi.com 5 MC10EL34, MC100EL34 There are two distinct functional relationships between the Master Reset and Clock: Internal Clock Disabled Internal Clock Enabled MR CLK Q0 Q1 Q2 EN CASE 1: If the MR is de−asserted (H−L), while the Clock is still high, the outputs will follow the first ensuing clock rising edge. Internal Clock Disabled Internal Clock Enabled MR CLK Q0 Q1 Q2 EN CASE 2: If the MR is de−asserted (H−L), after the Clock has transitioned low, the outputs will follow the second ensuing clock rising edge. Figure 2. Timing Diagrams The EN signal will “freeze” the internal divider flip−flops on the first falling edge of CLK after its assertion. The internal divider flip−flops will maintain their state during the freeze. The EN is deasserted (LOW), and after the next falling edge of CLK, then the internal divider flip−flops will “unfreeze” and continue to their next state count with proper phase relationships. TRR TRR CLOCK CLOCK MR MR OUTPUT OUTPUT CASE 1 CASE 2 Figure 3. Reset Recovery Time http://onsemi.com 6 MC10EL34, MC100EL34 Zo = 50 W Q D Receiver Device Driver Device Q D Zo = 50 W 50 W 50 W VTT VTT = VCC − 2.0 V Figure 4. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Device MC10EL34D Package Shipping † SO−16 48 Units / Rail MC10EL34DG SO−16 (Pb−Free) 48 Units / Rail MC10EL34DR2 SO−16 2500 / Tape & Reel SO−16 (Pb−Free) 2500 / Tape & Reel SO−16 48 Units / Rail MC100EL34DG SO−16 (Pb−Free) 48 Units / Rail MC100EL34DR2 SO−16 2500 / Tape & Reel SO−16 (Pb−Free) 2500 / Tape & Reel MC10EL34DR2G MC100EL34D MC100EL34DR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices http://onsemi.com 7 MC10EL34, MC100EL34 PACKAGE DIMENSIONS SO−16 D SUFFIX CASE 751B−05 ISSUE J −A− 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 −B− 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C −T− SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A S DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 ECLinPS are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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