SEMICONDUCTOR TECHNICAL DATA The MC10E/100E451 contains six D-type flip-flops with single-ended outputs and differential data inputs. The common clock input is also differential. The registers are triggered by a positive transition of the positive clock (CLK) input. A HIGH on the Master Reset (MR) input resets all Q outputs to LOW. The VBB output is intended for use as a reference voltage for single-ended reception of ECL signals to that device only. When using for this purpose, it is recommended that VBB is decoupled to VCC via a 0.01µF capacitor. The differential input structures are clamped so that the inputs of unused registers can be left open without upsetting the bias network of the device. The clamping action will assert the D and the CLK sides of the inputs. Because of the edge triggered flip-flop nature of the device simultaneously opening both the clock and data inputs will result in an output which reaches an unidentified but valid state. Note that the input clamps only operate when both inputs fall to 2.5V below VCC. • • • • • • 6-BIT D REGISTER DIFFERENTIAL DATA AND CLOCK Differential Inputs: Data and Clock VBB Output FN SUFFIX PLASTIC PACKAGE CASE 776-02 1100MHz Min. Toggle Frequency Asynchronous Master Reset Extended 100E VEE Range of – 4.2V to – 5.46V 75kΩ Input Pulldown Resistors D5 D5 D4 D4 D3 D3 VCCO 25 24 23 22 21 20 19 LOGIC DIAGRAM 26 18 VBB 27 17 Q4 CLK 28 16 VCC VEE 1 15 Q3 MR 2 14 VCCO NC 3 13 Q2 D0 4 12 Q1 CLK Pinout: 28-Lead PLCC (Top View) 5 6 7 8 9 10 Q5 D0 D0 R D1 D1 D D2 D2 D0 – D5 D0 – D5 CLK CLK MR VBB Q0 – Q5 Function +Data Input – Data Input +Clock Input – Clock Input Master Reset Input VBB Output Data Outputs R D3 D3 Q3 D R D4 D4 Q4 D R D5 D5 Q5 D R CLK CLK MR VBB 12/93 Motorola, Inc. 1996 Q2 D PIN NAMES Pin Q1 R 11 D0 D1 D1 D2 D2 VCCO Q0 * All VCC and VCCO pins are tied together on the die. Q0 D 2–1 REV 2 MC10E451 MC100E451 DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND) 0°C Symbol VBB Characteristic Output Reference Voltage 10E 100E IIH Input HIGH Current IEE Power Supply Current 10E 100E min typ 25°C max min –1.2 7 –1.2 6 –1.3 5 –1.3 8 85°C typ max min typ –1.2 5 –1.2 6 –1.3 1 –1.3 8 max Unit Condition V –1.3 8 –1.3 8 150 –1.1 9 –1.2 6 150 µA 150 mA 84 84 101 101 84 84 101 101 84 97 101 116 VCMR Common Mode Range – 2.0 – 0.4 – 2.0 – 0.4 – 2.0 – 0.4 V 2 1. VCMR is referenced to the most positive side of the differential input signal. Normal operation is obtained when the “HIGH” input is within the VCMR range and the input swing is greater than VPP MIN and < 1.0V. AC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND) 0°C Symbol Characteristic min typ 25°C max min typ 1100 1400 475 425 425 650 650 600 85°C max min typ 1100 1400 475 425 425 650 650 600 fMAX Max, Toggle Frequency 1100 1400 tPLH tPHL Propagation Delay to Output CLK (Diff) CLK (SE) MR 475 425 425 650 650 600 ts Setup Time D 150 –100 150 –100 150 –100 Hold Time D 250 100 250 100 250 100 VPP(AC) Minimum Input Swing 150 tRR Reset Recovery Time 750 tPW Minimum Pulse Width CLK, MR 400 th tSKEW Within-Device Skew tr tf Rise/Fall Times 20 - 80% max Unit Condition MHz ps 800 850 850 800 850 850 800 850 850 ps ps 150 600 750 159 600 750 mV 600 1 ps ps 400 100 400 100 100 ps 2 ps 275 450 800 275 450 800 275 450 800 1. Minimum input voltage for which AC parameters are guaranteed. 2. Within-device skew is defined as identical transitions on similar paths through a device. MOTOROLA 2–2 ECLinPS and ECLinPS Lite DL140 — Rev 4 MC10E451 MC100E451 OUTLINE DIMENSIONS FN SUFFIX PLASTIC PLCC PACKAGE CASE 776–02 ISSUE D 0.007 (0.180) B Y BRK -N- T L –M M U 0.007 (0.180) X G1 M S N T L –M S S N S D Z -L- -M- D W 28 V 1 C A 0.007 (0.180) M R 0.007 (0.180) M T L –M S T L –M S N S N S H S N S 0.007 (0.180) M T L –M N S S 0.004 (0.100) G J -T- K SEATING PLANE F VIEW S G1 T L –M S N 0.007 (0.180) M T L –M S N S VIEW S S NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIM G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIM R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). ECLinPS and ECLinPS Lite DL140 — Rev 4 T L –M K1 E S S VIEW D-D Z 0.010 (0.250) 0.010 (0.250) 2–3 DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 — 0.025 — 0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 — 0.020 2° 10° 0.410 0.430 0.040 — MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 — 0.64 — 11.43 11.58 11.43 11.58 1.07 1.21 1.07 1.21 1.07 1.42 — 0.50 2° 10° 10.42 10.92 1.02 — MOTOROLA MC10E451 MC100E451 Motorola reserves the right to make changes without further notice to any products herein. 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