MC100EP809 3.3V1:9 Differential HSTL/PECL to HSTL Clock Driver with LVTTL Clock Select and Enable http://onsemi.com Description The MC100EP809 is a low skew 1−to−9 differential clock driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The part is designed for use in low voltage applications which require a large number of outputs to drive precisely aligned low skew signals to their destination. The two clock inputs are differential HSTL or PECL and they are selected by the CLK_SEL pin which is LVTTL. To avoid generation of a runt clock pulse when the device is enabled/disabled, the Output Enable (OE), which is LVTTL, is synchronous ensuring the outputs will only be enabled/disabled when they are already in LOW state (Figure 8). The MC100EP809 guarantees low output−to−output skew. The optimal design, layout, and processing minimize skew within a device and from lot to lot. The MC100EP809 output structure uses open emitter architecture and will be terminated with 50 to ground instead of a standard HSTL configuration (Figure 6). To ensure the tight skew specification is realized, both sides of the differential output need to be terminated identically into 50 even if only one output is being used. If an output pair is unused, both outputs may be left open (unterminated) without affecting skew. Designers can take advantage of the EP809’s performance to distribute low skew clocks across the backplane of the board. HSTL clock inputs may be driven single−end by biasing the non−driven pin in an input pair (Figure 7). Features MARKING DIAGRAM* MC100 EP809 32−LEAD LQFP FA SUFFIX CASE 873A AWLYYWWG 32 1 A WL YY WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *For additional marking information, refer to Application Note AND8002/D. ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. • 100 ps Typical Device−to−Device Skew • 15 ps Typical within Device Skew • HSTL Compatible Outputs Drive 50 to GND with no • • • • • • Offset Voltage Maximum Frequency > 750 MHz 850 ps Typical Propagation Delay Fully Compatible with Micrel SY89809L PECL and HSTL Mode Operating Range: VCCI = 3 V to 3.6 V with GND = 0 V, VCCO = 1.6 V to 2.0 V Open Input Default State Pb−Free Packages are Available © Semiconductor Components Industries, LLC, 2006 November, 2006 − Rev. 7 1 Publication Order Number: MC100EP809/D VCCO Q3 Q3 Q4 Q4 Q5 Q5 VCCO MC100EP809 24 23 22 21 20 19 18 17 VCCO 25 16 VCCO Q2 26 15 Q6 Q2 27 14 Q6 Q1 28 13 Q7 Q1 29 12 Q7 Q0 30 11 Q8 Q0 31 10 Q8 VCCO 32 MC100EP809 5 HSTL_CLK HSTL_CLK CLK_SEL LVPECL_CLK 7 8 OE 4 GND 3 6 LVPECL_CLK 2 VCCI 9 1 VCCO All VCCI, VCCO, and GND pins must be externally connected to appropriate Power Supply to guarantee proper operation (VCCI 0 VCCO). Figure 1. 32−Lead LQFP Pinout (Top View) Table 1. PIN DESCRIPTION PIN Table 2. TRUTH TABLE FUNCTION HSTL_CLK*, HSTL_CLK** HSTL or LVDS Differential Inputs LVPECL_CLK*, LVPECL_CLK** LVPECL Differential Inputs CLK_SEL** LVCMOS/LVTTL Input CLK Select OE** LVCMOS/LVTTL Output Enable Q0 − Q8, Q0 − Q8 HSTL Differential Outputs VCC1 Positive Supply_Core (3.0 V − 3.6 V) VCC0 Positive Supply_HSTL Outputs (1.6 V − 2.0 V) GND Ground OE* CLK_SEL Q0 − Q8 Q0 − Q8 L L L H L H L H H L HSTL_CLK HSTL_CLK H H LVPECL_CLK LVPECL_CLK *The OE (Output Enable) signal is synchronized with the rising edge of the HSTL_CLK and LVOCL_CLK signals. * Pins will default LOW when left open. ** Pins will default HIGH when left open. http://onsemi.com 2 MC100EP809 CLK_SEL HSTL_CLK 0 9 HSTL_CLK LVPECL_CLK VCCI GND Q0−Q8 (HSTL) 9 Q0−Q8 (HSTL) 1 LVPECL_CLK VCCO Q D OE Figure 2. Logic Diagram Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 k Internal Input Pullup Resistor ESD Protection 37.5 k Human Body Model Machine Model Charged Device Model Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) LQFP−32 Flammability Rating Oxygen Index: 28 to 34 Transistor Count > 2 kV > 200 V > 2 kV Pb Pkg Pb−Free Pkg Level 2 Level 2 UL 94 V−0 @ 0.125 in 478 Devices Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. http://onsemi.com 3 MC100EP809 Table 4. MAXIMUM RATINGS Symbol Rating Unit VCC1 Core Power Supply Parameter GND = 0 V Condition 1 VCC1 = 1.8 V Condition 2 4 V VCC0 HSTL OutputPower Supply GND = 0 V VCC0 = 3.3 V 4 V VI PECL Mode Input Voltage GND = 0 V VI v VCC1 6 V Iout Output Current Continuous Surge 50 100 mA mA TA Operating Temperature Range Tstg Storage Temperature Range JA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm JC Thermal Resistance (Junction−to−Case) Standard Board Tsol Wave Solder 0 to +85 °C −65 to +150 °C LQFP−32 LQFP−32 80 55 °C/W °C/W LQFP−32 12 to 17 °C/W 265 265 °C Pb Pb−Free Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 5. LVPECL DC CHARACTERISTICS VCCI = 3.0 V to 3.6 V; VCCO = 1.6 V to 2.0 V, GND = 0 V 0°C 25°C 85°C Characteristic Min Typ Max Min Typ Max Min Typ Max Unit ICC Core Power Supply Current 75 95 115 75 95 115 75 95 115 mA VIH Input HIGH Voltage (Single−Ended) VCCI − 1.165 VCCI − 0.88 VCCI − 1.165 VCCI − 0.88 VCCI − 1.165 VCCI − 0.88 V VIL Input LOW Voltage (Single−Ended) VCCI − 1.945 VCCI − 1.6 VCCI − 1.945 VCCI − 1.6 VCCI − 1.945 VCCI − 1.6 V VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 2) (Figure 4) LVPECL_CLK/LVPECL_CLK 1.2 VCCI 1.2 VCCI 1.2 VCCI V Symbol IIH Input HIGH Current −150 150 −150 150 −150 150 A IIL Input LOW Current −150 150 −150 150 −150 150 A NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. VIHCMR max varies 1:1 with VCCI. The VIHCMR range is referenced to the most positive side of the differential input signal. Table 6. LVTTL/LVCMOS DC CHARACTERISTICS VCCI = 3.0 V to 3.6 V; VCCO = 1.6 V to 2.0 V, GND = 0 V 0°C Symbol Characteristic Min Typ 25°C Max 2.0 Min Typ 85°C Max 2.0 Min Typ Max Input HIGH Voltage VIL Input LOW Voltage 0.8 V IIH Input HIGH Current −150 150 −150 150 −150 150 A IIL Input LOW Current −300 300 −300 300 −300 300 A 0.8 2.0 Unit VIH 0.8 V NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. http://onsemi.com 4 MC100EP809 Table 7. LVTTL/LVCMOS DC CHARACTERISTICS VCCI = 3.0 V to 3.6 V; VCCO = 1.6 V to 2.0 V, GND = 0 V 0°C Symbol Characteristic Min Typ 25°C Max Min 1.0 1.2 Typ 85°C Max Min 1.0 1.2 Typ Max Unit 1.0 1.2 V VOH Output HIGH Voltage (Note 3) VOL Output LOW Voltage (Note 3) 0.1 0.4 0.1 0.4 0.1 0.4 V VIH Input HIGH Voltage (Figure 5) VX + 0.1 1.6 VX + 0.1 1.6 VX + 0.1 1.6 V VIL Input LOW Voltage (Figure 5) −0.3 VX − 0.1 −0.3 VX − 0.1 −0.3 VX − 0.1 V VX HSTL Input Crossover Voltage 0.68 0.9 0.68 0.9 0.68 0.9 V IIH Input HIGH Current −150 150 −150 150 −150 150 A IIL Input LOW Current −300 300 −300 300 −300 300 A VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 4) HSTL_CLK/HSTL_CLK 0.6 VCCI − 1.2 0.6 VCCI − 1.2 0.6 VCCI − 1.2 V V − − − NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. All outputs loaded with 50 to GND (Figure 6). 4. VIHCMR max varies 1:1 with VCCI. The VIHCMR range is referenced to the most positive side of the differential input signal. Table 8. AC CHARACTERISTICS VCCI = 3.0 V to 3.6 V; VCCO = 1.6 V to 2.0 V, GND = 0 V (Note 5) 0°C 25°C Characteristic Min Typ VOpp Differential Output Voltage fout < 100 MHz (Figure 3) fout < 500 MHz fout < 750 MHz 600 600 450 850 750 575 tPLH tPHL Propagation Delay (Differential Configuration) LVPECL_CLK to Q HSTL_CLK to Q 680 690 800 830 930 990 tskew Within−Device Skew (Note 6) Device−to−Device Skew (Note 7) 15 100 tJITTER Random Clock Jitter (Figure 3) (RMS) 1.4 VPP Input Swing (Differential Configuration) (Note 8) (Figure 4) LVPECL HSTL 200 200 200 200 200 200 mV mV tS OE Set Up Time (Note 9) 0.5 0.5 0.5 ns tH OE Hold Time 0.5 tr/tf Output Rise/Fall Time (20% − 80%) 350 Symbol Max 85°C Min Typ Max Min Typ 600 600 450 850 750 575 700 700 820 850 950 1000 50 200 15 100 3.0 1.4 600 600 450 850 750 575 780 790 920 950 1070 1110 ps ps 50 200 15 100 50 200 ps ps 3.0 1.4 3.0 ps 0.5 600 350 Max mV mV 0.5 450 600 350 Unit ns 600 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Measured with 750 mV (LVPECL) source or 1 V (HSTL) source, 50% duty cycle clock source. All outputs loaded with 50 to GND (Figure 6). 6. Skew is measured between outputs under identical transitions and conditions on any one device. 7. Device−to−Device skew for identical transitions and conditions. 8. VPP is the Differential Input Voltage swing required to maintain AC characteristics listed herein. 9. OE Set Up Time is defined with respect to the rising edge of the clock. OE High−to−Low transition ensures outputs remain disabled during the next clock cycle. OE Low−to−High transition enables normal operation of the next input clock (Figure 8). http://onsemi.com 5 MC100EP809 900 9 800 8 VOPP 7 600 6 500 5 400 4 300 3 RMS JITTER 200 2 100 0 tJITTER ps (RMS) VOPP (mV) 700 1 0 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (MHz) Figure 3. Output Frequency (FOUT) versus Output Voltage (VOPP) and Random Clock Jitter (tJITTER) http://onsemi.com 6 MC100EP809 VCCI VCCO(HSTL) VCCI(LVPECL) VPP VIHCMR VIH(DIFF) VIH(DIFF) VX VIL(DIFF) VIL(DIFF) VPP GND Figure 4. LVPECL Differential Input Levels GND Figure 5. HSTL Differential Input Levels Z = 50 Q HSTL OUTPUT Q 50 50 GROUND Figure 6. HSTL Output Termination and AC Test Reference CLK/CLK D.C. Bias* *Must fall within 680 to 900 mV (Preferably (VIH + VIL)/2). Figure 7. HSTL Single−Ended Input Configuration CLK CLK OE Q Q Figure 8. Output Enable (OE) Timing Diagram http://onsemi.com 7 MC100EP809 ORDERING INFORMATION Package Shipping † MC100EP809FA LQFP−32 250 Units / Tray MC100EP809FAG LQFP−32 (Pb−Free) 250 Units / Tray MC100EP809FAR2 LQFP−32 2000 / Tape & Reel MC100EP809FAR2G LQFP−32 (Pb−Free) 2000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices http://onsemi.com 8 MC100EP809 PACKAGE DIMENSIONS 32 A1 A −T−, −U−, −Z− 32 LEAD LQFP CASE 873A−02 ISSUE C 4X 25 0.20 (0.008) AB T−U Z 1 AE −U− −T− B P V 17 8 BASE METAL DETAIL Y V1 AC T−U Z AE DETAIL Y ÉÉ ÉÉ ÉÉ ÉÉ 9 −Z− 4X S1 0.20 (0.008) AC T−U Z F S 8X M_ G D DETAIL AD −AB− SECTION AE−AE C E −AC− H W K X DETAIL AD Q_ 0.250 (0.010) 0.10 (0.004) AC GAUGE PLANE SEATING PLANE J R M N 9 0.20 (0.008) B1 ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC). ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 http://onsemi.com 9 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative MC100EP809/D