SN74LS76A Dual JK Flip-Flop with Set and Clear The SN74LS76A offers individual J, K, Clock Pulse, Direct Set and Direct Clear inputs. These dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The Logic Level of the J and K inputs will perform according to the Truth Table as long as minimum set-up times are observed. Input data is transferred to the outputs on the HIGH-to-LOW clock transitions. http://onsemi.com LOW POWER SCHOTTKY MODE SELECT – TRUTH TABLE INPUTS OPERATING MODE Set Reset (Clear) *Undetermined Toggle Load “0” (Reset) Load “1” (Set) Hold * OUTPUTS SD CD J K Q Q L H L H H H H H L L H H H H X X X h l h l X X X h h l l H L H q L H q L H H q H L q 16 1 PLASTIC N SUFFIX CASE 648 Both outputs will be HIGH while both SD and CD are LOW, but the output states are unpredictable if SD and CD go HIGH simultaneously. H, h = HIGH Voltage Level L, I = LOW Voltage Level X = Immaterial l, h (q) = Lower case letters indicate the state of the referenced input 16 i, h (q) = (or output) one setup time prior to the HIGH–to–LOW clock transition 1 SOIC D SUFFIX CASE 751B GUARANTEED OPERATING RANGES Symbol VCC Parameter Supply Voltage Min Typ Max Unit 4.75 5.0 5.25 V 0 25 70 °C TA Operating Ambient Temperature Range IOH Output Current – High – 0.4 IOL Output Current – Low 8.0 Semiconductor Components Industries, LLC, 1999 December, 1999 – Rev. 6 1 ORDERING INFORMATION Device Package Shipping mA SN74LS76AN 16 Pin DIP 2000 Units/Box mA SN74LS76AD 16 Pin 2500/Tape & Reel Publication Order Number: SN74LS76A/D SN74LS76A LOGIC DIAGRAM LOGIC SYMBOL 2 Q Q CLEAR (CD) 16 K 1 CP 4 J C Q D SET (SD) K J SD 7 Q 15 11 6 CP 9 J C Q D 10 K 14 SD Q 12 3 8 VCC = PIN 5 GND = PIN 13 CLOCK (CP) DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH Input HIGH Voltage VIL Input LOW Voltage VIK Input Clamp Diode Voltage VOH Output HIGH Voltage VOL O Output LOW Voltage IIH Min Parameter Typ Max 2.0 0.8 – 0.65 2.7 – 1.5 3.5 Unit Test Conditions V Guaranteed Input HIGH Voltage for All Inputs V Guaranteed Input LOW Voltage for All Inputs V VCC = MIN, IIN = – 18 mA V VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table VCC = VCC MIN, VIN = VIL or VIH per Truth Table 0.25 0.4 V IOL = 4.0 mA 0.35 0.5 V IOL = 8.0 mA J, K Clear Clock 20 60 80 µA VCC = MAX, VIN = 2.7 V J, K Clear Clock 0.1 0.3 0.4 mA VCC = MAX, VIN = 7.0 V – 0.4 – 0.8 mA VCC = MAX, VIN = 0.4 V –100 mA VCC = MAX 6.0 mA VCC = MAX Input HIGH Current IIL Input LOW Current IOS Short Circuit Current (Note 1) ICC Power Supply Current J, K Clear, Clock – 20 Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V) Limits Symbol Parameter fMAX Maximum Clock Frequency tPLH tPHL Clock Clear Clock, Clear, Set to Output Min Typ 30 45 Max Unit Test Conditions MHz 15 20 ns 15 20 ns Max Unit VCC = 5.0 50V CL = 15 pF F AC SETUP REQUIREMENTS (TA = 25°C) Limits Symbol Parameter Min Typ tW Clock Pulse Width High 20 ns tW Clear Set Pulse Width 25 ns ts Setup Time 20 ns th Hold Time 0 ns http://onsemi.com 2 Test Conditions VCC = 5 5.0 0V SN74LS76A PACKAGE DIMENSIONS N SUFFIX PLASTIC PACKAGE CASE 648–08 ISSUE R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. –A– 16 9 1 8 B F C DIM A B C D F G H J K L M S L S SEATING PLANE –T– K H G D M J 16 PL 0.25 (0.010) T A M M INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 D SUFFIX PLASTIC SOIC PACKAGE CASE 751B–05 ISSUE J –A– 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 –B– 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C –T– SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A S http://onsemi.com 3 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 SN74LS76A ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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