SN74LS240, SN74LS244 Octal Buffer/Line Driver with 3-State Outputs The SN74LS240 and SN74LS244 are Octal Buffers and Line Drivers designed to be employed as memory address drivers, clock drivers and bus-oriented transmitters/receivers which provide improved PC board density. http://onsemi.com • Hysteresis at Inputs to Improve Noise Margins • 3-State Outputs Drive Bus Lines or Buffer Memory Address LOW POWER SCHOTTKY Registers • Input Clamp Diodes Limit High-Speed Termination Effects MARKING DIAGRAMS GUARANTEED OPERATING RANGES Symbol VCC Parameter Supply Voltage TA Operating Ambient Temperature Range IOH Output Current – High IOL Output Current – Low Min Typ Max Unit 4.75 5.0 5.25 V 0 25 70 °C –3.0 mA –15 mA 24 mA SN74LS24xN AWLYYWW 1 20 1 PDIP–20 N SUFFIX CASE 738 LS24x AWLYYWW 20 1 1 SOIC–20 DW SUFFIX CASE 751D x A WL YY WW = 0 or 4 = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION Device Semiconductor Components Industries, LLC, 2000 August, 2000 – Rev. 7 1 Package Shipping SN74LS240N PDIP–20 1440 Units/Box SN74LS240DW SOIC–20 2500/Tape & Reel SN74LS244N PDIP–20 1440 Units/Box SN74LS244DW SOIC–20 2500/Tape & Reel Publication Order Number: SN74LS240/D SN74LS240, SN74LS244 LOGIC AND CONNECTION DIAGRAMS DIP (TOP VIEW) SN74LS240 VCC 2G 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1 20 19 18 17 1 1G 2 1A1 3 4 5 2Y4 1A2 2Y3 VCC 2G 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1 20 19 18 17 1 1G 2 1A1 3 4 5 2Y4 1A2 2Y3 16 15 14 13 12 11 6 8 9 10 7 1A3 2Y2 1A4 2Y1 GND SN74LS244 16 15 14 13 12 11 6 8 9 10 7 1A3 2Y2 1A4 2Y1 GND TRUTH TABLES SN74LS244 SN74LS240 INPUTS INPUTS OUTPUT 1G, 2G D L L H L H X OUTPUT H L (Z) H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = HIGH Impedance http://onsemi.com 2 1G, 2G D L L H L H X L H (Z) SN74LS240, SN74LS244 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Min Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VT+–VT– Hysteresis VIK Input Clamp Diode Voltage 0.8 VOL Output LOW Voltage IOZH IOZL 0.4 –0.65 2.4 Output HIGH Voltage Max 2.0 0.2 VOH Typ –1.5 3.4 2.0 Unit Test Conditions V Guaranteed Input HIGH Voltage for All Inputs V Guaranteed Input LOW Voltage for All Inputs V VCC = MIN V VCC = MIN, IIN = –18 mA V VCC = MIN, IOH = –3.0 mA V VCC = MIN, IOH = MAX VCC = VCC MIN, VIN = VIL or VIH per Truth Table 0.25 0.4 V IOL = 12 mA 0.35 0.5 V IOL = 24 mA Output Off Current HIGH 20 µA VCC = MAX, VOUT = 2.7 V Output Off Current LOW –20 µA VCC = MAX, VOUT = 0.4 V 20 µA VCC = MAX, VIN = 2.7 V 0.1 mA VCC = MAX, VIN = 7.0 V –0.2 mA VCC = MAX, VIN = 0.4 V –225 mA VCC = MAX mA VCC = MAX IIH Input HIGH Current IIL Input LOW Current IOS Output Short Circuit Current (Note 1.) –40 Power Supply Current Total, Output HIGH Total, Output LOW ICC Total at HIGH Z 27 LS240 44 LS244 46 LS240 50 LS244 54 1. Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V) Limits Symbol Parameter Min Typ Max Unit tPLH tPHL Propagation Delay, Data to Output LS240 9.0 12 14 18 ns tPLH tPHL Propagation Delay, Data to Output LS244 12 12 18 18 ns tPZH Output Enable Time to HIGH Level 15 23 ns tPZL Output Enable Time to LOW Level 20 30 ns tPLZ Output Disable Time from LOW Level 15 25 ns tPHZ Output Disable Time from HIGH Level 10 18 ns http://onsemi.com 3 Test Conditions CL = 45 pF, RL = 667 Ω CL = 5.0 pF, F, RL = 667 Ω SN74LS240, SN74LS244 AC WAVEFORMS VIN 1.3 V 1.3 V tPLH VOUT VCC tPHL 1.3 V 1.3 V RL SW1 Figure 1. TO OUTPUT UNDER TEST VIN 1.3 V VOUT 1.3 V tPHL tPLH 1.3 V 1.3 V 5 kΩ CL* SW2 Figure 2. VE 1.3 V VE 1.3 V VOUT SWITCH POSITIONS tPLZ tPZL 1.3 V 0.5 V SYMBOL ≈ 1.3 V VOL Figure 3. SW1 SW2 tPZH Open Closed tPZL Closed Open tPLZ Closed Closed tPHZ Closed Closed Figure 5. VE 1.3 V VE tPZH VOUT 1.3 V 1.3 V tPHZ ≥VOH ≈ 1.3 V 0.5 V Figure 4. http://onsemi.com 4 SN74LS240, SN74LS244 PACKAGE DIMENSIONS N SUFFIX PLASTIC PACKAGE CASE 738–03 ISSUE E –A– 20 11 1 10 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. B L C –T– K SEATING PLANE M N E G F J D 0.25 (0.010) 20 PL 0.25 (0.010) 20 PL M T A M http://onsemi.com 5 M T B M DIM A B C D E F G J K L M N INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0 15 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0 15 0.51 1.01 SN74LS240, SN74LS244 D SUFFIX PLASTIC SOIC PACKAGE CASE 751D–05 ISSUE F A 20 X 45 h 1 10 20X B B 0.25 M T A S B S A L H M E 0.25 10X NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. 11 B M D 18X e A1 SEATING PLANE C T http://onsemi.com 6 DIM A A1 B C D E e H h L MILLIMETERS MIN MAX 2.35 2.65 0.10 0.25 0.35 0.49 0.23 0.32 12.65 12.95 7.40 7.60 1.27 BSC 10.05 10.55 0.25 0.75 0.50 0.90 0 7 SN74LS240, SN74LS244 Notes http://onsemi.com 7 SN74LS240, SN74LS244 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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